JPH1183933A - Inspection method for ic chip - Google Patents

Inspection method for ic chip

Info

Publication number
JPH1183933A
JPH1183933A JP9240106A JP24010697A JPH1183933A JP H1183933 A JPH1183933 A JP H1183933A JP 9240106 A JP9240106 A JP 9240106A JP 24010697 A JP24010697 A JP 24010697A JP H1183933 A JPH1183933 A JP H1183933A
Authority
JP
Japan
Prior art keywords
chip
connection
electrodes
evaluation
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9240106A
Other languages
Japanese (ja)
Inventor
Shinichi Hoshino
真一 星野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP9240106A priority Critical patent/JPH1183933A/en
Publication of JPH1183933A publication Critical patent/JPH1183933A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • H01L2224/73104Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain an inspection method in which an electrode is connected surely when an IC chip mounted on a circuit board by a resin, for connection, containing conductive particles is removed so as to be remounted on an evaluation board and in which the reliability of an inspection is enhanced by using the evaluation board whose electrode is formed to be protrusion-shaped. SOLUTION: An evaluation board 6a which is used for an IC chip inspection is constituted in such a way that, e.g. bump electrodes 3 are formed on a glass board 7 on which a conductor pattern 8 is formed. The electrodes 3 are installed in positions faced with bump electrodes 2 on an inspected IC chip, which is removed from a circuit board and to which a resin 4a for connection is stuck. Then, a resin 4b, for connection, which contains conductive particles 5b is arranged between the evaluation board 6a and the IC chip 1, it is heated and pressurized by using a heating and pressurization head or the like, and the IC chip 1 is connected to the evaluation board 6a. By this constitution, a pressure is applied so as to be concentrated between the electrodes 2 and the electrodes 3, a load is not applied to other places, a short circuit or the like can be suppressed, and a stable inspection can be executed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、導電粒子を含んだ
接続用樹脂を用いて回路基板に実装した突起電極付きI
Cチップを回路基板から取り外し、評価基板に再実装し
て前記ICチップの機能を検査するICチップ検査方法
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an I-shaped semiconductor device having a protruding electrode mounted on a circuit board using a connecting resin containing conductive particles.
The present invention relates to an IC chip inspection method for removing a C chip from a circuit board, re-mounting the C chip on an evaluation board, and inspecting the function of the IC chip.

【0002】[0002]

【従来の技術】ICチップをプリント基板やガラス基板
等の回路基板に直接実装する技術は、使用される機器の
小型化や、ICチップの駆動周波数の高速化、また接続
コストの低減化などに伴いさまざまな電子機器に用いら
れている。
2. Description of the Related Art The technology of directly mounting an IC chip on a circuit board such as a printed circuit board or a glass substrate is used to reduce the size of equipment used, increase the driving frequency of the IC chip, and reduce the connection cost. Accordingly, it is used in various electronic devices.

【0003】中でも液晶表示パネルでは、液晶駆動用I
Cチップをガラス基板に直接実装することで、コンパク
トでかつ対振動性も向上するため、液晶表示装置の特徴
である携帯性がさらに増すことになり、この接続方法が
主流になりつつある。この接続方法はガラス基板の上に
直接ICチップを実装することから、COG(Chip
On Glass)方式と呼ばれている。
In particular, in a liquid crystal display panel, a liquid crystal driving I
By directly mounting the C chip on a glass substrate, the compactness and the anti-vibration property are improved, so that the portability, which is a feature of the liquid crystal display device, is further increased, and this connection method is becoming mainstream. In this connection method, since an IC chip is directly mounted on a glass substrate, COG (Chip)
On Glass) method.

【0004】ICチップを回路基板に直接実装する方法
は、数種類の方法が考案されており、その一例を以下に
示す。図3は、ICチップと回路基板との接続方法を示
す。
Several methods have been devised for directly mounting an IC chip on a circuit board, examples of which are described below. FIG. 3 shows a method of connecting an IC chip to a circuit board.

【0005】ICチップ1には突起電極2が形成されて
おり、ICチップ1を接続する回路基板14には、突起
電極2と対向する位置に電極1が形成されている。IC
チップ1と回路基板14との間には、導電粒子5aを含
んだエポキシ系樹脂を主成分とする熱硬化性樹脂12a
をシート状に形成した接続用樹脂4aが配置されてい
る。
A protruding electrode 2 is formed on the IC chip 1, and the electrode 1 is formed on a circuit board 14 connecting the IC chip 1 at a position facing the protruding electrode 2. IC
A thermosetting resin 12a mainly composed of an epoxy resin containing conductive particles 5a is provided between the chip 1 and the circuit board 14.
Is formed in a sheet shape.

【0006】ICチップ1と回路基板14とを接続する
際には、突起電極2と電極13とを位置合わせした後、
ICチップ1を加熱加圧ヘッド11にて加熱加圧し、接
続用樹脂4aを硬化させる。
When connecting the IC chip 1 and the circuit board 14, after the projecting electrodes 2 and the electrodes 13 are aligned,
The IC chip 1 is heated and pressed by the heating and pressing head 11 to cure the connection resin 4a.

【0007】図4は、接続用樹脂4aを硬化させた後の
接続部の断面を示す。導電粒子5aを含んだ熱硬化性樹
脂12aは、加熱により一旦粘度が低下しさらに加圧時
の圧力で押し出されるため、ICチップ1からはみ出し
てICチップ1の側面と回路基板14との間にフィレッ
トのような形状を形成した状態で硬化する。
FIG. 4 shows a cross section of the connection portion after the connection resin 4a is cured. The thermosetting resin 12a containing the conductive particles 5a once lowers in viscosity by heating and is extruded by the pressure at the time of pressurization. It cures while forming a fillet-like shape.

【0008】[0008]

【発明が解決しようとする課題】上述のようにICチッ
プ1は回路基板14に実装されるのであるが、接続後に
このICチップ1に何らかの問題が生じた場合には、I
Cチップ1を回路基板14から取り外してその性能を検
査することが必要になる。
As described above, the IC chip 1 is mounted on the circuit board 14, but if any problem occurs in the IC chip 1 after the connection, the IC chip 1
It is necessary to remove the C chip 1 from the circuit board 14 and inspect its performance.

【0009】従来より、ICチップ1の機能を検査する
方法としてワイヤーボンディングを用いたバーイン検査
手法が行われていたが、この検査手法は作業工数がかか
り、また設備コストも高いといった問題があった。さら
に、ワイヤー部の信頼性が十分確保されていないため、
ICチップ1の高温高湿あるいは低温動作での信頼性の
確認ができないという問題もあった。
Conventionally, as a method for inspecting the function of the IC chip 1, a burn-in inspection method using wire bonding has been performed. However, this inspection method has a problem that it requires a large number of work steps and a high equipment cost. . Furthermore, since the reliability of the wire part is not sufficiently secured,
There is also a problem that the reliability of the IC chip 1 in high-temperature, high-humidity or low-temperature operation cannot be confirmed.

【0010】図5は、回路基板14に実装したICチッ
プ1を回路基板14から取り外した状態を示す。回路基
板14からICチップ1を取り外す際には、ICチップ
1を加熱して接続用樹脂を軟化させる方法が一般的であ
る。
FIG. 5 shows a state where the IC chip 1 mounted on the circuit board 14 is removed from the circuit board 14. When removing the IC chip 1 from the circuit board 14, a method of heating the IC chip 1 to soften the connection resin is general.

【0011】ICチップ1の表面は突起電極2が形成さ
れているため凸形状となり、一方、回路基板14の表面
は電極13は形成されているもののほぼフラットな状態
となっているため、接続用樹脂4aのほとんどがICチ
ップ1の方に付着してICチップ1が取り外され、IC
チップ1に形成された突起電極2の表面は、接続用樹脂
4aによって覆われた状態となる。
The surface of the IC chip 1 has a convex shape due to the formation of the protruding electrodes 2, while the surface of the circuit board 14 has the electrodes 13 formed but is almost flat, so that the connection Most of the resin 4a adheres to the IC chip 1 and the IC chip 1 is removed.
The surface of the protruding electrode 2 formed on the chip 1 is covered with the connection resin 4a.

【0012】このように接続用樹脂4aにて覆われたI
Cチップ1の性能を検査する方法としては、図6に示す
ように、ICチップ1の突起電極2にニードル16を接
触させる方法がある。
The I covered with the connecting resin 4a as described above
As a method of inspecting the performance of the C chip 1, there is a method of bringing the needle 16 into contact with the protruding electrode 2 of the IC chip 1, as shown in FIG.

【0013】すなわち、ICチップ1の入力側突起電極
2aより電気信号16aを入力し、ICチップ1の出力
側突起電極2bより電気信号16bを検出してICチッ
プの性能を検査する方法である。
That is, this is a method of inspecting the performance of an IC chip by inputting an electric signal 16a from an input-side protruding electrode 2a of the IC chip 1 and detecting an electric signal 16b from an output-side protruding electrode 2b of the IC chip 1.

【0014】しかしながらこの検査方法では、ICチッ
プ1の突起電極2の間のピッチが非常に狭い時には、I
Cチップ1の全ての突起電極2にニードル15を当てる
のが困難であるため、選択的に当てることになる。また
検査に用いるニードル15は、非常に細いため取り扱い
に注意を要し、摩耗しやすく、しかも非常に高価なもの
であるためコスト面で手軽に検査することが困難であっ
た。
However, according to this inspection method, when the pitch between the protruding electrodes 2 of the IC chip 1 is very narrow, I
Since it is difficult to apply the needles 15 to all the protruding electrodes 2 of the C chip 1, they are selectively applied. In addition, the needle 15 used for the inspection is very thin and requires careful handling, is easily worn, and is very expensive, so that it is difficult to easily perform the inspection in terms of cost.

【0015】また上記方法とは別に、接続用樹脂4aに
覆われたICチップ1を、図7に示すようにほぼフラッ
トな表面を有する評価基板6bに再び実装して検査する
方法がある。
In addition to the above-mentioned method, there is a method of mounting the IC chip 1 covered with the connection resin 4a again on an evaluation board 6b having a substantially flat surface as shown in FIG.

【0016】まず、回路基板14より取り外され表面を
接続用樹脂4aに覆われたICチップ1と、電極13の
形成された評価基板6bとの間に、導電粒子5bを含む
別の接続用樹脂4bを配置する。ICチップ1の突起電
極2と、評価基板6bの電極17とを位置合せして、加
熱加圧ヘッド11にて加熱加圧する。
First, another connecting resin containing conductive particles 5b is provided between the IC chip 1 which is removed from the circuit board 14 and whose surface is covered with the connecting resin 4a, and the evaluation board 6b on which the electrodes 13 are formed. 4b is arranged. The protruding electrode 2 of the IC chip 1 and the electrode 17 of the evaluation substrate 6b are aligned, and heated and pressed by the heating and pressing head 11.

【0017】このようにして評価基板6bに実装された
ICチップ1は、その機能を評価されるのであるが、I
Cチップ1にこびり付いた接続用樹脂5aが邪魔をし
て、接続用樹脂4bの導電粒子5bがICチップ1の突
起電極2と接触しにくく、突起電極2と評価基板6bに
形成された電極17とのコンタクトがとれないという問
題があった。
The function of the IC chip 1 mounted on the evaluation board 6b in this way is evaluated.
The connection resin 5a sticking to the C chip 1 hinders the conductive particles 5b of the connection resin 4b from contacting the protruding electrodes 2 of the IC chip 1 easily. There was a problem that it was not possible to contact with.

【0018】また、加熱加圧ヘッド11にてICチップ
1を加圧すると、ICチップ1の突起電極2と評価基板
6bの電極17との間で導電粒子5bに圧力がかかり、
導電粒子5bが潰れることで導電性が発揮される。その
際、突起電極2の周囲に付着した接続用樹脂4aを介し
てICチップ1と電極17との間においても導電粒子5
bに圧力がかかりやすくなるため、導電粒子5bに潰れ
が生じやすくなり、突起電極2どうしの間で隣接ショー
トを起こしやすいといった問題もあった。
When the IC chip 1 is pressed by the heating / pressing head 11, pressure is applied to the conductive particles 5b between the protruding electrodes 2 of the IC chip 1 and the electrodes 17 of the evaluation substrate 6b.
The conductivity is exhibited when the conductive particles 5b are crushed. At this time, the conductive particles 5 are also provided between the IC chip 1 and the electrode 17 via the connection resin 4a attached around the bump electrode 2.
Since the pressure is easily applied to b, the conductive particles 5b are likely to be crushed, and there is also a problem that the adjacent electrodes are likely to be short-circuited between the protruding electrodes 2.

【0019】本発明は前記問題点を解決し、ICチップ
の突起電極と評価基板の電極との接続を安定かつ確実に
し、ICチップの性能評価の信頼性を高め、低コストで
行えるICチップ検査方法を提供することを目的とす
る。
The present invention solves the above problems, stably and reliably connects the protruding electrodes of the IC chip to the electrodes of the evaluation board, increases the reliability of the performance evaluation of the IC chip, and can perform the IC chip inspection at low cost. The aim is to provide a method.

【0020】[0020]

【課題を解決するための手段】本発明のICチップ検査
方法は、特殊な形状の評価基板を用いたことを特徴とす
る。
An IC chip inspection method according to the present invention is characterized in that an evaluation board having a special shape is used.

【0021】この本発明によると、ICチップの突起電
極と評価基板の電極との接続が確実になり、信頼性の高
いICチップの性能検査を低コストにて行うことができ
る。
According to the present invention, the connection between the protruding electrode of the IC chip and the electrode of the evaluation board is ensured, and a highly reliable performance test of the IC chip can be performed at low cost.

【0022】[0022]

【発明の実施の形態】請求項1記載のICチップ検査方
法は、導電粒子を含んだ接続用樹脂を用いて回路基板に
実装した突起電極付きICチップを回路基板から取り外
し、評価基板に再実装して前記ICチップの機能を検査
するに際し、前記評価基板には、前記ICチップに形成
された突起電極と対向する形状の突起電極が形成された
ものを用い、評価基板の突起電極と、前記ICチップに
形成された突起電極とを、導電粒子を含んだ接続用樹脂
を用いて接続してICチップの機能を検査することを特
徴とする。
According to a first aspect of the present invention, there is provided an IC chip inspection method, wherein an IC chip having a protruding electrode mounted on a circuit board using a connection resin containing conductive particles is removed from the circuit board and re-mounted on an evaluation board. When testing the function of the IC chip, the evaluation substrate is formed with a projection electrode having a shape facing the projection electrode formed on the IC chip. The method is characterized in that the function of the IC chip is inspected by connecting the protruding electrodes formed on the IC chip with a connection resin containing conductive particles.

【0023】この構成によると、ICチップの突起電極
と評価基板の突起電極との接続が確実になり、しかもI
Cチップの突起電極どうしの間でショートが生じたりす
ることがなくなるため、安定的にしかも信頼性の高いI
Cチップ検査を行える。
According to this structure, the connection between the protruding electrode of the IC chip and the protruding electrode of the evaluation board is ensured.
Since a short circuit does not occur between the projecting electrodes of the C chip, a stable and highly reliable I
C chip inspection can be performed.

【0024】請求項2記載のICチップ検査方法は、請
求項1において、評価基板がガラス基板であることを特
徴とする。この構成によると、評価基板をガラス基板と
することでICチップと評価基板との接続状態を評価基
板の裏側より確認することができ、しかもコスト面でも
低コストとすることができる。
According to a second aspect of the present invention, there is provided an IC chip inspection method according to the first aspect, wherein the evaluation substrate is a glass substrate. According to this configuration, when the evaluation substrate is a glass substrate, the connection state between the IC chip and the evaluation substrate can be checked from the back side of the evaluation substrate, and the cost can be reduced.

【0025】以下、本発明の実施の形態について、図
1、図2を用いて説明する。なお前記従来例を示す図3
〜図7と同様をなすものには同一の符号をつけて説明す
る。 (実施の形態)図1、図2は本発明の(実施の形態)を
示す。
An embodiment of the present invention will be described below with reference to FIGS. FIG. 3 shows the conventional example.
7 that are the same as those shown in FIG. (Embodiment) FIGS. 1 and 2 show (embodiment) of the present invention.

【0026】図1に示すように、導体パターン8の形成
されたガラス基板7に、突起電極3が形成されて評価基
板6aが構成されている。この突起電極3は、ICチッ
プ1に形成された突起電極2と対向する位置に設けられ
ている。
As shown in FIG. 1, a protruding electrode 3 is formed on a glass substrate 7 on which a conductor pattern 8 is formed to form an evaluation substrate 6a. The projecting electrode 3 is provided at a position facing the projecting electrode 2 formed on the IC chip 1.

【0027】このように構成された評価基板6aと、回
路基板14から取り外され接続用樹脂4aが付着したI
Cチップ1との間に、導電粒子5bを含むシート状の接
続用樹脂4bを配置し、加熱加圧ヘッド11により加熱
加圧する。
The evaluation board 6a having the above-described structure and the I to which the connection resin 4a has been removed from the circuit board 14 are attached.
A sheet-shaped connection resin 4b containing conductive particles 5b is arranged between the C-chip 1 and heated and pressed by the heating and pressing head 11.

【0028】このような構成でICチップ1を評価基板
6aに接続すると、図2に示すように、圧力は突起電極
2と突起電極3との間に集中してかかるようになり、そ
の外の部分には負荷がかかりにくくなる。
When the IC chip 1 is connected to the evaluation board 6a in such a configuration, as shown in FIG. 2, the pressure is concentrated between the protruding electrodes 2 and the protruding electrodes 3, and the pressure is applied to the outside. The portion is less likely to be loaded.

【0029】そのため、突起電極2と突起電極3との間
では、接続用樹脂4bに含まれた導電粒子5bが潰れて
突起電極2と突起電極3との接続が可能となり、安定し
てICチップ1の機能を検査することができる。また、
それ以外の部分では導電粒子5bの潰れや、ICチップ
1の隣接し合う突起電極2の間での隣接ショートを抑え
ることができ、コンタクトの安定化及び向上を図ること
ができる。
Therefore, between the protruding electrodes 2 and the protruding electrodes 3, the conductive particles 5b contained in the connection resin 4b are crushed, so that the protruding electrodes 2 and the protruding electrodes 3 can be connected to each other. One function can be tested. Also,
In other portions, the crushing of the conductive particles 5b and the adjacent short circuit between the adjacent protruding electrodes 2 of the IC chip 1 can be suppressed, and the contact can be stabilized and improved.

【0030】上記(実施の形態)におけるICチップの
検査方法の具体例を以下に示す。 (実施例1)上記(実施の形態)において、ICチップ
1のサイズを12mm×2.5mmとし、その接続面側
には電解メッキ法で高さが15μm、面積が100μm
×50μmである突起電極3を形成した。
A specific example of the IC chip inspection method in the above (embodiment) will be described below. (Example 1) In the above (embodiment), the size of the IC chip 1 is 12 mm × 2.5 mm, and the connection surface side has a height of 15 μm and an area of 100 μm by electrolytic plating.
The projection electrode 3 having a size of × 50 μm was formed.

【0031】またICチップ1の突起電極2には、一度
硬化した接続用樹脂4aがICチップ1の表面から10
〜18μmの厚さで突起電極2を覆うように付着させ
た。評価基板6aには、反りが0.05mm/470m
mで、グレードが無アルカリであるガラス基板7を使用
し、その上に配線抵抗値の低いアルミニウム(Al)を
スパッタリングで成膜させ導体パターン8を形成したも
のを用いた。さらに、導体パターン8上には、ICチッ
プ1の突起電極2と向かい合うように突起起電極3をチ
タン層からなるバリアメタル9の上に金(Au)をメッ
キで10μm堆積させた。
On the protruding electrodes 2 of the IC chip 1, the connection resin 4a which has been hardened once is
It was attached so as to cover the protruding electrode 2 with a thickness of about 18 μm. The evaluation substrate 6a has a warp of 0.05 mm / 470 m.
m, a glass substrate 7 having a non-alkali grade was used, and a conductor pattern 8 was formed by forming a film of aluminum (Al) having a low wiring resistance by sputtering on the glass substrate 7. Further, on the conductor pattern 8, gold (Au) was deposited by plating to a thickness of 10 μm on the barrier metal 9 made of a titanium layer so as to face the bump electrode 2 of the IC chip 1.

【0032】突起電極3のサイズは110μm×60μ
mにし、接続時の位置ズレを考慮しマージンを保たせ
た。また、導体パターン8の保護のため、突起電極3以
外の箇所に窒化膜(SiNx)を成膜させ導体パターン
8の保護膜10を施した。
The size of the protruding electrode 3 is 110 μm × 60 μm.
m, and a margin was kept in consideration of positional deviation at the time of connection. Further, in order to protect the conductor pattern 8, a nitride film (SiNx) was formed on a portion other than the protruding electrode 3, and a protective film 10 for the conductor pattern 8 was provided.

【0033】ICチップ1と評価基板6aとを接続する
接続用樹脂4bは、樹脂ボールに金メッキを施した直径
5μmの導電粒子5bを5000±1500個/mm2
の範囲で分散させたエポキシ系熱硬化性樹脂12bを、
厚さ23μmのシート状に形成したものを用いた。
The connection resin 4b for connecting the IC chip 1 and the evaluation board 6a is composed of 5000 ± 1500 conductive particles 5b having a diameter of 5 μm and a resin ball plated with gold and having a diameter of 5000 ± 1500 / mm 2.
Epoxy thermosetting resin 12b dispersed in the range of
A sheet formed into a sheet having a thickness of 23 μm was used.

【0034】上記のように構成されたICチップ1と評
価基板6aと間にシート状の接続用樹脂4bを配置し、
突起電極2と突起電極3とを位置あわせして加熱加圧ヘ
ッド11にてICチップ1を加熱加圧した。
A sheet-like connecting resin 4b is arranged between the IC chip 1 configured as described above and the evaluation board 6a,
The projecting electrode 2 and the projecting electrode 3 were aligned with each other, and the IC chip 1 was heated and pressed by the heating / pressing head 11.

【0035】得られたICチップ1と評価基板6aとの
接続体は、評価基板6aに突起電極3が設けられていた
ため、加熱加圧したときにICチップ1の突起電極2と
評価基板6aの突起電極3の間のみに圧力の負荷が集中
し、それ以外の箇所には負荷がかかりにくくなった。
The obtained connection body between the IC chip 1 and the evaluation board 6a was provided with the protruding electrodes 3 on the evaluation board 6a. The pressure load was concentrated only between the protruding electrodes 3, and the load was hardly applied to other portions.

【0036】その効果、突起電極2と突起電極3との間
では導電粒子5bが潰れて電極間の接続が可能となり、
それ以外の部分では導電粒子5bの潰れや、ICチップ
1の隣接し合う突起電極2の間での隣接ショートが抑え
られ、コンタクトの安定化及び向上を得ることができ、
信頼性ある検査を行うことができた。
The effect is that the conductive particles 5b are crushed between the protruding electrodes 2 and 3, and the connection between the electrodes becomes possible.
In other portions, the collapse of the conductive particles 5b and the adjacent short circuit between the adjacent protruding electrodes 2 of the IC chip 1 are suppressed, and the contact can be stabilized and improved.
A reliable test could be performed.

【0037】[0037]

【発明の効果】以上のように本発明のICチップ検査方
法によれば、評価基板の電極を突起型にすることによ
り、回路基板から取り外し一度硬化した接続用樹脂が付
着したICチップを再度、評価基板に接続用樹脂を用い
て接続してもICチップの突起電極と評価基板の電極と
のコンタクトが安定してとれ、信頼性のあるICチップ
の検査を行うことができ、かつコスト的にも従来より低
く抑えることができる。
As described above, according to the IC chip inspection method of the present invention, the electrodes of the evaluation board are formed in the form of projections, so that the IC chip to which the connection resin once hardened and adhered is removed again. Even when connection is made to the evaluation substrate using a connection resin, the contact between the protruding electrode of the IC chip and the electrode of the evaluation substrate can be stably obtained, and a reliable inspection of the IC chip can be performed. Can also be kept lower than before.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(実施の形態)におけるICチップと評価基板
との接続方法を示す断面図
FIG. 1 is a cross-sectional view illustrating a method for connecting an IC chip and an evaluation substrate in an embodiment.

【図2】(実施の形態)におけるICチップと評価基板
との接続部の断面図
FIG. 2 is a cross-sectional view of a connection portion between an IC chip and an evaluation board in the embodiment.

【図3】従来のICチップと回路基板との接続方法を示
す断面図
FIG. 3 is a sectional view showing a conventional method for connecting an IC chip to a circuit board.

【図4】従来のICチップと回路基板との接続部の状態
の断面図
FIG. 4 is a cross-sectional view of a state of a connection portion between a conventional IC chip and a circuit board.

【図5】従来のICチップと評価基板との接続方法を示
す断面図
FIG. 5 is a sectional view showing a conventional method for connecting an IC chip to an evaluation board.

【図6】従来の回路基板から取り外したICチップの断
面図
FIG. 6 is a cross-sectional view of an IC chip detached from a conventional circuit board.

【図7】従来のICチップと評価基板との接続部の断面
FIG. 7 is a sectional view of a connection portion between a conventional IC chip and an evaluation board.

【符号の説明】[Explanation of symbols]

1 ICチップ 2 突起電極 3 突起電極 4a,4b 接続用樹脂 5a,5b 導電粒子 6a,6b 評価基板 DESCRIPTION OF SYMBOLS 1 IC chip 2 Projecting electrode 3 Projecting electrode 4a, 4b Connection resin 5a, 5b Conductive particle 6a, 6b Evaluation board

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】導電粒子を含んだ接続用樹脂を用いて回路
基板に実装した突起電極付きICチップを回路基板から
取り外し、評価基板に再実装して前記ICチップの機能
を検査するに際し、 前記評価基板には、前記ICチップに形成された突起電
極と対向する形状の突起電極が形成されたものを用い、 評価基板の突起電極と、前記ICチップに形成された突
起電極とを、導電粒子を含んだ接続用樹脂を用いて接続
してICチップの機能を検査するICチップ検査方法。
When the IC chip with a protruding electrode mounted on a circuit board using a connection resin containing conductive particles is removed from the circuit board and re-mounted on an evaluation board to test the function of the IC chip, As the evaluation substrate, a projection electrode having a shape facing the projection electrode formed on the IC chip is used. The projection electrode on the evaluation substrate and the projection electrode formed on the IC chip are electrically conductive particles. IC chip inspection method for inspecting the function of an IC chip by connecting using a connection resin containing the same.
【請求項2】評価基板がガラス基板である請求項1記載
のICチップ検査方法。
2. The IC chip inspection method according to claim 1, wherein the evaluation substrate is a glass substrate.
JP9240106A 1997-09-05 1997-09-05 Inspection method for ic chip Pending JPH1183933A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9240106A JPH1183933A (en) 1997-09-05 1997-09-05 Inspection method for ic chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9240106A JPH1183933A (en) 1997-09-05 1997-09-05 Inspection method for ic chip

Publications (1)

Publication Number Publication Date
JPH1183933A true JPH1183933A (en) 1999-03-26

Family

ID=17054586

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9240106A Pending JPH1183933A (en) 1997-09-05 1997-09-05 Inspection method for ic chip

Country Status (1)

Country Link
JP (1) JPH1183933A (en)

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