KR20100081624A - Semiconductor chip having bump of high density and method for fabricating the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip having a high density of bumps and a method of manufacturing the same. In the semiconductor chip having a plurality of bumps for connecting the integrated electric circuit and the integrated electric circuit electrically, each bump Is composed of first and second bump portions having different widths, and the first and second bump portions are alternately arranged in a row to face each other on the semiconductor chip such that the first and second bump portions are alternately positioned on the same line, and each bump is arranged in the nth order. The bumps are alternately arranged to be spaced apart from each other so as to be spaced apart from each other so that the second bumps of the bumps arranged n + 1th are disposed between the first bumps of the bumps. Bump pitch can be effectively refined, more accurate and easier probe test as well as easier assembly This has the effect of performing assembly.

Description

A semiconductor chip having a bump disposed at a high density, and a manufacturing method therefor {SEMICONDUCTOR CHIP HAVING BUMP OF HIGH DENSITY AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip, and more particularly, to effectively reduce the size of a semiconductor chip and to refine a bump pitch, and to perform a probe test more accurately and easily. In addition, the present invention relates to a semiconductor chip having a bump disposed at a high density so that assembly can be performed more easily, and a method of manufacturing the same.

Recently, with the rapid development of the information society, the need for flat panel display (FPD), which has excellent characteristics such as thinness, light weight and low power consumption, has emerged. Among them, liquid crystal display (LCD) ), Which is excellent in resolution, color display, and image quality, is being actively applied to notebooks and desktop monitors.

In general, a liquid crystal display (LCD) is formed by arranging two substrates on which electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injecting a liquid crystal material between the two substrates, and then applying voltage to the two electrodes. By moving the liquid crystal molecules by the electric field is a device that represents the image by the transmittance of light that varies accordingly.

The liquid crystal display (LCD) includes a liquid crystal panel in which liquid crystal is injected between two substrates, a backlight disposed under the liquid crystal panel and used as a light source, and a driver for driving the liquid crystal panel, which is located outside the liquid crystal panel.

Here, the driving unit includes a drive integrated circuit (IC) for applying a signal to the wiring of the liquid crystal panel. The method of packaging the driving IC on the liquid crystal panel includes a chip on glass (Chip On Glass) COG), Tape Carrier Package (TCP), Chip On Film (COF), and the like.

The chip-on-glass (COG) method is a method of directly attaching a driving IC to an array substrate of an LCD to directly connect an output electrode of the driving IC to a wiring pad on the array substrate. The advantages are simple and low manufacturing costs.

In other words, the chip-on-glass technology (COG) inverts the driving circuit and directly mounts the bump pad of the driving circuit to the glass panel, which enables the mounting of the driving circuit with a much finer inter-electrode pitch than the conventional method. Owing to the minimization of the footprint, the system size can be reduced, the thickness can be reduced, the resolution can be improved, and the manufacturing cost can be reduced.

In addition, chip-on-glass (COG) technology can expect high yield due to the small number of mounting processes and the number of parts used. It is easy to inspect and repair between liquid crystal panel, driving circuit, liquid crystal panel and module, and has higher reliability. It is recognized as a technology that can implement the implementation of IC.

In the chip on glass (COG) method, a bump is formed on a bare chip, and then mounted on a panel in which an inner lead pad and an out lead pad are formed. Technology. In this case, the bump has a function of making an electrical connection between the circuit of the semiconductor chip and the printed circuit board (PCB).

On the other hand, in the case of a semiconductor chip packaged in a chip-on-glass (COG) method, there is a risk of occurrence of an electrical short phenomenon as the distance between the bump and the bump located on the metal pad is narrowed.

In addition, during the test process of checking the electrical characteristics of the semiconductor chip, the bumps of the semiconductor chip and the needle of the probe card are misaligned to increase contact resistance, or, in severe cases, to open. While being generated, it is possible to receive a defective determination despite the case of a normal semiconductor chip.

Accordingly, there is a continuing need for bumps having a high-density fine pitch that can reduce the risk of electrical short phenomenon and test misjudgment that can occur in semiconductor chips while achieving high integration of devices.

For example, in the conventional straight type bumps, bumps are arranged in a row, but as the bumps are arranged in a row, the width of the bumps is narrowed. Thus, a probe test is performed. ) And difficulty in assembly.

In order to solve this problem, the conventional staggered type bump structure is advantageous to probe test and assembly by placing the bumps in two rows, but the chip size is increased. There are disadvantages.

That is, a needle is required to perform a probe test, and a tungsten needle having a diameter of about 60 μm is used. The current bump pitch is about 25 μm, and it is difficult to test by arranging probe needles of about 60 μm in a line, so the needles are arranged in a staggered type. At this time, if the length of the bump is short, the needle may come out of the bump during the test.

In addition, when the bump shapes are arranged in two rows in a staggered type bump structure, pads occupy a wider area inside the chip than in one row, thereby increasing the chip size. There is a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to effectively reduce the size of a semiconductor chip and to refine the bump pitch, and to more accurately and easily test the probe. The present invention provides a semiconductor chip having a high density of bumps and a method of manufacturing the same, which can perform not only a test but also an assembly more easily.

In order to achieve the above object, a first aspect of the present invention is a semiconductor chip having a plurality of bumps for connecting an integrated electrical circuit and the integrated electrical circuit, wherein each bump has a different width; Comprising first and second bumps, the first and second bumps are arranged alternately in a row to face each other on the semiconductor chip so that the first and second bumps are alternately positioned on the same line, between the first bumps of each of the n-th arranged bumps It is to provide a semiconductor chip having bumps arranged at a high density, characterized in that the bumps are alternately arranged so as to be spaced apart from each other by a predetermined interval so that the second bump portions of each bump arranged n + 1th.

According to a second aspect of the present invention, there is provided a semiconductor chip including a plurality of bumps for electrically connecting an integrated electric circuit with the integrated electric circuit, wherein each bump is connected to the first and second bump parts having different widths. And arranged in two rows alternately on the semiconductor chip, wherein the second bump portions of the bumps disposed in the second row are disposed between the second bump portions of the bumps arranged in the first row. It is to provide a semiconductor chip having a bump formed.

Here, the semiconductor chip is preferably mounted in a chip 0n film (COF) or chip 0n glass (COG) method.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor chip having a plurality of bumps for electrically connecting an integrated electric circuit and the integrated electric circuit, the method comprising: (a) a front surface of a semiconductor substrate on which a metal pad is formed; Selectively forming the first passivation layer and then removing the first passivation layer to expose a portion of the metal pad through a process of exposing and developing the photoresist; (b) forming a second passivation layer on the entire surface of the first passivation layer including the exposed metal pads, and then exposing a portion of the metal pad and part of the first passivation layer through exposure and development of a photoresist layer; Selectively removing the protective film; (c) forming a base metal layer on an entire surface of the second passivation layer including the exposed first passivation layer and the metal pad, and forming a UBM layer on a portion where the bump is to be formed by exposing and developing the photoresist layer; And (d) forming bumps on the top surface of the UBM layer, the bumps having first and second bump portions having different widths in a plane such that they project upwardly to a predetermined height. It is to provide a method for manufacturing a semiconductor chip.

Here, in the step (b), the second protective film is preferably made of a coating layer of Phosphorous Silicate Glass (PSG) or Polyimide Isoindoro Quinazorindion (PIQ).

Preferably, in the step (b), the exposed metal pads are arranged in a line at the periphery of the semiconductor chip at predetermined intervals so as to correspond to the direction in which the bumps are arranged in a rectangle when the semiconductor substrate is viewed in a plane. Can be arranged linearly.

Preferably, in the step (b), the exposed metal pads may be linearly arranged in a line according to the arrangement direction of the second bump portion of each bump in the same shape as the second bump portion of the bump.

Preferably, in the step (d), the bumps are formed to be composed of first and second bump portions having different widths in a T-shape when the semiconductor substrate is viewed in a plane, and each bump is formed of the semiconductors. The bumps are alternately arranged in a line to face each other, and the bumps are spaced apart from each other such that the second bumps of the n + 1th bumps are positioned between the first bumps of the nth bumps. Alternately, they can be spaced apart.

Preferably, in the step (d), the bumps are formed to be composed of first and second bump portions having different widths in a T-shape when the semiconductor substrate is viewed in a plane, and each bump is formed of the semiconductors. The second periphery of the bumps disposed in the second row may be disposed between the second bumps of the bumps disposed in the first row, alternately arranged in two rows along the edges of the chip.

As described above, the semiconductor chip according to the embodiment of the present invention includes bumps arranged at a high density, thereby effectively reducing the size of the semiconductor chip and miniaturization of the bump pitch, and more precisely. Not only can you easily perform probe tests, but you can also perform assemblies more easily.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the following embodiments of the present invention may be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. The embodiments of the present invention are provided to enable those skilled in the art to more fully understand the present invention.

(First embodiment)

1 is a schematic plan view illustrating a semiconductor chip having bumps disposed at a high density according to a first embodiment of the present invention.

Referring to FIG. 1, a semiconductor chip 100 according to a first embodiment of the present invention may include a plurality of metal pads 110 and metal pads 110 disposed along a periphery of the semiconductor chip 100. And a plurality of bumps 120 electrically connected to and protruding upwardly.

Here, the metal pad 110 is for electrically connecting the microelectronic devices (not shown) inside the semiconductor chip 100 and an external printed circuit board (PCB) at predetermined intervals. It may be formed in a shape surrounding the edge of the semiconductor chip 100.

Although not shown in the drawings, each metal pad 110 may be formed through at least one metal line and a predetermined contact hole or via hole located in the semiconductor chip 100. Electrically connected.

In addition, a bump 120 formed to protrude upward at a predetermined height is positioned on an upper portion of the metal pad 110. The bumps 120 are formed of, for example, a first bump portion 121 and a second bump portion 122 having different widths W in a T-shape, and each bump 120 includes a semiconductor chip 100. The periphery of the () is arranged alternately in a line opposite to each other.

That is, the bumps 120 are formed to be spaced at regular intervals so that the first bumps 121 and the second bumps 122 of the bumps 120 are alternately positioned on the same line, and are alternately arranged to face each other. It is arranged. In other words, each bump (n-1 and n + 1) arranged evenly between the first bump portion 121 of each bump 120 arranged in the odd (nth and n + 2th) The bumps 120 are alternately arranged to be spaced apart from each other so that the second bumps 122 of the 120 are positioned to face each other.

Here, the first bump portion 121 and the second bump portion 122 of each bump 120 is preferably formed to have the same length (L), but is not limited thereto, and may be formed to have different lengths. have. For example, the length of the first bump part 121 may be shorter or longer than the length of the second bump part 122.

Meanwhile, the bumps 120 may be formed of various metals such as gold (Au), tin (Sn), copper (Cu), nickel (Ni) or a combination thereof, and may be formed by a plating method. It may be made of an organic or inorganic material other than metal. In addition, the bump 120 may be formed as a single layer or multiple layers of a lower layer and an upper layer. Although not shown in the drawings, in the case of bumps 120 formed in a multilayer, the lower layer may be, for example, TiW, Cr, Cu, Ti, Ni, NiV, Pd, Cr / Cu, TiW / Cu, TiW / Au or NiV / Cu and the like, and the top layer may be made of, for example, plateable Au, Ni, Cu, Pd, Ag, or an alloy thereof.

Further, the lower layer and the upper layer of the bump 120 are preferably a combination of a TiW / Au lower layer and an Au or Au alloy upper layer, for example, a lower layer of TiW 0.05 to 0.5 µm and Au 0.05 to 0.5 µm and Au 1 to 1. More preferred is a combination of top layers of 10 μm.

The semiconductor chip 100 as described above may be mounted in, for example, a chip on glass (COG) method through an anisotropic conductive film (not shown).

Here, the anisotropic conductive film usually includes a small conductive particle in the thermosetting resin film, and with the property of having conductivity by the conductive particles, the insulating property when the distance between the conductive particles is a predetermined distance or more Has the characteristics.

On the other hand, the conductive particles in the anisotropic conductive film may have a diameter in the range of about 5 to 20㎛, for example, may be a polymer or glass ball (Co) coated with Au, Ag, Ni or metal.

The semiconductor chip 100 according to the first embodiment of the present invention as described above may increase the area of the bump 120 to increase the number of contacts with the conductive particles in the anisotropic conductive film, thereby reducing the contact resistance.

In addition, holes H are disposed in the lower portions of the bumps 120 so that a part of the metal pad 110 is open to test whether the semiconductor chip 100 is defective before the bumps 120 are formed. By forming a linear arrangement in a line according to the arrangement direction of the bump 120, there is an effect that can be performed more accurately and easily a probe test (Probe Test).

Meanwhile, when the probe test is to be performed through the bumps 120, the semiconductor chip 100 according to the first embodiment of the present invention may have a first and second bumps 121 having a relatively larger area than the conventional bumps. And 122, which is a contact surface of a conventional probe needle, is used to determine whether a semiconductor chip 100 is defective due to misalignment of the probe needle and the bump 120. Can be effectively reduced.

On the other hand, the semiconductor chip 100 according to the first embodiment of the present invention is preferably, for example, an LDI (LCD Driver IC) chip for driving a panel of a liquid crystal display (LCD), but is not limited thereto. no.

In addition, in the above-described embodiment, the semiconductor chip 100 has been described using the conventional chip-on-glass (COG) method as an example. However, the semiconductor chip 100 may be applied to, for example, the chip-on-film (COF) method. Of course.

(2nd Example)

2 is a schematic plan view illustrating a semiconductor chip having bumps disposed at a high density according to a second embodiment of the present invention.

Referring to FIG. 2, the semiconductor chip 100 having the bumps disposed at a high density according to the second embodiment of the present invention has only a planar arrangement structure of the bumps 120 ′ as compared with the first embodiment described above. Since there are differences and the functions and effects of the remaining components are the same as in the above-described first embodiment, a detailed description thereof will be referred to the first embodiment of the present invention.

Hereinafter, a planar arrangement structure of the bump 120 ′, which is a main difference from the first embodiment of the present invention described above, will be described in detail.

That is, the bumps 120 'applied to the second embodiment of the present invention are, for example, a first bump portion (that is, a T-shaped head portion) 121' having a different width in a T shape and a second bump. It consists of parts (that is, T-shaped legs) 122 ', and is arranged in two rows alternately along the edge of the semiconductor chip 100 along the periphery.

That is, the second bump portion 122 ′ of the bump 120 ′ disposed in the second row B between the second bump portions 122 ′ of the bump 120 ′ disposed in the first row A. FIG. Bumps 120 'disposed in the first and second rows A and B are disposed to face each other.

Meanwhile, the width W ₁ of the first bump part 121 ′ of the bump 120 ′ applied to the second embodiment of the present invention is greater than the width W ₂ of the second bump part 122 ′. desirable.

In addition, the first bump portion 121 ′ and the second bump portion 122 ′ of each bump 120 ′ are preferably formed to have the same length L, but are not limited thereto and may have different lengths. It may be formed. For example, the length of the first bump part 121 ′ may be shorter or longer than the length of the second bump part 122 ′.

In addition, a hole (Hole) is formed in the lower portion of each bump 120 'such that a portion of the metal pad 110 is open to test whether the semiconductor chip 100 is defective before the bump 120' is formed. By forming the H) to be linearly arranged in a line according to the arrangement direction of the second bump portion 122 ′ of the bump 120 ′, the probe test can be performed more accurately and easily.

Hereinafter, a method of manufacturing a semiconductor chip having high density bumps according to the first and second embodiments of the present invention will be described in detail.

3A to 3F are schematic cross-sectional views illustrating a method of manufacturing a semiconductor chip having high density bumps according to first and second embodiments of the present invention.

3A and 3B, first, an agent for protecting a microelectronic device (not shown) inside the semiconductor chip 100 on the front surface of the semiconductor substrate 101 on which the probe pad metal pads 110 are formed. 1 After forming a passivation layer 102, a first photosensitive film (not shown) is applied to the entire surface of the first passivation layer 102, and then a part of the metal pad 110 is formed by an exposure and development process. That is, the first passivation layer 102 is selectively removed to expose the formation regions of the bumps 120 and 120 ′.

Referring to FIGS. 3C and 3D, a coating layer such as, for example, Phosphorous Silicate Glass (PSG) or Polyimide Isoindoro Quinazorindion (PIQ) may be disposed on the entire surface of the first passivation layer 102 including the exposed metal pad 110 for testing the probe. After the second protective film 103 is formed, a second photoresist film (not shown) is applied to the entire surface of the second protective film 103, and then, a part and the first portion of the metal pad 110 are formed by an exposure and development process. The second passivation layer 103 is selectively removed to expose a portion of the passivation layer 102.

Meanwhile, FIG. 4 is a plan view of the semiconductor chip, in which the planar state of FIG. 3D is enlarged by region, wherein the exposed metal pad 110 is spaced at a predetermined interval when the semiconductor substrate 101 is viewed from the plane. The semiconductor chips 100 are formed to surround the edges of the semiconductor chip 100 and linearly arranged in a line.

In particular, the planar shape of the exposed metal pad 110 is arranged in a line so as to correspond to the arrangement direction of the bump 120 in a rectangular shape, such as the longitudinal direction of the bump 120 applied to the first embodiment of the present invention described above. The semiconductor chip may be generated by misalignment of the probe needle and the metal pad 110 by using the increased surface area of the metal pad 110 as a contact surface of a conventional probe needle. It is possible to effectively reduce the misjudgment as to whether or not the defect is 100).

Further, the planar shape of the exposed metal pad 110 is the same shape as the second bump portion 122 ′ of the bump 120 ′ applied to the second embodiment of the present invention, and the adjacent second bump portion ( 122 ') is formed to be arranged in a line in the direction to form, there is an effect that can perform a probe test (Probe Test) more accurately and easily.

Referring to FIG. 3E, a base metal layer (Base) is deposited on the entire surface of the exposed second passivation layer 102 and the second passivation layer 103 including the metal pad 110 by, for example, a sputtering process. A metal layer (not shown), and then a third photosensitive film (not shown) is applied to the entire surface of the base metal layer, and then bumps 120 and 120 'are subjected to an exposure and development process in a later step. By selectively removing the base metal layer of all portions except the portion to be formed to form an under bump metallurgy (UBM) layer 104 on the portion where the bumps 120, 120 'are to be formed.

Referring to FIG. 3F, the first surface of the present invention is formed by forming the high density bumps 120 and 120 ′ on the upper surface of the UBM layer 104 by electroplating Au to protrude upward to a predetermined height. And the semiconductor chip 100 according to the second embodiment.

Meanwhile, FIG. 5 is a plan view of a semiconductor chip partially showing the planar state of FIG. 3F by region, and FIG. 6 is a plan view of bumps partially enlarged by region in the plane state of FIG. 3F, and FIG. 7 is FIG. 3F. It is an actual cross-sectional photograph of the semiconductor chip which shows the bump area enlarged in the cross-sectional state of.

1, 5 to 7, the bump 120 applied to the first embodiment of the present invention described above has a different width, for example, in a T-shape when the semiconductor substrate 101 is viewed in a plan view. The first bump part 121 and the second bump part 122 may be formed, and the bumps 120 may be alternately arranged in a line at the periphery of the semiconductor chip 100 so as to face each other. It is possible to effectively reduce the size and to refine the bump pitch.

In addition, as shown in FIG. 2, the bump 120 ′ applied to the second embodiment of the present invention described above has a width different from each other in a T-shape when the semiconductor substrate 101 is viewed in a plane. The first bump portion 121 ′ and the second bump portion 122 ′ may be formed, and the bumps 120 ′ may be alternately arranged in two rows along the edge of the semiconductor chip 100. A semiconductor chip having bumps disposed at a high density may be implemented.

Although a preferred embodiment of a semiconductor chip having a high density disposed bump and a method of manufacturing the same according to the present invention has been described above, the present invention is not limited thereto, and the claims and the detailed description of the invention and the accompanying drawings. It is possible to carry out various modifications within the scope of this also belongs to the present invention.

1 is a schematic plan view illustrating a semiconductor chip having bumps disposed at a high density according to a first embodiment of the present invention.

2 is a schematic plan view illustrating a semiconductor chip having bumps disposed at a high density according to a second embodiment of the present invention.

3A to 3F are schematic cross-sectional views illustrating a method of manufacturing a semiconductor chip having bumps disposed at high density according to the first and second embodiments of the present invention.

FIG. 5 is a plan view of the semiconductor chip in which the planar state of FIG. 3F is partially enlarged.

FIG. 6 is a plan view of bumps partially enlarged for each region in the planar state of FIG. 3F.

FIG. 7 is an actual cross-sectional photograph of a semiconductor chip in which a bump area is enlarged in a cross-sectional state of FIG. 3F.

Claims (5)

A semiconductor chip having a plurality of bumps for connecting an integrated electrical circuit and the integrated electrical circuit electrically, Each bump is composed of first and second bump portions having different widths, and the first and second bump portions are alternately arranged in a row to face each other on the semiconductor chip such that the first and second bump portions are alternately positioned on the same line. The bumps are alternately arranged so that the bumps are spaced apart from each other so as to be spaced apart from each other so that the second bumps of the n + 1th arranged bumps are positioned between the first bumps of the nth arranged bumps. A semiconductor chip having a bump. A semiconductor chip having a plurality of bumps for connecting an integrated electrical circuit and the integrated electrical circuit electrically, Each bump is composed of first and second bump portions having different widths, and are arranged in two rows alternately on the semiconductor chip. And a second bump portion of the bump disposed in the second column between the second bump portions of the bump disposed in the first row. In the manufacturing method of a semiconductor chip having a plurality of bumps for connecting the integrated electrical circuit and the integrated electrical circuit, (a) forming a first passivation layer on the entire surface of the semiconductor substrate on which the metal pad is formed, and then selectively removing the first passivation layer to expose a portion of the metal pad through an exposure and development process of the photoresist; (b) forming a second passivation layer on the entire surface of the first passivation layer including the exposed metal pads, and then exposing a portion of the metal pad and part of the first passivation layer through exposure and development of a photoresist layer; Selectively removing the protective film; (c) forming a base metal layer on an entire surface of the second passivation layer including the exposed first passivation layer and the metal pad, and forming a UBM layer on a portion where the bump is to be formed by exposing and developing the photoresist layer; And and (d) forming bumps on the top surface of the UBM layer, the bumps having first and second bump portions having different widths in planar direction so as to project upwardly to a predetermined height. Method of manufacturing a semiconductor chip. The method of claim 3, In the step (b), the exposed metal pads are linearly arranged in a line at the periphery of the semiconductor chip at predetermined intervals so as to correspond to the arrangement direction of the bumps in a rectangle when the semiconductor substrate is viewed in a plane, or A semiconductor chip manufacturing method comprising bumps arranged at high density, wherein the bumps are arranged in a line in the same shape as the second bump portions of the bumps in a line along the arrangement direction of the second bump portions of the bumps. The method of claim 3, In the step (d), the bumps are formed to be composed of first and second bump portions having different widths in a T-shape when the semiconductor substrate is viewed in a plane, and each bump is formed at a periphery of the semiconductor chip. Alternatingly arranged in a row to face each other, alternately so that each bump is spaced apart from each other so that the second bump portion of each of the n + 1st bump is located between the first bump portion of each of the nth arranged bump. Place it, The bumps are formed to be formed of first and second bump portions having different widths in a T-shape when viewed from the top of the semiconductor substrate, and each bump alternates with each other along an edge at a periphery of the semiconductor chip. A method for manufacturing a semiconductor chip having bumps arranged at high density, wherein the second bump portions of the bumps arranged in the second column are disposed between the second bump portions of the bumps arranged in the first column.

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