JPH118340A - Lead frame for semiconductor device and its manufacture - Google Patents

Lead frame for semiconductor device and its manufacture

Info

Publication number
JPH118340A
JPH118340A JP17658697A JP17658697A JPH118340A JP H118340 A JPH118340 A JP H118340A JP 17658697 A JP17658697 A JP 17658697A JP 17658697 A JP17658697 A JP 17658697A JP H118340 A JPH118340 A JP H118340A
Authority
JP
Japan
Prior art keywords
layer
lead frame
semiconductor device
alloy
copper alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP17658697A
Other languages
Japanese (ja)
Inventor
Hideo Hotta
日出男 堀田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP17658697A priority Critical patent/JPH118340A/en
Publication of JPH118340A publication Critical patent/JPH118340A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/02Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material
    • C23C28/021Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material including at least one metal alloy layer
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/02Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material
    • C23C28/023Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings only including layers of metallic material only coatings of metal elements only
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/40Coatings including alternating layers following a pattern, a periodic or defined repetition
    • C23C28/42Coatings including alternating layers following a pattern, a periodic or defined repetition characterized by the composition of the alternating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Other Surface Treatments For Metallic Materials (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a lead frame for a resin-sealed semiconductor device with a base from alloys of copper, which does not need expensive Au plating and exhibits good wettability and wire-bond ability and at the same time to provide a method for manufacturing such a lead frame. SOLUTION: A lead frame for a resin-sealed semiconductor device is made of a base 110 from alloys of copper. A layer 120 of Ni or alloys of Ni of 0.5 μm or more, a layer 130 of Ag or an alloy of Ag and Pd of 0.0500.5 μm, a layer 140 of Pd of 0.05-0.5 μm and a layer 150 of Ag or an alloy of Ag and Pd of 5-500 Å are formed on the entire or a specified part of the surface 110S of the base 110 from alloys of copper from the nearest to the surface 110S according to the measurement by X-ray photoelectron spectroscopy.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は,樹脂封止型半導体装置
用のリードフレームに関し、特に、Auめっきを必要と
せず、良好な半田濡れ性、ワイヤボンディング性を得る
ことができる樹脂封止型半導体装置用のリードフレーム
と、その製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for a resin-sealed type semiconductor device, and more particularly to a resin-sealed type which can obtain good solder wettability and wire bonding property without requiring Au plating. The present invention relates to a lead frame for a semiconductor device and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来より用いられている樹脂封止型の半
導体装置(プラスチックリードフレームパッケージ)
は、一般に図5(a)に示されるような構造であり、半
導体素子520を搭載するダイパッド部511や周囲の
回路との電気的接続を行うためのアウターリード部51
3、アウターリード部513に一体となったインナーリ
ード部512、該インナーリード部512の先端部と半
導体素子520の電極パッド(端子)521とを電気的
に接続するためのワイヤ530、半導体素子520を封
止して外界からの応力、汚染から守る樹脂540等から
なっており、半導体素子520をリードフレーム510
のダイパッド511部等に搭載した後に、樹脂540に
より封止してパッケージとしたもので、半導体素子52
0の電極パッド521に対応できる数のインナーリード
512を必要とするものである。そして、このような樹
脂封止型の半導体装置の組立部材として用いられる(単
層)リードフレーム510は、一般には図5(b)に示
すような構造のもので、半導体素子を搭載するためのダ
イパッド511と、ダイパッド511の周囲に設けられ
た半導体素子と結線するためのインナーリード512、
該インナーリード512に連続して外部回路との結線を
行うためのアウターリード513、樹脂封止する際のダ
ムとなるダムバー514、リードフレーム510全体を
支持するフレーム(枠)部515等を備えており、通
常、コバール、42合金(42%ニッケル−鉄合金)、
銅系合金のような導電性に優れた金属を用い、プレス法
もしくはエッチング法により外形加工されていた。
2. Description of the Related Art Resin-sealed semiconductor devices (plastic lead frame packages) conventionally used.
5A generally has a structure as shown in FIG. 5A, and includes an outer lead portion 51 for making electrical connection with a die pad portion 511 on which a semiconductor element 520 is mounted and surrounding circuits.
3, an inner lead portion 512 integrated with the outer lead portion 513, a wire 530 for electrically connecting a tip end of the inner lead portion 512 and an electrode pad (terminal) 521 of the semiconductor element 520, and the semiconductor element 520. The semiconductor element 520 is formed of a resin 540 or the like which protects the semiconductor element 520 from stress and contamination from the outside by sealing the semiconductor element 520.
After being mounted on the die pad 511 and the like, it is sealed with a resin 540 to form a package.
This requires the number of inner leads 512 corresponding to the number of the electrode pads 521 of zero. The (single-layer) lead frame 510 used as an assembly member of such a resin-sealed semiconductor device generally has a structure as shown in FIG. 5B, and is used for mounting a semiconductor element. A die pad 511, and inner leads 512 for connecting to a semiconductor element provided around the die pad 511;
An outer lead 513 for connecting to an external circuit continuously to the inner lead 512, a dam bar 514 serving as a dam for resin sealing, a frame (frame) portion 515 for supporting the entire lead frame 510 are provided. And usually, Kovar, 42 alloy (42% nickel-iron alloy),
The outer shape has been processed by a pressing method or an etching method using a metal having excellent conductivity such as a copper-based alloy.

【0003】そして、このリードフレームは、半導体素
子と結線するためのインナーリード512のワイヤボン
ディング領域には、AgめっきまたはAuめっき等の貴
金属めっきが必要とされ、一般には、外形加工後に、必
要部のみに貴金属めっきを部分的に施していた。また、
ペースト等を介して半導体素子をダイボンディングする
側のダイパッド511表面にも貴金属めっきを必要とし
施していた。特に、インナーリード512のワイヤボン
デイング領域やダイパッド511のダイボンディング領
域等の貴金属めっきが必要な領域のみへのめっきを、部
分めっきと言っており、一般にはマスク治具を用いて、
めっき液をノズルから噴射してめっきする方法が採られ
ている。また、リードフレームのアウターリードには、
半田濡れ性の良いものが求められる。
In this lead frame, a noble metal plating such as Ag plating or Au plating is required in a wire bonding area of an inner lead 512 for connecting to a semiconductor element. Only the noble metal plating was partially applied. Also,
Noble metal plating is also required and applied to the surface of the die pad 511 on the side where the semiconductor element is die-bonded via paste or the like. In particular, plating only on a region that requires noble metal plating, such as a wire bonding region of the inner lead 512 and a die bonding region of the die pad 511, is referred to as partial plating. Generally, using a mask jig,
A method of injecting a plating solution from a nozzle to perform plating is employed. Also, the outer leads of the lead frame
Good solder wettability is required.

【0004】このため、リードフレームの第一の形態と
して、ダイパッド(チップ搭載部)511とインナーリ
ード512のワイヤボンディング領域には、Agまたは
Auめっきを設け、且つアウターリード513部にはS
nまたはSn合金層を設けたものが知られている。この
形態のものは、AgまたはAuの部分めっき用のマスク
治具が必要で、製造工程が複雑となり、Auを用いる場
合は、特にコスト高となる。リードフレームの第二の形
態として、リードフレーム全面に、中間めっき層として
Niめっき層を設け、外層としてPdめっきを層を設け
たものが、特許第1501723号公報等により知られ
ている。しかしこのリードフレームの場合、熱処理工程
を経ると表面層のPdが酸化したり、中間層のNiめっ
きが外層のPdめっき層中に拡散し、表面にNiの酸化
物を作り、ワイヤボンディング性や半田濡れ性が劣化
し、問題となっていた。リードフレームの第三の形態と
して、特開平4−115558号公報に開示されている
ように、Pd表面上にAuめっき層を施すものもある。
しかし、このリードフレームの場合は、Auめっき層を
用いるためコストが高い。
For this reason, as a first form of the lead frame, Ag or Au plating is provided in the wire bonding region between the die pad (chip mounting portion) 511 and the inner lead 512, and the outer lead 513 is provided with S or S plating.
A device provided with an n or Sn alloy layer is known. This form requires a mask jig for partial plating of Ag or Au, and the manufacturing process is complicated. When Au is used, the cost is particularly high. As a second embodiment of the lead frame, a lead frame provided with a Ni plating layer as an intermediate plating layer and a Pd plating layer as an outer layer is known from Japanese Patent No. 1501723 and the like. However, in the case of this lead frame, the Pd of the surface layer is oxidized after the heat treatment step, or the Ni plating of the intermediate layer diffuses into the Pd plating layer of the outer layer to form an oxide of Ni on the surface, thereby improving the wire bonding property and the like. Deterioration of solder wettability has been a problem. As a third form of the lead frame, there is one in which an Au plating layer is provided on the surface of Pd as disclosed in Japanese Patent Application Laid-Open No. 4-115558.
However, in the case of this lead frame, the cost is high because an Au plating layer is used.

【0005】[0005]

【発明が解決しようとする課題】上記のように、銅合金
製のリードフレームにおいては、インナーリードのワイ
ヤボンデイング領域やダイパッドのダイボンディング領
域等への貴金属めっきが必要で、且つ、アウターリード
には、半田濡れ性の良いものが求められていたが、いず
れも、製造面、コスト面で問題があった。本発明は、こ
のような状況のもと、銅合金基材からなる樹脂封止型の
半導体装置用リードフレームで、高価なAuめっきを必
要とせず、半田濡れ性、ワイヤボンディング性に優れた
樹脂封止型半導体装置用のリードフレームを提供しよう
とするものである。同時に、そのようなリードフレーム
の製造方法を提供しようとするものである。
As described above, a lead frame made of a copper alloy requires noble metal plating on a wire bonding area of an inner lead, a die bonding area of a die pad, and the like. However, there has been a demand for one having good solder wettability, but all have problems in terms of manufacturing and cost. Under such circumstances, the present invention provides a resin-encapsulated semiconductor device lead frame made of a copper alloy base material, which does not require expensive Au plating, and has excellent solder wettability and wire bonding properties. An object of the present invention is to provide a lead frame for a sealed semiconductor device. At the same time, it is intended to provide a method for manufacturing such a lead frame.

【0006】[0006]

【課題を解決するための手段】本発明の半導体装置用リ
ードフレームは、銅合金基材からなる樹脂封止型の半導
体装置用リードフレームであって、銅合金基材表面の全
部ないし所定の部分においては、X線光電子分光による
測定で、銅合金基材表面から順に、0.5μm以上のN
i層あるいはNiの合金層、0.05〜0.5μmのA
g層あるいはAgとPdとの合金層、0.05〜0.5
μmのPd層、5〜500ÅのAg層あるいはAgとP
dとの合金層が形成されていることを特徴とするもので
ある。
A lead frame for a semiconductor device according to the present invention is a resin-encapsulated lead frame for a semiconductor device made of a copper alloy base material, wherein the lead frame is provided on the entire surface or a predetermined portion of the surface of the copper alloy base material. In the measurement by X-ray photoelectron spectroscopy, 0.5 μm or more of N
i layer or Ni alloy layer, 0.05 to 0.5 μm A
g layer or alloy layer of Ag and Pd, 0.05 to 0.5
μm Pd layer, 5-500 ° Ag layer or Ag and P
d. An alloy layer with d is formed.

【0007】本発明の半導体装置用リードフレームの製
造方法は、銅合金基材表面の全部ないし所定の部分にお
いては、X線光電子分光による測定で、銅合金基材表面
から順に、0.5μm以上のNi層あるいはNiの合金
層、0.05〜0.5μmのAg層あるいはAgとPd
との合金層、0.05〜0.5μmのPd層、5〜50
0ÅのAg層あるいはAgとPdとの合金層が形成され
ている樹脂封止型の半導体装置用リードフレームの製造
方法であって、リードフレームの封止樹脂と接する側の
銅合金基材表面の全部ないし所定の部分の銅合金基材の
表面に、順次、Ni層、Ag層、Pd層、ないしNi
層、Ag層、Pd層、Ag層を形成した後に、大気下
で、加熱処理を行って製造することを特徴とするもので
ある。そして、上記において、加熱処理前の、銅合金基
材の表面のNi層、Ag層、Pd層、ないしNi層、A
g層、Pd層、Ag層の形成を、湿式めっき法、イオン
プレーティング法、蒸着法の、いずれか1つ、または2
以上の方法の組合せにより行うことを特徴とするもので
ある。また、本発明の半導体装置用リードフレームの製
造方法は、銅合金基材表面の全部ないし所定の部分にお
いては、X線光電子分光による測定で、銅合金基材表面
から順に、0.5μm以上のNi層あるいはNiの合金
層、0.05〜0.5μmのAg層あるいはAgとPd
との合金層、0.05〜0.5μmのPd層、5〜50
0ÅのAg層あるいはAgとPdとの合金層が形成され
ている樹脂封止型の半導体装置用リードフレームの製造
方法であって、リードフレームの封止樹脂と接する側の
銅合金基材表面の全部ないし所定の部分の銅合金基材の
表面に、順次、Ni層、Ag層、Pd層、Ag層を形成
したものであることを特徴とするものである。そして、
上記における銅合金基材の表面へのNi層、Ag層、P
d層、Ag層の形成を、湿式めっき法、イオンプレーテ
ィング法、蒸着法の、いずれか1つ、または2以上の方
法の組合せにより行うことを特徴とするものである。
In the method of manufacturing a lead frame for a semiconductor device according to the present invention, the entire or predetermined portion of the surface of the copper alloy base material is measured by X-ray photoelectron spectroscopy, and is 0.5 μm or more in order from the copper alloy base material surface. Ni layer or Ni alloy layer, Ag layer of 0.05 to 0.5 μm or Ag and Pd
Alloy layer, Pd layer of 0.05 to 0.5 μm, 5 to 50
A method for manufacturing a resin-encapsulated semiconductor device lead frame in which a 0 ° Ag layer or an alloy layer of Ag and Pd is formed, the method comprising: Ni layer, Ag layer, Pd layer, Ni layer
After the formation of the layers, the Ag layer, the Pd layer, and the Ag layer, a heat treatment is performed in the air to produce the layer. Then, in the above, the Ni layer, Ag layer, Pd layer, or Ni layer, A on the surface of the copper alloy base material before the heat treatment.
The formation of the g layer, the Pd layer, and the Ag layer may be performed by any one of wet plating, ion plating, and vapor deposition, or 2
The present invention is characterized in that it is performed by a combination of the above methods. Further, the method for manufacturing a lead frame for a semiconductor device of the present invention is characterized in that the entire or predetermined portion of the surface of the copper alloy base material is measured by X-ray photoelectron spectroscopy, and the order of 0.5 μm or more from the copper alloy base material surface. Ni layer or Ni alloy layer, 0.05 to 0.5 μm Ag layer or Ag and Pd
Alloy layer, Pd layer of 0.05 to 0.5 μm, 5 to 50
A method for manufacturing a resin-encapsulated semiconductor device lead frame in which a 0 ° Ag layer or an alloy layer of Ag and Pd is formed, the method comprising: The present invention is characterized in that a Ni layer, an Ag layer, a Pd layer, and an Ag layer are sequentially formed on the surface of the copper alloy substrate in all or a predetermined portion. And
Ni layer, Ag layer, P on the surface of the copper alloy substrate
The method is characterized in that the d layer and the Ag layer are formed by any one of wet plating, ion plating, and vapor deposition, or a combination of two or more methods.

【0008】[0008]

【作用】本発明の半導体装置用リードフレームは、上記
のような構成にすることにより、銅合金基材からなる樹
脂封止型の半導体装置用リードフレームで、高価なAu
めっきを必要とせず、半田濡れ性、ワイヤボンディング
性に優れた樹脂封止型半導体装置用のリードフレームの
提供を可能としている。そして更に、曲げ加工性に良好
なリードフレームの提供を可能としている。具体的に
は、銅合金基材表面の全部ないし所定の部分に、基準板
にフッ化クロム膜を用いたX線光電子分光による測定
で、銅合金基材表面から順に、0.5μm以上Ni層あ
るいはNiの合金層、0.05〜0.5μmのAg層あ
るいはAgとPdとの合金層、0.05〜0.5μmの
Pd層、5〜500ÅのAg層あるいはAgとPdとの
合金層が形成されていることにより、これを達成してい
る。
According to the lead frame for a semiconductor device of the present invention having the above-described structure, it is a resin-sealed type lead frame for a semiconductor device made of a copper alloy base material and is expensive Au.
It is possible to provide a lead frame for a resin-encapsulated semiconductor device which does not require plating and has excellent solder wettability and wire bonding properties. Further, it is possible to provide a lead frame having good bending workability. More specifically, the entire Ni alloy layer is measured by X-ray photoelectron spectroscopy using a chromium fluoride film as a reference plate on all or a predetermined portion of the surface of the copper alloy substrate. Alternatively, an alloy layer of Ni, an Ag layer of 0.05 to 0.5 μm or an alloy layer of Ag and Pd, a Pd layer of 0.05 to 0.5 μm, an Ag layer of 5 to 500 ° or an alloy layer of Ag and Pd This is achieved by the fact that is formed.

【0009】最外表面に、5〜500ÅのAg層あるい
はAgとPdとの合金層を設けることにより、最外層と
してAu層を設けなくても、0.05〜0.5μmのP
d層の酸化を防止してワイヤボンディング性の良いもの
とでき、更に、0.05〜0.5μmのPd層と0.5
μm以上のNi層との間に0.05〜0.5μmのAg
層あるいはAgとPdとの合金層を設けていることによ
り、熱処理によるNiの0.05〜0.5μmのPd層
への拡散を抑制し、ワイヤボンディング性の劣化を防い
でいる。また、このように、銅合金基材表面から、順
に、0.5μm以上のNi層あるいはNiの合金層、
0.05〜0.5μmのAg層あるいはAgとPdとの
合金層、0.05〜0.5μmのPd層、5〜500Å
のAg層あるいはAgとPdとの合金層が形成されてい
る領域においては、有機材料を熱処理したときに生じる
有機ガスの汚染に対しても影響を受けずらく、半田濡れ
性を良好なレベルに維持できる。この理由は、最外表面
のAg層あるいはAgとPdとの合金層が、触媒作用の
あるPd層を有機ガスから保護しているためと判断され
る。更に、アウターリード部等、銅合金基材表面から、
順に、0.5μm以上のNi層あるいはNiの合金層、
0.05〜0.5μmのAg層あるいはAgとPdとの
合金層、0.05〜0.5μmのPd層、5〜500Å
のAg層あるいはAgとPdとの合金層が形成されてい
る領域においては、曲げ加工に際し、クラックを生じる
ことは無く、銅合金の表面が曲げ加工により露出しない
ようにしている。この理由は、中間に設けたAg層ある
いはAgとPdとの合金層がNi層で生じたクラックを
埋め、最外層にクラックが現れるのを防ぐためと判断さ
れる。
By providing an Ag layer of 5 to 500 ° or an alloy layer of Ag and Pd on the outermost surface, a 0.05 to 0.5 μm P layer can be formed without providing an Au layer as the outermost layer.
The d-layer can be prevented from being oxidized to provide a good wire bonding property.
Ag of 0.05-0.5 μm between Ni layer of μm or more
By providing a layer or an alloy layer of Ag and Pd, the diffusion of Ni into the Pd layer of 0.05 to 0.5 μm due to the heat treatment is suppressed, and deterioration of the wire bonding property is prevented. Further, as described above, in order from the surface of the copper alloy substrate, a Ni layer or a Ni alloy layer of 0.5 μm or more,
Ag layer of 0.05 to 0.5 μm or alloy layer of Ag and Pd, Pd layer of 0.05 to 0.5 μm, 5 to 500 °
In the region where the Ag layer or the alloy layer of Ag and Pd is formed, it is hardly affected by the contamination of the organic gas generated when the organic material is heat-treated, and the solder wettability is at a satisfactory level. Can be maintained. The reason is considered to be that the Ag layer on the outermost surface or the alloy layer of Ag and Pd protects the Pd layer having a catalytic action from the organic gas. Furthermore, from the copper alloy substrate surface such as the outer lead part,
In order, a Ni layer or a Ni alloy layer of 0.5 μm or more,
Ag layer of 0.05 to 0.5 μm or alloy layer of Ag and Pd, Pd layer of 0.05 to 0.5 μm, 5 to 500 °
In the region where the Ag layer or the alloy layer of Ag and Pd is formed, no crack occurs during bending, and the surface of the copper alloy is not exposed by the bending. The reason is considered to be that the Ag layer or the alloy layer of Ag and Pd provided in the middle fills the cracks generated in the Ni layer and prevents the cracks from appearing in the outermost layer.

【0010】本発明の半導体装置用リードフレームの製
造方法は、本発明の半導体装置用リードフレームを製造
するための方法で、特に、リードフレームの全表面領域
に対し、銅合金基材表面から、順に、0.5μm以上の
Ni層あるいはNiの合金層、0.05〜0.5μmの
Ag層あるいはAgとPdとの合金層、0.05〜0.
5μmのPd層、5〜500ÅのAg層あるいはAgと
Pdとの合金層とを形成する場合には、銅合金基材の表
面全面に、順次、Ni層、Ag層、Pd層、ないし順
次、Ni層、Ag層、Pd層、Ag層を形成し、この後
に、大気下で、加熱処理うだけで済み、マスク治具等を
必要とせず、作業を簡単なものとできる。尚、加熱処理
前の、銅合金基材の表面のNi層、Ag層、Pd層の形
成は、湿式めっき法、イオンプレーティング法、蒸着法
等を用いて行うことができる。
The method for manufacturing a lead frame for a semiconductor device according to the present invention is a method for manufacturing a lead frame for a semiconductor device according to the present invention. A Ni layer or an Ni alloy layer of 0.5 μm or more, an Ag layer of 0.05 to 0.5 μm or an alloy layer of Ag and Pd, and a 0.05 to 0.
When a 5 μm Pd layer, an Ag layer of 5 to 500 ° or an alloy layer of Ag and Pd is formed, a Ni layer, an Ag layer, a Pd layer, or A Ni layer, an Ag layer, a Pd layer, and an Ag layer are formed, and thereafter, heat treatment only is required in the air, and the operation can be simplified without requiring a mask jig or the like. The formation of the Ni layer, Ag layer, and Pd layer on the surface of the copper alloy substrate before the heat treatment can be performed by a wet plating method, an ion plating method, an evaporation method, or the like.

【0011】[0011]

【発明の実施の形態】本発明の半導体装置用リードフレ
ームを以下、図にそって説明する。図1は、本発明の半
導体装置用リードフレームの銅合金基材表面の状態を示
した断面図である。図1中、110は銅合金基材、11
0Sは銅合金基材表面、120はNi層あるいはNiの
合金層、130はAg層あるいはAgとPdとの合金
層、140はPd層、150はAg層あるいはAgとP
dとの合金層である。本発明の半導体装置用リードフレ
ームは、銅合金基材からなる樹脂封止型の半導体装置用
リードフレームであって、封止樹脂と接する側の銅合金
基材表面の全領域ないしワイヤボンディング領域やダイ
ボンディング領域を含む所定の領域において、図1に示
すように、X線光電子分光による測定で、銅合金基材表
面110Sから順に、0.5μmの以上のNi層あるい
はNiの合金層120、0.05〜0.5μmのAg層
あるいはAgとPdとの合金層130、0.05〜0.
5μmのPd層140、5〜500ÅのAg層あるいは
AgとPdとの合金層150が形成されている。ワイヤ
ボンディング領域において、リードフレームの銅合金基
材表面部が図1に示すように形成されていることによ
り、最外層としてAu層を設けなくても、Pd層140
の酸化を防止でき、熱処理による、NiのPd層140
への拡散を抑制でき、結局、ワイヤボンディング性の良
いものとできる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A lead frame for a semiconductor device according to the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing a state of a surface of a copper alloy base material of a lead frame for a semiconductor device of the present invention. In FIG. 1, 110 is a copper alloy substrate, 11
0S is a copper alloy substrate surface, 120 is a Ni layer or an Ni alloy layer, 130 is an Ag layer or an alloy layer of Ag and Pd, 140 is a Pd layer, 150 is an Ag layer or Ag and Pd.
d and an alloy layer. The lead frame for a semiconductor device of the present invention is a resin-sealed lead frame for a semiconductor device made of a copper alloy base material, and the entire region or the wire bonding region of the surface of the copper alloy base material in contact with the sealing resin. In a predetermined region including the die bonding region, as shown in FIG. 1, as measured by X-ray photoelectron spectroscopy, a 0.5 μm or more Ni layer or Ni alloy layer 120, 0 Ag layer or alloy layer 130 of Ag and Pd having a thickness of 0.05 to 0.5 μm.
A Pd layer 140 of 5 μm, an Ag layer of 5 to 500 ° or an alloy layer 150 of Ag and Pd is formed. Since the surface of the copper alloy base material of the lead frame is formed as shown in FIG. 1 in the wire bonding region, the Pd layer 140 can be formed without providing the Au layer as the outermost layer.
Of Pd layer 140 of Ni by heat treatment.
Can be suppressed, and eventually the wire bonding property can be improved.

【0012】Ag層あるいはAgとPdとの合金層15
0の厚さは、Pd層140の酸化防止の面から5Å以上
必要であるが、コスト面からは500Å以下が好まし
い。Pd層140の厚さは、ワイヤボンディング性の面
から0.05以上必要で、0.5μmより厚いとコスト
高となる。Ag層あるいはAgとPdとの合金層130
の厚さは、熱処理におけるPd層140へのNiの拡散
防止の面からは0.05以上必要で、コスト面からは
0.5μm以下が好ましい。また、Ni層あるいはNi
の合金層120は、ウターリード部の耐食性確保のた
め、0.5μmの以上の厚さが必要である。
Ag layer or alloy layer 15 of Ag and Pd
The thickness of 0 is required to be 5 ° or more from the viewpoint of preventing oxidation of the Pd layer 140, but is preferably 500 ° or less from the viewpoint of cost. The thickness of the Pd layer 140 needs to be 0.05 or more from the viewpoint of wire bonding properties, and if it is thicker than 0.5 μm, the cost increases. Ag layer or alloy layer 130 of Ag and Pd
Is required to be 0.05 or more from the viewpoint of preventing the diffusion of Ni into the Pd layer 140 during the heat treatment, and is preferably 0.5 μm or less from the viewpoint of cost. Also, a Ni layer or Ni layer
Is required to have a thickness of 0.5 μm or more in order to ensure the corrosion resistance of the water lead portion.

【0013】次に、本発明の半導体装置用リードフレー
ムの製造方法について以下、図2にそって説明する。先
ず、実施の形態の第1の例を挙げる。はじめに、図2
(a)に示すように、外形加工されたリードフレームの
銅合金基材210(図2(a)(イ))に対して、湿式
めっき等を行い、銅合金基材表面210Sから、順に、
Ni層220、Ag層230、Pd層240を設けたも
の(図2(a)(ロ))を作製する。銅合金基材の表面
へのNi層、Ag層、Pd層の形成は、湿式めっき法、
イオンプレーティング法、蒸着法の、いずれか1つ、ま
たは2以上の方法の組合せにより行う。そして、これを
大気下で、加熱処理を行い、図1に示す断面構造にし
て、使用するものである。熱処理条件としては、例え
ば、ホットプレート加熱で、170°Cならば処理時間
は300秒程度必要であるが、420°Cならば30秒
程度でも良いが、加熱温度と加熱時間を適当に組合せ
る。
Next, a method of manufacturing a lead frame for a semiconductor device according to the present invention will be described with reference to FIG. First, a first example of the embodiment will be described. First, Figure 2
As shown in (a), wet-plating or the like is performed on the copper alloy base material 210 (FIG. 2 (a) (a)) of the lead frame whose outer shape has been processed, and in order from the copper alloy base material surface 210S.
A device provided with a Ni layer 220, an Ag layer 230, and a Pd layer 240 (FIG. 2A) is manufactured. The formation of the Ni layer, Ag layer, and Pd layer on the surface of the copper alloy substrate is performed by a wet plating method,
It is performed by any one of ion plating method and vapor deposition method or a combination of two or more methods. Then, this is subjected to a heat treatment in the atmosphere to obtain a cross-sectional structure shown in FIG. 1 for use. As a heat treatment condition, for example, a hot plate heating requires a processing time of about 300 seconds at 170 ° C., or about 30 seconds at 420 ° C. However, the heating temperature and the heating time are appropriately combined. .

【0014】次いで、実施の形態の第2の例を挙げる。
図2(b)に示すように、外形加工されたリードフレー
ムの銅合金基材210(図2(b)(イ))に対して、
湿式めっき等を行い、銅合金基材表面210Sから、順
に、Ni層220A、Ag層230A、Pd層240
A、Ag層235Aを設けたもの(図2(b)(ロ))
を作製し、これを大気下で、更に、加熱処理を施し図1
に示す断面構造にして、使用するものである。銅合金基
材の表面210SへのNi層、Ag層、Pd層、Ag層
の形成を、第1の例と同様、湿式めっき法、イオンプレ
ーティング法、蒸着法の、いずれか1つ、または2以上
の方法の組合せにより行う。
Next, a second example of the embodiment will be described.
As shown in FIG. 2 (b), the copper alloy base material 210 (FIG. 2 (b) (a)) of the lead frame whose outer shape has been processed is
Wet plating or the like is performed, and the Ni layer 220A, the Ag layer 230A, and the Pd layer 240 are sequentially formed from the copper alloy substrate surface 210S.
A, provided with Ag layer 235A (FIG. 2 (b) (b))
Was prepared and subjected to a heat treatment in the atmosphere to obtain a mixture shown in FIG.
The sectional structure shown in FIG. The formation of the Ni layer, the Ag layer, the Pd layer, and the Ag layer on the surface 210S of the copper alloy base material is performed by one of wet plating, ion plating, and vapor deposition as in the first example, or It is performed by a combination of two or more methods.

【0015】次いで、実施の形態の第3の例を挙げる。
第3の例の場合は、外形加工されたリードフレームの銅
合金基材210(図2(c)(イ))に対して、湿式め
っき等を行い、銅合金基材表面210Sから、順に、N
i層220B、Ag層230B、Pd層240B、Ag
層235Bを設け(図2(c)(ロ))、直接、図1に
示す断面構造にするもので、加熱処理を施さず、直接使
用するものである。銅合金基材の表面210SへのNi
層、Ag層、Pd層、Ag層の形成は、第1の例、第2
の例と同様に、湿式めっき法、イオンプレーティング
法、蒸着法の、いずれか1つ、または2以上の方法の組
合せにより行う。
Next, a third example of the embodiment will be described.
In the case of the third example, wet-plating or the like is performed on the copper alloy substrate 210 (FIG. 2 (c) (a)) of the lead frame whose outer shape has been processed, and in order from the copper alloy substrate surface 210S. N
i layer 220B, Ag layer 230B, Pd layer 240B, Ag
A layer 235B is provided (FIGS. 2 (c) and 2 (b)) and directly has the cross-sectional structure shown in FIG. 1, and is directly used without heat treatment. Ni on surface 210S of copper alloy substrate
The layers, the Ag layer, the Pd layer, and the Ag layer are formed in the first example and the second example.
In the same manner as in the above example, the method is performed by any one of wet plating, ion plating, and vapor deposition, or a combination of two or more methods.

【0016】[0016]

【実施例】更に、実施例を挙げて、本発明を説明する。
表1に示す、実施例〜実施例のリードフレームは、
図1に示す各層が、表2に示す製造方法により作製され
たものである。表1に示す比較例は、図1に示す各層に
該当する層が、それぞれ表2に示す製造方法により作製
されたものである。尚、表1の比較例の、各層の空欄部
は、相当する層の厚さがゼロであることを意味してお
り、表2に示す各層の空欄部は、相当する層の厚さがゼ
ロであることを意味している。 比較例1a、比較例1bは、実施例1のリードフレーム
において、図1に示すAgまたはAgとPdの合金層1
30、およびAgまたはAgとPdの合金層150がな
いもので、比較例2a、比較例2bは、実施例2のリー
ドフレームにおいて、図1に示すAgまたはAgとPd
の合金層130、およびAgまたはAgとPdの合金層
150がないもので、比較例3は、実施例3のリードフ
レームにおいて、図1に示すAgまたはAgとPdの合
金層130、およびAgまたはAgとPdの合金層15
0がないものである。上記各実施例のリードフレーム、
各比較例のリードフレームの作製条件は、それぞれ、図
2に示す各層が、表2に示す厚さに湿式めっき形成され
たものを、それぞれ、表2に示す加熱処理条件にて処理
したものである。尚、加熱処理は、大気下、ホットプレ
ート加熱である。 表3は、上記各実施例のリードフレーム、各比較例のリ
ードフレームについて、半田濡れ性、ワイヤボンディン
グ性、W曲げ性を評価した結果を示したものである。 表3より、各実施例のリードフレームは、いずれも、半
田濡れ性、ワイヤボンディング性、W曲げ性の面、全て
で良好であることが分かる。これに対し、比較例のリー
ドフレームは、半田濡れ性、W曲げ性で実施例に劣るこ
とは明白で、且つ、加熱処理を施したものは、ワイヤボ
ンディング性の点でも、実施例のリードフレームに比べ
劣ることが分かる。
EXAMPLES The present invention will be further described with reference to examples.
The lead frames of Examples to Examples shown in Table 1 are:
Each layer shown in FIG. 1 is manufactured by the manufacturing method shown in Table 2. In the comparative example shown in Table 1, layers corresponding to the layers shown in FIG. 1 were produced by the manufacturing methods shown in Table 2, respectively. In the comparative example of Table 1, the blank portion of each layer means that the thickness of the corresponding layer is zero, and the blank portion of each layer shown in Table 2 indicates that the thickness of the corresponding layer is zero. It means that Comparative Example 1a and Comparative Example 1b are different from the lead frame of Example 1 in that Ag or the alloy layer 1 of Ag and Pd shown in FIG.
Comparative Example 2a and Comparative Example 2b differ from the lead frame of Example 2 in that Ag or Ag and Pd shown in FIG.
Comparative Example 3 does not include the alloy layer 130 of Ag or Ag and Ag and Pd, and the alloy layer 130 of Ag or Ag and Pd shown in FIG. Ag and Pd alloy layer 15
There is no 0. Lead frame of each of the above embodiments,
The manufacturing conditions of the lead frame of each comparative example were obtained by processing each of the layers shown in FIG. 2 which were wet-plated to the thickness shown in Table 2 under the heat treatment conditions shown in Table 2, respectively. is there. The heat treatment is hot plate heating in the atmosphere. Table 3 shows the results of evaluating the solder wettability, wire bonding property, and W-bendability of the lead frame of each of the above examples and the lead frame of each of the comparative examples. From Table 3, it can be seen that all of the lead frames of Examples were good in solder wettability, wire bonding property, and W-bendability. On the other hand, it is clear that the lead frame of the comparative example is inferior to the example in solder wettability and W bending property, and the one subjected to the heat treatment also has a wire bonding property. It turns out that it is inferior to.

【0017】実施例、実施例のリードフレームは、
いずれも、銅合金からなる外形加工されたリードフレー
ムの表面を、定法により脱脂、活性化処理を行った後、
銅合金全面に、順に、Niめっき、Agめっき、Pdめ
っきを、それぞれ、表2に示す所定厚で形成したもの
を、表2に示す加熱処理を施して作製したものである。
実施例のリードフレームは、銅合金からなる外形加工
されたリードフレームの表面を、定法により脱脂、活性
化処理を行った後、銅合金全面に、順に、Niめっき、
Agめっき、Pdめっき、Agめっきを、それぞれ表2
に示す所定の厚さで形成したものを、加熱処理をせずに
作製したものである。比較例1a、比較例2aのリード
フレームは、それぞれ実施例、実施例のリードフレ
ーム作製において、Agめっきを施さず、且つ加熱処理
を施さないで作製したものである。比較例1b、比較例
2bのリードフレームは、それぞれ実施例、実施例
のリードフレーム作製において、Agめっきを施さず、
加熱処理は施して作製したものである。比較例3のリー
ドフレームは、実施例のリードフレーム作製におい
て、Agめっきを施さないで作製したものである。尚、
Agめっきは一般に市販されている。日本高純度化学株
式会社製のめっき液のテンペレジストAGRを、Pdめ
っきは同じく日本高純度化学株式会社製のパラブライト
SSTを、Niめっきは自家調合した標準的なスルファ
ミン酸浴を用いた。
The lead frame of the embodiment and the embodiment is as follows.
In any case, after performing the degreasing and activation treatment on the surface of the lead frame that has been subjected to external processing made of copper alloy by a standard method,
Ni plating, Ag plating, and Pd plating were sequentially formed on the entire surface of the copper alloy to have a predetermined thickness shown in Table 2, respectively, and were prepared by performing a heat treatment shown in Table 2.
The lead frame of the embodiment, the outer surface of the lead frame made of a copper alloy, after degreasing and activating by a conventional method, Ni plating over the entire copper alloy, in order,
Ag plating, Pd plating and Ag plating are shown in Table 2 respectively.
Are formed without heat treatment. The lead frames of Comparative Example 1a and Comparative Example 2a were produced without performing Ag plating and without performing heat treatment in the lead frame production of the example and the example, respectively. The lead frames of Comparative Example 1b and Comparative Example 2b were not subjected to Ag plating in the production of the lead frames of Examples and Examples, respectively.
The heat treatment was performed. The lead frame of Comparative Example 3 was manufactured without performing Ag plating in the manufacture of the lead frame of the example. still,
Ag plating is generally commercially available. Temper resist AGR of a plating solution manufactured by Nippon Kojundo Chemical Co., Ltd., Pb plating was also used with Parabright SST also manufactured by Nippon Kojundo Chemical Co., Ltd., and Ni plating was a standard sulfamic acid bath prepared by self-mixing.

【0018】尚、図3は、実施例を作製する際にとっ
た、図2(a)(ロ)に示す、銅合金基材表面にめっき
を施したものの、熱処理前のXPS(X線光電子分光)
による深さ方向の分析図であり、図4はこれに熱処理を
施した後のXPS(X線光電子分光)による深さ方向の
分析図である。図3、図4中、横軸は外表面からの深さ
を表し、縦軸は濃度(%)を表している。尚、図3、図
4中においては、測定に際してのノイズの影響が大き
く、ここでは、L1、L2線の下側は無視して考えてい
る。図4中、(イ)は最外表で、ここでは、Agないし
AgとPdの合金が形成されていることを示している。
(ロ)は、最外表から数千Åの深さの所で、ここではP
d層のみが存在する領域で、(ハ)はAgとPd層との
合金が存在し、(ニ)はほぼAg層のみの領域で、
(ホ)はNi層の領域である。
FIG. 3 shows an XPS (X-ray photoelectron beam) obtained by plating the surface of the copper alloy substrate shown in FIG. Spectroscopy)
FIG. 4 is an analysis diagram in the depth direction by XPS (X-ray photoelectron spectroscopy) after heat treatment is performed on the heat treatment. 3 and 4, the horizontal axis represents the depth from the outer surface, and the vertical axis represents the concentration (%). In FIGS. 3 and 4, the influence of noise at the time of measurement is large, and the lower side of the lines L1 and L2 is ignored here. In FIG. 4, (a) is the outermost table, which indicates that Ag or an alloy of Ag and Pd is formed.
(B) is a depth of several thousand square meters from the outermost table.
In the region where only the d layer exists, (c) shows an alloy of Ag and Pd layer, and (d) shows the region where only the Ag layer exists.
(E) is a region of the Ni layer.

【0019】各評価は、以下のようにして行った。半田
濡れ性は、メニスコグラフ試験装置を用い、ゼロクロス
タイムを測定し評価した。ワイヤボンディング性は、2
5μmの金線を用いて、荷重120g、温度250°
C、超音波条件30mW、15msecにて、ワイヤボ
ンディングを行い、ピールゲージで引張強度を測定し
た。また、W曲げ性は、SEMI G62−94規格に
よるW曲げ試験方法を用い、クラックの発生状況により
評価した。
Each evaluation was performed as follows. The solder wettability was evaluated by measuring a zero cross time using a meniscograph tester. The wire bonding property is 2
Using a 5 μm gold wire, load 120 g, temperature 250 °
C, wire bonding was performed under ultrasonic conditions of 30 mW and 15 msec, and tensile strength was measured with a peel gauge. The W bendability was evaluated based on the state of occurrence of cracks using a W bend test method according to SEMI G62-94 standard.

【0020】[0020]

【発明の効果】本発明は、上記のように、銅合金基材か
らなる樹脂封止型の半導体装置用リードフレームで、高
価なAuめっきを必要とせず、半田濡れ性、ワイヤボン
ディング性、更には曲げ加工性に良好なリードフレーム
の提供を可能としている。同時に、そのようなリードフ
レームを比較的簡単な方法で製造できるリードフレーム
の製造方法の提供を可能としている。
As described above, the present invention relates to a resin-sealed type lead frame for a semiconductor device made of a copper alloy base material, which does not require expensive Au plating, and has solder wettability, wire bonding property, Has made it possible to provide a lead frame excellent in bending workability. At the same time, it is possible to provide a method for manufacturing a lead frame that can manufacture such a lead frame by a relatively simple method.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置用リードフレームの表面部
の断面図
FIG. 1 is a cross-sectional view of a surface portion of a lead frame for a semiconductor device of the present invention.

【図2】銅合金基材表面への膜形成状態を説明するため
の断面図
FIG. 2 is a cross-sectional view for explaining a film formation state on a copper alloy base material surface.

【図3】加熱処理前の、XPSによる深さ方向の分析図FIG. 3 is an analysis diagram in a depth direction by XPS before a heat treatment.

【図4】加熱処理後の、XPSによる深さ方向の分析図FIG. 4 is an analysis diagram in a depth direction by XPS after a heat treatment.

【図5】従来の半導体装置とリードフレームを説明する
ための図
FIG. 5 is a diagram illustrating a conventional semiconductor device and a lead frame.

【符号の説明】[Explanation of symbols]

110 銅合金基材 110S 銅合金基材表面 120 Ni層あるいはNiの合金層 130 Ag層あるいはAgとPdとの合
金層 140 Pd層 150 Ag層あるいはAgとPdとの合
金層 210 銅合金基材 210S 銅合金基材表面 220、220A、220B Ni層 230、230A、230B Ag層 235、235A、235B Ag層 240、240A、240B Pd層 500 樹脂封止型半導体装置 510 リードフレーム 511 ダイパッド 512 インナリード 513 アウターリード 514 ダムバー 515 フレーム(枠)部 520 半導体素子 521 電極パッド(端子) 530 ワイヤ 540 樹脂
Reference Signs List 110 Copper alloy base material 110S Copper alloy base surface 120 Ni layer or Ni alloy layer 130 Ag layer or alloy layer of Ag and Pd 140 Pd layer 150 Ag layer or alloy layer of Ag and Pd 210 Copper alloy base 210S Copper alloy substrate surface 220, 220A, 220B Ni layer 230, 230A, 230B Ag layer 235, 235A, 235B Ag layer 240, 240A, 240B Pd layer 500 Resin-sealed semiconductor device 510 Lead frame 511 Die pad 512 Inner lead 513 Outer Lead 514 Dam bar 515 Frame (frame) 520 Semiconductor element 521 Electrode pad (terminal) 530 Wire 540 Resin

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 銅合金基材からなる樹脂封止型の半導体
装置用リードフレームであって、銅合金基材表面の全部
ないし所定の部分においては、X線光電子分光による測
定で、銅合金基材表面から順に、0.5μm以上のNi
層あるいはNiの合金層、0.05〜0.5μmのAg
層あるいはAgとPdとの合金層、0.05〜0.5μ
mのPd層、5〜500ÅのAg層あるいはAgとPd
との合金層が形成されていることを特徴とする半導体装
置用リードフレーム。
1. A lead frame for a resin-sealed semiconductor device comprising a copper alloy base material, wherein the entire or predetermined portion of the surface of the copper alloy base material is measured by X-ray photoelectron spectroscopy. 0.5μm or more Ni in order from the material surface
Layer or Ni alloy layer, Ag of 0.05-0.5 μm
Layer or alloy layer of Ag and Pd, 0.05-0.5μ
m Pd layer, 5-500 ° Ag layer or Ag and Pd
A lead frame for a semiconductor device, wherein an alloy layer of
【請求項2】 銅合金基材表面の全部ないし所定の部分
においては、X線光電子分光による測定で、銅合金基材
表面から順に、0.5μm以上のNi層あるいはNiの
合金層、0.05〜0.5μmのAg層あるいはAgと
Pdとの合金層、0.05〜0.5μmのPd層、5〜
500ÅのAg層あるいはAgとPdとの合金層が形成
されている樹脂封止型の半導体装置用リードフレームの
製造方法であって、リードフレームの封止樹脂と接する
側の銅合金基材表面の全部ないし所定の部分の銅合金基
材の表面に、順次、Ni層、Ag層、Pd層、ないしN
i層、Ag層、Pd層、Ag層を形成した後に、大気下
で、加熱処理を行って製造することを特徴とする半導体
装置用リードフレームの製造方法。
2. The entire or predetermined portion of the surface of the copper alloy substrate is measured by X-ray photoelectron spectroscopy, and the Ni layer or the Ni alloy layer having a thickness of 0.5 μm or more, in order from the copper alloy substrate surface. Ag layer of 0.05 to 0.5 μm or alloy layer of Ag and Pd, Pd layer of 0.05 to 0.5 μm,
A method for manufacturing a resin-encapsulated semiconductor device lead frame in which an Ag layer or an alloy layer of Ag and Pd having a thickness of 500 ° is formed, the method comprising: Ni layer, Ag layer, Pd layer, N layer
A method for manufacturing a lead frame for a semiconductor device, comprising: forming an i-layer, an Ag layer, a Pd layer, and an Ag layer, and then performing a heat treatment in the atmosphere.
【請求項3】 請求項2における加熱処理前の、銅合金
基材の表面へのNi層、Ag層、Pd層、ないしNi
層、Ag層、Pd層、Ag層の形成を、湿式めっき法、
イオンプレーティング法、蒸着法の、いずれか1つ、ま
たは2以上の方法の組合せにより行うことを特徴とする
半導体装置用リードフレームの製造方法。
3. The Ni layer, Ag layer, Pd layer, or Ni layer on the surface of the copper alloy substrate before the heat treatment according to claim 2.
Layer, Ag layer, Pd layer, and Ag layer are formed by a wet plating method,
A method for manufacturing a lead frame for a semiconductor device, wherein the method is performed by any one of ion plating method and vapor deposition method or a combination of two or more methods.
【請求項4】 銅合金基材表面の全部ないし所定の部分
においては、X線光電子分光による測定で、銅合金基材
表面から順に、0.5μm以上のNi層あるいはNiの
合金層、0.05〜0.5μmのAg層あるいはAgと
Pdとの合金層、0.05〜0.5μmのPd層、5〜
500ÅのAg層あるいはAgとPdとの合金層が形成
されている樹脂封止型の半導体装置用リードフレームの
製造方法であって、リードフレームの封止樹脂と接する
側の銅合金基材表面の全部ないし所定の部分の銅合金基
材の表面に、順次、Ni層、Ag層、Pd層、Ag層を
形成したものであることを特徴とする半導体装置用リー
ドフレームの製造方法。
4. An entire layer or a predetermined portion of the surface of the copper alloy substrate is measured by X-ray photoelectron spectroscopy. Ag layer of 0.05 to 0.5 μm or alloy layer of Ag and Pd, Pd layer of 0.05 to 0.5 μm,
A method for manufacturing a resin-encapsulated semiconductor device lead frame in which an Ag layer or an alloy layer of Ag and Pd having a thickness of 500 ° is formed, the method comprising: A method for manufacturing a lead frame for a semiconductor device, wherein a Ni layer, an Ag layer, a Pd layer, and an Ag layer are sequentially formed on the surface of the copper alloy base material in all or a predetermined portion.
【請求項5】 請求項4における銅合金基材の表面への
Ni層、Ag層、Pd層、Ag層の形成を、湿式めっき
法、イオンプレーティング法、蒸着法の、いずれか1
つ、または2以上の方法の組合せにより行うことを特徴
とする半導体装置用リードフレームの製造方法。
5. The method of claim 4, wherein the formation of the Ni layer, Ag layer, Pd layer, and Ag layer on the surface of the copper alloy substrate is performed by any one of a wet plating method, an ion plating method, and a vapor deposition method.
A method for manufacturing a lead frame for a semiconductor device, wherein the method is performed by one or a combination of two or more methods.
JP17658697A 1997-06-18 1997-06-18 Lead frame for semiconductor device and its manufacture Withdrawn JPH118340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17658697A JPH118340A (en) 1997-06-18 1997-06-18 Lead frame for semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17658697A JPH118340A (en) 1997-06-18 1997-06-18 Lead frame for semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH118340A true JPH118340A (en) 1999-01-12

Family

ID=16016161

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17658697A Withdrawn JPH118340A (en) 1997-06-18 1997-06-18 Lead frame for semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH118340A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1305132C (en) * 1999-10-01 2007-03-14 三星航空产业株式会社 Lead frame and its electroplating method
USRE45924E1 (en) * 2005-09-22 2016-03-15 Enplas Corporation Electric contact and socket for electrical part

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1305132C (en) * 1999-10-01 2007-03-14 三星航空产业株式会社 Lead frame and its electroplating method
USRE45924E1 (en) * 2005-09-22 2016-03-15 Enplas Corporation Electric contact and socket for electrical part

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