JPH1174878A - デジタルデータ伝送システム - Google Patents

デジタルデータ伝送システム

Info

Publication number
JPH1174878A
JPH1174878A JP23245997A JP23245997A JPH1174878A JP H1174878 A JPH1174878 A JP H1174878A JP 23245997 A JP23245997 A JP 23245997A JP 23245997 A JP23245997 A JP 23245997A JP H1174878 A JPH1174878 A JP H1174878A
Authority
JP
Japan
Prior art keywords
clock
signal
multiplexed
circuit
recovery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23245997A
Other languages
English (en)
Japanese (ja)
Other versions
JPH1174878A5 (enExample
Inventor
Hiromi Notani
宏美 野谷
Harufusa Kondo
晴房 近藤
Masahiko Ishiwaki
昌彦 石脇
Tsutomu Yoshimura
勉 吉村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP23245997A priority Critical patent/JPH1174878A/ja
Priority to US09/032,944 priority patent/US6396888B1/en
Publication of JPH1174878A publication Critical patent/JPH1174878A/ja
Publication of JPH1174878A5 publication Critical patent/JPH1174878A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0614—Systems characterised by the synchronising information used the synchronising signal being characterised by the amplitude, duration or polarity
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP23245997A 1997-08-28 1997-08-28 デジタルデータ伝送システム Pending JPH1174878A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP23245997A JPH1174878A (ja) 1997-08-28 1997-08-28 デジタルデータ伝送システム
US09/032,944 US6396888B1 (en) 1997-08-28 1998-03-02 Digital data transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23245997A JPH1174878A (ja) 1997-08-28 1997-08-28 デジタルデータ伝送システム

Publications (2)

Publication Number Publication Date
JPH1174878A true JPH1174878A (ja) 1999-03-16
JPH1174878A5 JPH1174878A5 (enExample) 2005-04-07

Family

ID=16939624

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23245997A Pending JPH1174878A (ja) 1997-08-28 1997-08-28 デジタルデータ伝送システム

Country Status (2)

Country Link
US (1) US6396888B1 (enExample)
JP (1) JPH1174878A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009075592A (ja) * 2007-09-20 2009-04-09 Anapass Inc データ駆動回路及び遅延固定ループ回路
JP2010130364A (ja) * 2008-11-27 2010-06-10 Sony Corp タイミング調整回路、固体撮像素子、およびカメラシステム

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6570944B2 (en) 2001-06-25 2003-05-27 Rambus Inc. Apparatus for data recovery in a synchronous chip-to-chip system
US6470060B1 (en) * 1999-03-01 2002-10-22 Micron Technology, Inc. Method and apparatus for generating a phase dependent control signal
US7015749B1 (en) * 2001-02-08 2006-03-21 National Semiconductor Corporation Frequency discriminator using replica compensated delay lines and method of operation
US20030081709A1 (en) * 2001-10-30 2003-05-01 Sun Microsystems, Inc. Single-ended IO with dynamic synchronous deskewing architecture
US20050207280A1 (en) * 2004-03-16 2005-09-22 Fowler Michael L Bit clock with embedded word clock boundary
US20050219083A1 (en) * 2004-03-16 2005-10-06 Boomer James B Architecture for bidirectional serializers and deserializer
US7064690B2 (en) * 2004-04-15 2006-06-20 Fairchild Semiconductor Corporation Sending and/or receiving serial data with bit timing and parallel data conversion
US7248122B2 (en) * 2005-09-14 2007-07-24 Fairchild Semiconductor Corporation Method and apparatus for generating a serial clock without a PLL
US7977992B2 (en) * 2006-11-14 2011-07-12 Avago Technologies Enterprise IP (Singapore) Pte. Ltd. Precision phase generator and method for phase generation
US8159887B2 (en) 2007-04-19 2012-04-17 Rambus Inc. Clock synchronization in a memory system
JP4404122B2 (ja) * 2007-09-07 2010-01-27 セイコーエプソン株式会社 高速シリアルインターフェース回路及び電子機器
US20090068314A1 (en) * 2007-09-12 2009-03-12 Robert Chatel Granulation Method And Additives With Narrow Particle Size Distribution Produced From Granulation Method
JP4927033B2 (ja) * 2008-05-30 2012-05-09 Ｎｔｔエレクトロニクス株式会社 クロック再生用信号生成方法及びクロック再生回路
US9706508B2 (en) * 2013-04-05 2017-07-11 Honeywell International Inc. Integrated avionics systems and methods
CN108023723B (zh) * 2016-11-04 2021-07-09 华为技术有限公司 频率同步的方法以及从时钟
US10284358B1 (en) * 2017-03-24 2019-05-07 Northrop Grumman Systems Corporation Clock and frame synchronization carried as a single composite signal allows the use of a single transmission line with a narrower bandwidth
US12360552B2 (en) * 2021-06-16 2025-07-15 Avago Technologies International Sales Pte. Limited Synchronization of devices with a gapped reference clock

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0309763B1 (en) * 1987-09-03 1995-03-15 Nec Corporation Multiplexer and demultiplexer apparatus adaptable for two kinds of transmission rates
JPH0683172B2 (ja) * 1988-09-27 1994-10-19 日本電気株式会社 フレームアライメント方式
US5175734A (en) * 1989-09-27 1992-12-29 Siemens Aktiengesellschaft Clock supply for multiplex systems
US4965884A (en) * 1989-11-22 1990-10-23 Northern Telecom Limited Data alignment method and apparatus
WO1991011064A1 (en) * 1990-01-08 1991-07-25 Hitachi, Ltd. Correlation code transmission system
JPH0748725B2 (ja) * 1990-07-25 1995-05-24 日本電気株式会社 フレーム同期回路
AU663590B2 (en) * 1992-05-29 1995-10-12 Nec Corporation SDH radio communication system and transmitter/receiver equipment therefor
EP0622958B1 (en) * 1993-04-28 1998-08-12 Matsushita Electric Industrial Co., Ltd. Real-time data transmitter and receiver
GB9414729D0 (en) * 1994-07-21 1994-09-07 Mitel Corp Digital phase locked loop

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009075592A (ja) * 2007-09-20 2009-04-09 Anapass Inc データ駆動回路及び遅延固定ループ回路
US8031189B2 (en) 2007-09-20 2011-10-04 Anapass Inc. Data driver circuit and delay-locked loop circuit
JP2010130364A (ja) * 2008-11-27 2010-06-10 Sony Corp タイミング調整回路、固体撮像素子、およびカメラシステム

Also Published As

Publication number Publication date
US6396888B1 (en) 2002-05-28

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