JPH1173365A - データ移動操作を最適化する方法 - Google Patents

データ移動操作を最適化する方法

Info

Publication number
JPH1173365A
JPH1173365A JP10174400A JP17440098A JPH1173365A JP H1173365 A JPH1173365 A JP H1173365A JP 10174400 A JP10174400 A JP 10174400A JP 17440098 A JP17440098 A JP 17440098A JP H1173365 A JPH1173365 A JP H1173365A
Authority
JP
Japan
Prior art keywords
message
memory
register
status
copy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10174400A
Other languages
English (en)
Japanese (ja)
Other versions
JPH1173365A5 (enExample
Inventor
M Brewer Tony
トニー・エム・ブルーアー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JPH1173365A publication Critical patent/JPH1173365A/ja
Publication of JPH1173365A5 publication Critical patent/JPH1173365A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/68—Details of translation look-aside buffer [TLB]
    • G06F2212/682—Multiprocessor TLB consistency

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP10174400A 1997-06-24 1998-06-22 データ移動操作を最適化する方法 Pending JPH1173365A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US881,346 1997-06-24
US08/881,346 US5966733A (en) 1997-06-24 1997-06-24 Optimizing data movement with hardware operations

Publications (2)

Publication Number Publication Date
JPH1173365A true JPH1173365A (ja) 1999-03-16
JPH1173365A5 JPH1173365A5 (enExample) 2005-09-22

Family

ID=25378291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10174400A Pending JPH1173365A (ja) 1997-06-24 1998-06-22 データ移動操作を最適化する方法

Country Status (2)

Country Link
US (1) US5966733A (enExample)
JP (1) JPH1173365A (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6668314B1 (en) * 1997-06-24 2003-12-23 Hewlett-Packard Development Company, L.P. Virtual memory translation control by TLB purge monitoring
US6493807B1 (en) * 1999-07-01 2002-12-10 Intel Corporation Updating flash blocks
US6263403B1 (en) * 1999-10-31 2001-07-17 Hewlett-Packard Company Method and apparatus for linking translation lookaside buffer purge operations to cache coherency transactions
JP3714184B2 (ja) * 2001-03-29 2005-11-09 富士通株式会社 記憶装置のデータ領域間複写処理方法、及び記憶システム
US6807608B2 (en) 2002-02-15 2004-10-19 International Business Machines Corporation Multiprocessor environment supporting variable-sized coherency transactions
US6704836B1 (en) * 2002-11-13 2004-03-09 Crossroads Systems, Inc. Method for dynamic control of concurrent extended copy tasks
US20050021836A1 (en) 2003-05-01 2005-01-27 Reed Carl J. System and method for message processing and routing
GB0317699D0 (en) * 2003-07-29 2003-09-03 Ibm A copy engine and a method for data movement
US7496690B2 (en) * 2003-10-09 2009-02-24 Intel Corporation Method, system, and program for managing memory for data transmission through a network
US20110296437A1 (en) * 2010-05-28 2011-12-01 Devendra Raut Method and apparatus for lockless communication between cores in a multi-core processor

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2253432A5 (enExample) * 1973-11-30 1975-06-27 Honeywell Bull Soc Ind
JPS6091462A (ja) * 1983-10-26 1985-05-22 Toshiba Corp 演算制御装置
US5276808A (en) * 1991-02-04 1994-01-04 International Business Machines Corporation Data storage buffer system and method
US5560003A (en) * 1992-12-21 1996-09-24 Iowa State University Research Foundation, Inc. System and hardware module for incremental real time garbage collection and memory management
US5502811A (en) * 1993-09-29 1996-03-26 International Business Machines Corporation System and method for striping data to magnetic tape units
JP2778913B2 (ja) * 1994-04-26 1998-07-23 株式会社東芝 マルチプロセッサシステム及びメモリアロケーション方法
US5581737A (en) * 1994-09-12 1996-12-03 International Business Machines Corporation Method and apparatus for expansion, contraction, and reapportionment of structured external storage structures

Also Published As

Publication number Publication date
US5966733A (en) 1999-10-12

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