JPH1168727A - Sampling frequency converting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely transfer data and to improve a sampling frequency converting error by mutually comparing the values of plural latched data signal and selecting one of plural data signals corresponding to the compared result. SOLUTION: A latch array circuit 70 inputs the data signal latched by a flip-flop 1 and (n) ways of data signals of respectively different phases are generated by respectively latching the inputted signal through (n) clock signals. Then, (n) latched data signals are respectively latched by an output clock signal Co, and the latched data signals are outputted from the latch array circuit 70 to a selective output circuit 40. Corresponding to the data contents of the plural inputted data signals, the selective output circuit 40 selects one of data signals with fixed values among these signals. A flip-flop circuit 2 inputs the selected signal, latches that signal through the output clock signal Co and outputs it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for performing sampling frequency conversion of a digital signal in which a plurality of data are continuous by digital signal processing, and relates to a circuit having a plurality of phases based on a clock signal synchronized with an input digital signal before conversion. A different clock signal is generated, the data signal on the input side is latched by the generated clock signal, and further, the latched digital signal is latched with a clock signal synchronized with the converted output digital signal, and then a plurality of latched digital signals are latched. By selecting the data signal of the phase in which the value of the input data is securely latched, it is possible to reliably transfer the data, and furthermore, the phase of the data can be changed within a range that does not affect the data determination. The sampling frequency conversion circuit that can improve the sampling frequency conversion error by interpolating according to Is shall.

[0002]

2. Description of the Related Art FIG. 10 shows a block diagram of a conventional sampling frequency conversion circuit. In this figure, a synchronous flip-flop 1 'that latches an input data signal Di using the timing of a rising waveform or a falling waveform of an input clock signal Ci as a latch timing.
And a synchronous flip-flop 2 'for latching the output of the synchronous flip-flop 1' using the output clock signal Co as a latch timing, and sampling the output clock signal Co from the synchronous flip-flop 2 '. By outputting the output data signal Do having the frequency, the sampling frequency of the input clock signal Ci is converted to the sampling frequency of the output clock signal Co so that the sampling frequency is converted.

In order to reliably latch a data signal with the synchronous flip-flops used for the flip-flops 1 'and 2' in the above-mentioned conventional sampling frequency conversion circuit, a clock signal for sampling must be
For example, a period during which the contents of the data signal input before and after the rising edge timing (latch timing) is stable is required. A period in which the content of this data signal is stable, that is, a setup period in which the data content before the latch timing needs to be stable, and a period in which the data content after the latch timing needs to be stable If the latched data signal changes during the two periods, the correct data is not reliably latched, and the contents of the data signal differ between the input and output of the flip-flop. It may be.

In a conventional sampling frequency conversion circuit, a sampling frequency conversion error is directly output due to skipping or overtaking of a sampling point due to a difference in frequency.

FIG. 12 is an example of a timing chart when a sampling frequency conversion is performed so that the clock ratio becomes 3: 2 in the conventional sampling frequency conversion circuit, and four data out of a plurality of data of the input data signal Di are output. D0
A conversion example is shown for a data string composed of D1, D2, and D3. Since this conversion is a conversion in which the sampling frequency is lowered, the data that has not been sampled is skipped, and in the output data signal Do, for example, the data D0 and D1 are thinned out without outputting the data D2.
-It is converted to a data string consisting of D3.

FIG. 13 is a diagram showing an example of an input / output error of the sampling frequency conversion circuit when the ratio of the frequency before and after the sampling frequency conversion is 3: 2. The vertical axis represents the value of the data, and the horizontal axis represents the position of the sampling timing. In FIG. 13A, a data string 100a indicated by a solid line is an example of a data string of the input data signal Di, and a data string 100b indicated by a dotted line is a data string 100.
5 shows an example of a data sequence when the data signal Di of a is band-limited to a required frequency band. In FIG. 13B, a data string 200a indicated by a solid line is an example of a data string of the output data signal Do, and a data string 200b indicated by a dotted line.
Represents a data sequence when the value of the output data signal Do is determined so as to reproduce the waveform of the dotted line of the data sequence 100b described above. When reproducing the data sequence 200b, an error of the actual data sequence 200a with respect to the data sequence 200b becomes a sampling frequency conversion error.

FIG. 14 shows an example of an output error when a signal in a frequency band required for signal output is frequency-converted at a ratio of 3: 2. The vertical axis represents the value of the data, and the horizontal axis represents the position of the data in FIG. 101b represents an example of the value of the input data signal Di after the band limitation. 201c is the value of the output data signal Do, and there is a sampling frequency conversion error with respect to the value of the output data signal Do which should be originally indicated by 201b.

FIG. 15 is an example of a timing chart when the sampling frequency conversion is performed so that the clock ratio becomes 3: 4 in the conventional sampling frequency conversion circuit. 4 shows an example of conversion of a data string including four data D0, D1, D2, and D3 among a plurality of data of the input data signal Di. In this conversion, some of the sampled data is repeatedly sampled for the case of a conversion in which the sampling frequency is increased, and for example, D1 is converted into a data string composed of overlapping data D0, D1, D1, D2, D3. You.

FIG. 16 shows an example of an output error when frequency conversion is performed at a ratio of 3: 4 before band limitation to a frequency band required for signal output. The vertical axis represents the value of the data, and the horizontal axis represents the position of the data in FIG. 102a is an example of the value of the input data signal Di, and 102b is a value when the input data signal Di is band-limited to a frequency band required for signal output. 202d is a value of the output data signal Do, which is the output data signal D which should be originally represented by 202b.
There is a sampling frequency conversion error for the value of o.

FIG. 17 shows an example of an output error when a signal in a frequency band required for signal output is frequency-converted at a ratio of 3: 4. The vertical axis represents the value of the data, and the horizontal axis represents the position of the data in FIG. 103b represents the value of the input data signal Di. 203e is the output data signal D
With respect to the value of o, there is a sampling frequency conversion error with respect to the value of the output data signal Do which should be represented by 203b.

[0011]

In the conventional sampling frequency conversion circuit shown in FIG. 10, since the data is transferred from the synchronous flip-flop 1 'to the synchronous flip-flop 2' having a different sampling frequency and phase, the input clock signal Ci is input. , The output side clock signal and the output side clock signal Co as shown in the timing chart of FIG.
Is that the timing T2 is the latch timing, and at this time, the data 1c is changing (transitioning), so that the data in the setup period and the hold period is not stable. For this reason, indefinite data (hereinafter, referred to as data x) is output to the output data signal Do.

In view of the above, the present invention provides a sampling frequency conversion circuit in which data of a plurality of phases are prepared on the input side, and data can be reliably transferred by discriminating safe data on the output side. .

As described above, in the conventional sampling frequency conversion circuit, a data string is generated by partially missing data or repeating the same data. However, there has been a problem that due to the lack or repetition, a sampling frequency conversion error occurs as if the data at the sampling time had a timing error of about one sampling interval from the actual value.

Accordingly, in the present invention, the value of the output data at the time of sampling frequency conversion is interpolated with a weighted average ratio corresponding to the phase within a range that does not affect data discrimination, thereby obtaining a sampling frequency conversion error. To provide a sampling frequency conversion circuit capable of improving the above.

Further, according to the present invention, for a frequency band required for an output signal, a low-pass filter for band limitation is provided before the sampling frequency conversion circuit, and a low-pass filter for improving a sampling frequency conversion error is provided at the subsequent stage, so that the accuracy can be improved. Provided is a sampling frequency conversion circuit capable of performing various conversions.

[0016]

In order to solve the above-mentioned problems, the present invention converts the sampling frequency of an input digital data signal (first data signal), and converts the converted digital data signal (first data signal). A data signal of the first data signal is switched at a timing shifted by a predetermined phase with respect to a switching timing phase of the data of the first data signal. Means for generating a plurality of data signals each having a delayed value of one data signal;
Out of the data signals of the second
Means for latching with a clock signal having a data switching timing of the data signal, and the values of the plurality of latched data signals are compared with each other, and one of the plurality of latched data signals is determined according to the comparison result. Means for outputting the selected data signal as a second data signal.

Further, the present invention converts the sampling frequency of an input digital data signal (first data signal) and outputs the converted digital data signal (second data signal). In the conversion circuit, the first data signal is switched at a timing shifted by a predetermined phase with respect to the data switching timing phase of the first data signal, and the first data signal has a value obtained by interpolating the first data signal in accordance with each of the predetermined phases. Means for generating a data signal; means for latching each of the plurality of generated data signals and the plurality of data signals of the first data signal with a clock signal having data switching timing of the second data signal; The plurality of latched data signals according to the value of the latched data signal One of the inner is selected, and has a means for outputting the selected data signal as the second data signal.

Further, in order to solve the above-mentioned problems, the present invention inputs a digital data signal, and uses a sampling frequency (second frequency) different from the sampling frequency (first frequency) at the time of input. In the sampling frequency conversion circuit that performs sampling frequency conversion by sampling the input data signal and outputs the data signal after the sampling frequency conversion, the clock signal having the data signal and the clock signal having the first frequency (A first clock signal) and the first
And a flip-flop for latching the data signal in response to the first clock signal, and a clock signal having the same frequency based on the first clock signal and having a predetermined position relative to the first clock signal. Means for generating one or more clock signals having a phase difference (phase difference clock signal); and at least one or more of the one or more phase difference clock signals and the first clock signal generated by the clock generation means. Also, a plurality of clock signals (such as a phase difference signal), an output data signal of the flip-flop, and a clock signal (a second clock signal) having the second frequency are input. Means for respectively latching the input data signals by a phase difference signal or the like, and a plurality of data signals latched with the respective different phase differences. A latch array means comprising means for latching with the second clock signal and a value comparison between a plurality of data signals latched by the second clock signal output from the latch array means, respectively. And a selection output means for selecting and outputting a data signal having predetermined data stability according to the comparison result.

Further, the present invention has interpolation calculation means for generating interpolation data from the output data signal of the flip-flop by interpolation calculation according to the predetermined phase difference, and the latch array means corresponds to the interpolation data respectively. Latched by a clock signal having a different phase difference.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 20 is a diagram illustrating an example of a block configuration of a sampling frequency conversion circuit according to the present invention. In this figure, 1 is a flip-flop, 30 is a clock signal generation circuit, 70 is a latch array circuit, 40 is a select output circuit, and 2 is a flip-flop.

To explain the operation, the data signal Di input to the flip-flop 1 is latched at the latch timing of the clock signal Ci also input. The clock signal Ci is supplied to the clock signal generation circuit 30.
And one or more clock signals having the same frequency but different phases are generated based on the clock signal Ci. The phase difference (phase interval) between signals having adjacent phases between these generated clock signals or the clock signal Ci is determined by a synchronous flip-flop used for a latch operation or the like in the latch array circuit 70. Is set to be longer than the combined period of the setup period and the hold period (hereinafter, referred to as an indefinite period). By doing so, the clock signal C is simultaneously output during the irregular period of the plurality of data signals during the latch operation by the output clock signal Co described later.
This can be done for at most one data signal without including the latch timing of o.

As a result, the clock signal generating circuit 30 outputs a plurality of clock signals Ci and the generated clock signals, or a plurality of clock signals generated only, ie, n (n is an integer). The clock signal of (positive integer) is output to the subsequent latch array circuit 70.

The latch array circuit 70 receives the data signal latched by the flip-flop 1 and latches the input data signal by the above-mentioned n clock signals. In other words, n data signals having different phases are generated. Further, the latch array circuit 70
Inputs an output clock signal Co having a frequency different from that of the input clock signal Ci. Then, the above-mentioned n latched data signals are respectively latched by the output clock signal Co, and the latched data signals Da1 to Da1 are output.
Dan is output from the latch array circuit 70 to the selection output circuit 40 at the subsequent stage.

There is a possibility that one of the n data signals Da1 to Dan latched by the output clock signal Co has an indeterminate value. That is, at most one of the data signals latched at the latch timing of the clock signal Co has an indefinite period.

For this reason, the selection output circuit 40 selects one of the data signals having an indefinite value from among the plurality of input data signals Da1 to Dan in accordance with the data contents of the plurality of data signals Da1 to Dan. Output to flip-flop 2.

The flip-flop 2 receives the selected signal, latches it with the output clock signal Co, and outputs the latched signal to the subsequent stage (not shown).

As described above, a data signal equivalent to the input data signal, excluding the data signal latched irregularly, can be converted into a sampling frequency and output.

FIG. 21 is a diagram showing a block configuration example of another embodiment of the present invention. In this figure, FIG.
The description of components denoted by the same reference numerals as those of the first embodiment is omitted. The configuration example of FIG. 21 differs greatly from that of FIG. 20 in that the data signal latched by the flip-flop 1 is input to the data signal interpolation circuit 50, and is interpolated by a predetermined interpolation process. A data signal is to be generated. As a result, the data signal interpolation circuit 5 outputs a plurality of data signals consisting of the base data signal and the generated interpolation data signal or a plurality of data signals consisting of only the generated interpolation data signal, that is, n (n is a positive number) ) Data signal is output to the subsequent latch array circuit 70.
Further, in the latch array circuit 70 ′, the data signal input from the data signal interpolating means is configured to receive a plurality of data signals from the clock signal generating means 30 according to the weighting method of the weighted average processing at the time of the interpolation processing of each interpolated data signal. Among the clock signals having the predetermined latch timing. Then, the latched data signals Db1 to Dbn are applied to the latch array circuit 7 respectively.
0 'is output to the subsequent selection output circuit 40'.

One of the data signals Db1 to Dbn may have an undefined data content. Therefore, the selection output circuit 40 ′ selects one of the data signals having an indefinite value among the plurality of input data signals Db 1 to Dbn in accordance with the contents of the input data signals Db 1 to Dbn, Output.

The flip-flop 2 receives the selected signal, latches it by the output clock signal Co, and outputs it to the subsequent stage (not shown).

As described above, a data signal equivalent to the input data signal, excluding the data signal latched at irregular intervals, can be output after being subjected to sampling frequency conversion. By latching the interpolation data corresponding to the phase for each clock signal, the sampling frequency conversion can be performed so that the waveform of the data signal after the sampling frequency conversion approximates the waveform before the conversion. A sampling frequency conversion circuit can be realized.

FIG. 1 is a diagram showing an example of a block configuration of a sampling frequency conversion circuit according to the present invention. In this sampling frequency conversion circuit, input latch means (flip-flop) 1 and output latch means (flip-flop) 2
, And synchronous flip-flops 10, 11, 12,.
23, and a latch array circuit 70 composed of synchronous flip-flops 20, 21, 22,.
It comprises a clock signal generating means 30 and an output selecting means 40.

From the preceding stage (not shown), for example, a digital video signal is input to the flip-flop 1 as an input data signal Di, and is latched by an input clock signal Ci which is a sampling frequency of the input data signal Di. Flip-flop 1 outputs data signal 1a. This data signal 1a is supplied to the flip-flop 1
Thus, a data signal having a required signal rising / falling speed such that an unstable region (undefined period) of data near the data switching change point is as short as possible than a stable region of data.

The clock signal generating means 30 generates clock signals 30a, 30b,... Having the same frequency and different phases from each other based on the input side clock signal Ci.
.. A plurality of clock signals of 30c are generated. The phase difference (phase interval) of the clock signal is set to be longer than the indefinite period, which is one of the characteristics of the synchronous flip-flop used for the latch operation and the like. FIG. 1 shows a case where the number of latch clocks having the same frequency and different phases from each other is four or more.
In addition, even when the number of clocks is two or three, a sampling frequency conversion circuit having the features of the present invention can be realized.

Synchronous flip-flops 10, 11 and 12
.. 13 are input with the data signal 1a, and are latched by clock signals Ci.30a, 30b. The clock signals Ci, 30a, 30b,... 30c have the same frequency, and the phase difference between the clock signals is set longer than the indefinite period of the synchronous flip-flop. Of the latch timings, only one of the latch timings of the clock signal is in the irregular period, or none of them is included. Therefore, at least one or more of the plurality of synchronous flip-flops can reliably latch a stable data signal. Therefore, a plurality of data signals 10a and 1a are obtained by sampling a signal to which data switching phases are respectively different and at least one of which data is reliably input.
13a are output.

A plurality of data signals 10a, 11a, 12a,... Having different phases output from the flip-flops.
13a are synchronous flip-flops 20, 21, 22... 2
3 and latched by the output clock signal Co. Data signals 10a, 11a, 12a respectively
.. Clock signal Ci having a sampling frequency of 13a
.. 30c and the output side clock signal Co are asynchronous, so that the synchronous flip-flops 20 ・ 21 ・
22 ... 23 a plurality of latched output data signals 20a
Any of 21a, 22a... 23a may have data different from the input data because the data is latched at irregular intervals as described above, but the other data is stable. The state data, that is, the same data as the input data is latched.

The selection output means 40 finds data at the data signal change point or data before and after the data signal change point from the plurality of output data signals 20a, 21a, 22a,. The data latched by the clock signal having the most preferable phase is output as the data signal 2c by selecting the data signal corresponding to the phase which changes by the clock signal, that is, the data signal corresponding to the opposite phase or the phase close to the opposite phase.

The data signal 2c is input to the synchronous flip-flop 2, and is latched by the output clock signal Co having the sampling frequency after the sampling conversion. The synchronous flip-flop 2 outputs a data signal Do having a sampling frequency of the output side clock signal Co, which is not affected by a timing delay or variation occurring during the selection processing operation by the selection output means 40.

In this way, the sampling frequency of the input data signal Di using the input clock signal Ci as the sampling clock is converted to the output data signal Do using the output clock signal Co as the sampling clock.

Hereinafter, referring to FIGS. 2 and 3, the clock signal generation means 30 and the selection output means 40 when n = 4 will be described.
An example of the internal configuration and their operations will be described.

FIG. 2 shows an example of the configuration of the clock signal generating means 30. A circuit for generating a target clock signal by inputting a clock signal 31a having an opposite phase to a double frequency synchronized with the input side clock signal Ci to the clock signal generation means of the present example, Has become. This means has a synchronous flip-flop 31 and is configured by adding signal inverting circuits 32 and 33.

The synchronous flip-flop 31 latches the input-side clock signal Ci using the clock signal 31a, so that the input-side clock signal C
The clock signal 3 having a phase delayed by a quarter phase from i.
0a is generated.

The signal inverting circuit 32 inverts the input clock signal Ci to generate a clock signal 30b having a phase delayed by a half phase from the input clock signal Ci.

In the signal inverting circuit 33, the clock signal 30
By inverting a, a clock signal 30d having a phase delayed by three quarters from the input side clock signal Ci is generated.

In this way, clock signals Ci, 30a, 30b, and 30d having the same frequency and different phases by one quarter are generated together.

FIG. 3 shows an example of the configuration of the selection output means 40. The selection output means of this example is composed of digital comparators 41, 42, 43 and selectors 44, 45, 46.

The digital comparator 41 compares the contents of the data signal 21a and the data signal 22a. The digital comparator 42 compares the contents of the data signal 22a and the data signal 23a. The digital comparator 43 outputs the data signal 23a and the data signal 20a.
Compare the contents of These comparators 41, 42, 4
3 is H if the compared contents match each other.
If it is different, a signal of Low is output.

The selector 44 is a digital comparator 4
1 is High, the data signal 22a is changed to Low.
At this time, the data signal 23a is selected and output.

The selector 45 is a digital comparator 4
2 is High, the output of the selector 44 is set to Lo.
At the time of w, the data signal 20a is selected and output.

The selector 46 is a digital comparator 4
3 is High, the output of the selector 45 is set to Lo.
In the case of w, the data signal 21a is selected and the data signal 2c is selected.
And output to the subsequent stage.

Table 1 shows the operation of the selection output means 40 shown in FIG. 3 according to the data contents when the contents of the data signals 20a, 21a, 22a and 23a change from the value "D0" to the value "D1". The relation of the signal 2c is shown. Since “x” is latched at the transition point, the input value “D0”,
This represents indefinite data that is not determined as “D1”.

[0052]

[Table 1]

FIG. 4 shows an example of the sampling frequency conversion circuit in FIG. 20 and shows a configuration example of a circuit when clock signals of three phases are used (when n = 3). In this figure, the description of the same reference numerals as those in FIGS. 1, 2 and 3 is omitted. The signal inverting circuit 34 is the same as the signal inverting circuit 33 in FIG. 2, but a signal 30e delayed by three quarters output from the signal inverting circuit 34 is input to the synchronous flip-flop 12 as a clock signal and used. Similarly to FIG. 1, the input data signal Di having the input clock signal Ci as the sampling frequency is changed to the output data signal D using the output clock signal Co as the sampling frequency.
The sampling frequency is converted to o.

FIG. 5 shows an example of a timing chart of the sampling frequency conversion circuit of FIG.

Table 2 shows that the contents of the input data signal Di are changed from "D0" to "D1" with respect to the operation of the selection output means of FIG.
A state in which the contents of the data signals 20a, 21a, and 22a on the output side can be taken according to the data contents when changing to
The relation of the data signal 2c is shown.

[0056]

[Table 2]

FIG. 6 shows an example of the sampling frequency conversion circuit shown in FIG. 21, and shows an example of a configuration in which clock signals of three phases are used and a middle point is interpolated. The components having the same reference numerals as those in FIG. In this case, the interpolation calculation means 54 uses the data signal 1a and the data signal 10 to interpolate the middle point.
An operation for calculating the average of a is performed. The interpolation data signal 54a output from the interpolation calculation means 54 is a value that is the result of the calculation for obtaining the average value,
12 is input.

FIG. 7 shows an example of a timing chart of the sampling frequency conversion circuit of FIG.

Table 3 shows the selection output circuit 4 shown in FIG.
As for the operation of the selection output means in FIG. 6 corresponding to 0 ', the output-side data signals 20a, 21a,... In response to the change of the content of the input data signal Di from the value "D0" to "D1" and further to "D2" States that the contents of 22a can be taken;
The relationship with the data signal 2c is shown. "D01" in Table 3
Is the value of the interpolated data obtained by averaging the ratio of “D0” and “D1” in a one-to-one ratio, and “D12” is the value of “D1” and “D1”.
The ratio of “2” represents the value of the interpolated data obtained by averaging 1: 1.

[0060]

[Table 3]

FIG. 8 is an example of the sampling frequency conversion circuit shown in FIG. 21 and shows an example of a configuration in which three-point interpolation is performed using clock signals of four phases. Figure 1,
Those having the same reference numerals as those in FIGS. 2, 3 and 4 have the same functions, and therefore the description thereof will be omitted.

The interpolation calculating means 51 is a calculator for obtaining an interpolation value for the phase of the clock signal 30a from the data signal 1a and the data signal 10a. Here, a case where linear interpolation is taken as an example will be described. The data signal 1a and the data signal 10a are weighted and averaged at a ratio of 1: 3 to output an interpolation data signal 51a.

The interpolation calculating means 52 is a calculator for obtaining an interpolation value for the phase of the clock signal 30b from the data signal 1a and the data signal 10a. In the case of linear interpolation, the data signal 1a and the data signal 10a are weighted and averaged at a ratio of 1: 1 to output an interpolation data signal 52a.

The interpolation calculating means 53 is a calculator for obtaining an interpolation value for the phase of the clock signal 30c from the data signal 1a and the data signal 10a. In the case of linear interpolation, the data signal 1a and the data signal 10a are weighted and averaged at a ratio of 3: 1 to output an interpolation data signal 53a.

The latch means 11 latches the interpolation data signal 51a with the clock signal 30a, the latch means 12 latches the interpolation data signal 52a with the clock signal 30b, and the latch means 14 latches the interpolation data signal 5 with the clock signal 30c.
3a, so that four latch means 10 and 11 are latched.
12 and 13 are clock signals Ci 30a 30b 3
Four data signals 1 for the four phases 0c
0a, 11a, 12a, and 13a are output.

The data signals 10a and 11 of these four phases
a, 12a, 13a are latch means 20, 21, 22, 2
3 are latched by the clock signal Co and output the data signals 20a, 21a, 22a, and 23a, respectively. Since the interpolation data signal is desirable for each phase, even if the data has stable data, the data of the adjacent phase is output. And the contents are different from each other.

Therefore, the digital comparator 41
In order to determine and select a stable output signal in steps 42 and 43, it is necessary that the content is the same as that of the data of the adjacent phase when the data has stable data. Therefore, in order to determine the output, the latch means 110, 120,.
130, latch means 210 and 22 on the output clock signal side
0.230 is added one between each phase.

The latch means 110 uses the clock signal 30a and the desired interpolation data signal 5 for the phase of the clock signal 30b.
2a is latched and a data signal 110a is output. The latch means 210 receives the data signal 110a with the clock signal Co.
And outputs a data signal 210a. The digital comparator 410 latches and outputs the data signal 22a and the data signal 2 from the interpolation data signal 52a.
The contents of 10a are compared, and if they match, the data signal 22a is determined to be safe and High is output, and if different, Low is output.

The latch means 120 outputs the desired interpolated data signal 5 to the phase of the clock signal 30c with the clock signal 30b.
Latch 3a and outputs data signal 120a. The latch means 220 outputs the data signal 120a with the clock signal Co.
And outputs a data signal 220a. The digital comparator 411 latches and outputs the data signal 23a and the data signal 2 from the interpolation data signal 53a.
The contents of 20a are compared, and if they match, the data signal 23a is determined to be safe and High is output, and if different, Low is output.

The latch means 130 latches the desired data signal 1a at the phase of the clock signal Ci with the clock signal 30c and outputs the data signal 130a. Latch means 2
Reference numeral 30 outputs a data signal 230a by latching the data signal 130a with the clock signal Co. The digital comparator 412 compares the data signal 20a latched and output from the data signal 1a with the contents of the data signal 230a. If they match, the data signal 20a is determined to be safe and High is output if different, and Low is output. .

In this way, the input data signal Di having the input clock signal Ci as the sampling frequency can be interpolated at three points while the sampling frequency is converted to the output data signal Do having the output clock signal Co as the sampling frequency. .

FIG. 9 shows an example of a timing chart of the sampling frequency conversion circuit of FIG.

Table 4 shows that the contents of the input data signal Di change from the value "D0" to "D
1 "and" D2 ", the output data signals 20a, 210a, 21a, 220a, 22a.
The relationship between the possible states of the contents 230a and 23a and the data signal 2c is shown. In Table 4, "D11" represents the value of the data signal obtained by weighted averaging with the ratio of "D0" and "D1" being 3: 1, and "D12" represents the ratio of "D0" and "D1" being 1: 1. The value of the data signal obtained by adding and averaging, "D13" is the value of the data signal obtained by weighted averaging with the ratio of "D0" and "D1" being 1: 3, and "D21" is the ratio of "D1" and "D2". The value of the data signal weighted averaged as 3 to 1 is
“D22” is the value of the data signal obtained by averaging the ratio of “D1” and “D2” as 1: 1 and “D23” is “D1”
And the value of the data signal obtained by weighting and averaging the ratio of “D2” to 1: 3.

[0074]

[Table 4]

FIG. 18 shows an example of a configuration in which a low-pass filter is added before and after the sampling frequency conversion circuit. In this case, a sampling frequency conversion circuit 60, a band-pass low-pass filter 61, and a sampling frequency conversion error improving low-pass filter 62 are provided.

The frequency characteristics obtained by synthesizing the respective frequency characteristics of the filters 61 and 62 correspond to the output 200f of all the circuits.
Is set so as to satisfy the required frequency characteristics. For example, the frequency characteristic required at an output of 200f is 1.5 MHz
Up to -3 dB and up to 3.5 MHz and up to -20 dB
B or less, the band-pass low-pass filter 61
Is 3.5 MHz at -2 dB or more up to 1.5 MHz or less.
The frequency band from z to -20 dB is set to a characteristic of -20 dB or less, and the band is sufficiently limited. The low-pass filter 62 for improving sampling frequency conversion error is a filter having a characteristic of -1 dB or more to 1.5 MHz or less. .5MH
-3 dB or more up to z and -20 at 3.5 MHz or more
When the combination of the frequency of the input clock signal Ci and the frequency of the output clock signal Co, which is the sampling frequency of the data signal, changes, the output 200
The filter coefficients of the band-limiting low-pass filter 61 and the sampling frequency conversion error improving low-pass filter 62 are changed according to the change in the combination so that the frequency characteristic required by f is obtained.

FIG. 19 shows an example of an output error when the sampling frequency conversion is performed by the sampling frequency conversion circuit having the configuration of FIG. 18 so that the clock ratio becomes 3: 4.
The vertical axis represents the value of the data, and the horizontal axis represents the relative time of the data. In the graph on the input side Di, reference numeral 104a denotes an input data signal of the entire circuit, and reference numeral 104b denotes an input data signal which is band-limited by the band-pass low-pass filter 61 in accordance with a frequency characteristic required for the output 200f. In the graph of the output side Do, 204e is an output data signal of the sampling frequency conversion circuit 60, 204f is an output data signal of the entire circuit, 20f
4b is an output data signal that should be, 204d is 104
4A shows an output data signal when the data signal of FIG. From 204d to 204e and further to 204f, the waveform becomes closer to the original output data signal of 204b.

[0078]

According to the present invention, a data signal having a phase whose data is stable at an output side is provided by using a clock signal generating means and a latching means for preparing a data signal having a plurality of phases at an input side. Because you can select and output
Stable and correct data signal transfer can be reliably performed.

Further, according to the present invention, the sampling frequency conversion error can be improved by using the interpolation operation means for interpolating the contents of the data signal in accordance with the phase within a range which does not affect the discrimination of the data signal.

Further, in the present invention, for a frequency band required for an output signal, a low-pass filter for band limitation is provided before the sampling frequency conversion circuit, and a low-pass filter for improving the sampling frequency conversion error is provided at the subsequent stage, so that more accurate measurement is possible. It is possible to perform a proper sampling frequency conversion.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a block configuration of a sampling frequency conversion circuit according to the present invention.

FIG. 2 is a diagram illustrating a configuration example of a clock signal generation unit.

FIG. 3 is a diagram showing a configuration example of a selection output unit.

FIG. 4 is a diagram showing a block configuration of an embodiment of a sampling frequency conversion circuit.

FIG. 5 is a diagram showing an example of a timing chart of the sampling frequency conversion circuit of FIG. 4;

FIG. 6 is a diagram showing a block configuration of an embodiment of a sampling frequency conversion circuit.

FIG. 7 is a diagram showing an example of a timing chart of the sampling frequency conversion circuit of FIG. 6;

FIG. 8 is a diagram showing a block configuration of an embodiment of a sampling frequency conversion circuit.

9 is a diagram showing an example of a timing chart of the sampling frequency conversion circuit of FIG. 8;

FIG. 10 is a diagram showing an example of a block configuration of a conventional sampling frequency conversion circuit.

FIG. 11 is a diagram illustrating an example of a timing chart of a conventional sampling frequency conversion circuit.

FIG. 12 is a diagram showing an example of a timing chart when a sampling frequency conversion is performed by a conventional sampling frequency conversion circuit.

FIG. 13 is a diagram illustrating an example of an output error when a sampling frequency is converted by a conventional sampling frequency conversion circuit.

FIG. 14 is a diagram illustrating an example of an output error when a sampling frequency is converted by a conventional sampling frequency conversion circuit.

FIG. 15 is a diagram showing an example of a timing chart when a sampling frequency conversion is performed by a conventional sampling frequency conversion circuit.

FIG. 16 is a diagram illustrating an example of an output error when a sampling frequency is converted by a conventional sampling frequency conversion circuit.

FIG. 17 is a diagram illustrating an example of an output error when a sampling frequency is converted by a conventional sampling frequency conversion circuit.

FIG. 18 is a diagram showing an example of a configuration in which a low-pass filter is added before and after a sampling frequency conversion circuit.

19 is a diagram illustrating an example of an output error when the sampling frequency is converted by the circuit whose configuration example is illustrated in FIG. 18;

FIG. 20 is a diagram illustrating an example of a block configuration of a sampling frequency conversion circuit according to the present invention.

FIG. 21 is a diagram illustrating an example of a block configuration of a sampling frequency conversion circuit according to the present invention.

[Explanation of symbols]

1: Synchronous flip-flop, 2: Synchronous flip-flop, 10, 11, 12,..., 13: Synchronous flip-flop, 14: Synchronous flip-flop, 20, 2
1, 22,..., 23: synchronous flip-flop, 2
4: synchronous flip-flop, 30: clock signal generation means, 31: synchronous flip-flop, 32, 33, 3
4: signal inversion circuit, 40: selection output means, 41, 42,
43: digital comparator, 44, 45, 46: selector, 50, 50 ': interpolation calculation means, 51, 52, 5
3: interpolation calculation means, 110, 120, 140, 210,
220, 230: synchronous flip-flop, 60: sampling frequency conversion circuit, 61: low-pass filter for band limitation, 62: low-pass filter for improving sampling frequency conversion error, 70, 70 ': latch array circuit

Claims (7)

[Claims] 1. A sampling frequency conversion circuit for converting a sampling frequency of an input digital data signal (first data signal) and outputting the converted digital data signal (second data signal). A plurality of data signals are switched at timings shifted by a predetermined phase with respect to the data switching timing phase of the first data signal, and the first data signal is delayed in accordance with each of the predetermined phases. Means for generating the plurality of data signals and the first
Out of the data signals of the second
Means for latching with a clock signal having a data switching timing of the data signal, and the values of the plurality of latched data signals are compared with each other, and one of the plurality of latched data signals is determined according to the comparison result. And a means for outputting the selected data signal as a second data signal. 2. A sampling frequency conversion circuit for converting a sampling frequency of an input digital data signal (first data signal) and outputting the converted digital data signal (second data signal). A plurality of data signals having a value obtained by interpolating the first data signal in accordance with each of the predetermined phases are generated while being switched at timings shifted by a predetermined phase with respect to the data switching timing phase of the first data signal. Means for generating the plurality of data signals and the first
Out of the data signals of the second
Means for latching with a clock signal having a data switching timing of the data signal, and selecting one of the plurality of latched data signals according to the value of the latched data signal, and selecting the selected data signal. The second
And a means for outputting the data signal as a data signal. 3. A digital data signal is input, and the input data signal is sampled at a sampling frequency (second frequency) that does not always match the sampling frequency (first frequency) of the input data signal. Thus, in the sampling frequency conversion circuit that performs the sampling frequency conversion of the data signal and outputs the data signal having the converted sampling frequency, the input data signal is latched by the first clock signal having the first frequency. A flip-flop and the first
Generating one or a plurality of clock signals (phase difference clock signals) having the same frequency as the first clock signal and having a predetermined phase difference with respect to the first clock signal based on the first clock signal. And a plurality of clock signals (hereinafter referred to as phase difference clock signals) of one or more phase difference clock signals and the first clock signal generated by the clock generation means, and the flip-flop. And a second clock signal having the second frequency are inputted, and the latched data signal is latched by each of the inputted phase difference clock signals. Means and the first
The plurality of data signals latched by the latch means are respectively latched by the second clock signal.
The value of a plurality of data signals latched by the second latch means is compared with the value of a plurality of data signals latched by the second latch means, and the plurality of latched signals are latched by the second latch means in accordance with the comparison result. And a selection output means for selecting and outputting a data signal having a predetermined data stability among the data signals. 4. The sampling frequency conversion circuit according to claim 3, further comprising:
The values of the data signals latched by adjacent phase difference clock signals of the plurality of data signals latched by the second latch means are compared with each other, and at least the data signals whose compared values do not match are compared. A sampling frequency conversion circuit for selecting and outputting one data signal from the data signals excluding. 5. The sampling frequency conversion circuit according to claim 3, further comprising an interpolation operation means for generating an interpolation data signal by interpolating an output data signal of said flip-flop according to said predetermined phase difference. And
A sampling frequency conversion circuit, wherein said latch array means latches said interpolation data signal by a corresponding phase difference clock signal. 6. A digital data signal is input, and the input data signal is sampled at a sampling frequency (second frequency) different from the sampling frequency (first frequency) at the time of the input. In a sampling frequency conversion circuit that performs sampling frequency conversion and outputs the data signal after the sampling frequency conversion, the data signal and the clock signal (first clock signal) having the first frequency are input to the sampling frequency conversion circuit. A flip-flop for latching the data signal in response to the first clock signal, a first clock signal input thereto, a clock signal having the same frequency based on the first clock signal, and a first clock Means for generating one or more clock signals having a predetermined phase difference with the signal (phase difference clock signal); And at least a plurality of clock signals (phase difference signals, etc.) of one or a plurality of phase difference clock signals and the first clock signal generated by the clock generation means, and an output data signal of the flip-flop. And a clock signal (second clock signal) having the second frequency, and means for respectively latching the input data signals by the input plurality of phase difference signals and the like. Means for latching a plurality of data signals latched by the phase difference with the second clock signal, respectively, and latched by the second clock signal output from the latch array means. By comparing values between a plurality of data signals, selecting a data signal having predetermined data stability according to the comparison result Sampling frequency conversion circuit characterized by having a selection output means for force. 7. The sampling frequency conversion circuit according to claim 6, further comprising interpolation calculation means for generating interpolation data from an output data signal of said flip-flop by interpolation calculation according to said predetermined phase difference. latch·
A sampling frequency conversion circuit, wherein the array means latches the interpolation data with clock signals having a corresponding phase difference.