JPH116858A - Semiconductor test circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid terminals for exclusive use of clock and suppress the increase of consumption current by inputting a system clock as a clock for scanning test according to the external control signal in testing. SOLUTION: In testing a system clock is inputted as a clock for scanning test according to the external control signal. In scanning mode a control terminal 3 is set in high level, the system clock is inputted from a terminal 4, so that a clock for scanning test is produced by a scanning clock producing circuit 15 and selected as a clock input to FF11 by a selector 14. If a terminal 2 is set in low level in normal operation, the reverse output of Q output of FF10 and 11 are selected as input data to FF10 and 11 by selectors 12 and 13. Then, by setting the terminal 3 in low level, the reverse output of the Q output of FF10 is selected as clock input to the FF11 by a selector 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan circuit for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art For example, when a scan circuit is applied to an asynchronous counter circuit in which an output of a certain flip-flop becomes a clock input of a next-stage flip-flop, a clock selection circuit and a data selection circuit are required. Some are characterized by a circuit configuration. In this case, during normal operation, a clock is input from a clock input terminal to operate the asynchronous counter, and when testing the scan circuit, a scan clock is input from the scan clock input terminal.

[0003]

However, when a scan circuit is applied to the asynchronous counter circuit,
A dedicated terminal must be provided as a clock input for the scan test.

The present invention has been made to solve the above problem. When a scan circuit is applied to the asynchronous counter circuit, a clock in a normal operation is changed by a control signal from the outside into a clock signal in a scan test. It is an object of the present invention to provide a semiconductor test circuit which enables a test of the above-mentioned asynchronous counter circuit without providing a dedicated clock terminal for a scan test by inputting a clock to a scan circuit.

Further, the present invention has been made to solve the problem that current consumption increases in a normal operation state by sharing a clock in a normal operation with a clock in a scan test. It is an object of the present invention to provide a semiconductor test circuit which does not transmit a scan test clock to the flip-flop by an external control signal, thereby suppressing an increase in current consumption.

[0006]

According to the present invention, there is provided a semiconductor test circuit comprising: a) a semiconductor integrated circuit having an asynchronous counter circuit and a combinational logic circuit using the output of the asynchronous circuit counter circuit as a data input; 2. The semiconductor integrated circuit according to claim 1, further comprising: a semiconductor test circuit having a circuit configuration capable of inputting a system clock as a scan test clock in response to a control signal from the semiconductor integrated circuit. The circuit configuration is such that a clock input to the asynchronous counter circuit is not transmitted by the control signal.

[0007]

Embodiments of the present invention will be described below.

FIG. 1 is a block diagram of a semiconductor test circuit according to the present invention. 1 is a scan input data terminal, 2 and 3 are control terminals, 4 is a system clock terminal, 5 is an output terminal of a scan circuit, 10 and 11 are flip-flops, 12, 1
Reference numerals 3 and 14 are selectors, and reference numeral 15 is a scan clock generation circuit. In this embodiment, the flip-flop 10 is a lower bit and the flip-flop 11 is an upper bit.

The test is performed in the following procedure.

In the scan mode, first, when the control terminal 2 is set to the high level, the selector 13 selects the scan input data SI as input data to the flip-flop 11, and the selector 12 selects the flip-flop 1.
The Q output output from the flip-flop 11 is selected as input data to 0. Next, the control terminal 3 is set to a high level, and a scan test clock is generated by the scan clock generating circuit 15 by inputting a system clock from the terminal 4, and the selector 14 uses the selector 14 as a clock input to the flip-flop 11 for scan test. Select a clock. In this state, the scan input data SI is serially input to the flip-flop 11 from the terminal 1 as a scan test clock generated from the scan clock generation circuit 15. Then, a clock is input from the system clock terminal 4 to operate the two flip-flops 10 and 11.

As a result, the Q output from the flip-flop 11 is latched by the flip-flop 10 via the selector 12 based on the scan input data SI input first. Finally, flip-flop 1
The Q output latched to 0 is output to the output terminal 5 of the scan circuit by the scan test clock. Even if the scan test clock signal is delayed, the scan test data is connected so as to transmit the scan test data from the most significant bit flip-flop 11 to the least significant bit flip-flop 10. The output of the bit flip-flop 10 is not transmitted as the output of the most significant bit flip-flop 11, and normal operation can be performed.

Next, during normal operation, when the control terminal 2 is first set to a low level, inverted outputs of the Q outputs of the flip-flops 10 and 11 are selected as input data to the flip-flops 10 and 11 by the selectors 12 and 13. You. Next, when the control terminal 3 is set to low level, the selector 14
Thereby, the inverted output of the Q output of the flip-flop 10 is selected as the clock input to the flip-flop 11.
In this state, the system clock is input from the terminal 4 to perform the counter operation. By setting the control terminal 3 to the low level, the scan clock is not generated by the scan clock generation circuit 15 and the scan test clock is not transmitted to the flip-flop 11, so that an increase in current consumption can be suppressed.

The embodiment of the present invention is merely an example, and is applicable not only to an asynchronous counter circuit constituted by two flip-flops but also to an asynchronous circuit constituted by a plurality of flip-flops. It is possible to apply.

[0014]

As described above, according to the present invention,
When a scan circuit is applied to the asynchronous counter circuit, a clock for normal operation is input to the scan circuit as a clock signal for the scan test by an external control signal, so that there is no dedicated clock terminal for the scan test. Then, the test of the asynchronous counter circuit can be performed. In addition, since it is not necessary to provide the dedicated terminal, the area of the semiconductor integrated circuit itself is reduced, and the cost can be reduced. Further, during normal operation, the scan test clock is not transmitted to the flip-flop by an external control signal, so that an increase in current consumption can be suppressed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor test circuit of the present invention.

[Explanation of symbols]

 Reference Signs List 1 input data terminal for scan 2 control terminal 3 control terminal 4 system clock terminal 5 output terminal of scan circuit 10 flip-flop 11 flip-flop 12 selector 13 selector 14 selector 15 selector 15 scan clock generation circuit

Claims (2)

[Claims] 1. A semiconductor integrated circuit having an asynchronous counter circuit and a combinational logic circuit having an output of the asynchronous circuit counter circuit as a data input. B) At the time of a test, a system clock is a scan test clock by an external control signal. A semiconductor test circuit having a circuit configuration capable of inputting a clock as a clock. 2. The semiconductor integrated circuit according to claim 1, wherein
A semiconductor test circuit having a circuit configuration in which a clock input to the asynchronous counter circuit is not transmitted by the external control signal during normal operation.