JP3532652B2 - Boundary scan test circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a boundary scan test circuit for an integrated circuit having a 3-state output buffer.

[0002]

2. Description of the Related Art In recent years, a boundary scan test has attracted attention as an important method for designing a testable board (printed circuit board), and the architecture of the test is defined as IEEE Standard 1149.1 (1990). Has been reached.

FIG. 8 shows the configuration of a conventional boundary scan test circuit which complies with the IEEE standard. Figure 8
The boundary scan test circuit of is an application example to an integrated circuit having a 3-state output buffer.

FIG. 8 illustrates an integrated circuit 300 having three 3-state output buffers 101, 102 and 103. 3-state output buffers 101, 102, 1
Each 3-state output of 03 is an external terminal (output pin)
It is connected to 11, 12, and 13, respectively. The output control signals 119, 121, 123 are signals to be provided as 3-state control inputs from the internal circuit (not shown) to the 3-state output buffers 101, 102, 103 during the normal operation of the integrated circuit 300. 12
Reference numerals 0, 122, and 124 denote three-state output buffers 101, 102, 1 from the internal circuit during normal operation of the integrated circuit 300.
03 are signals to be provided as data inputs, respectively. In addition, the 3-state output buffer 101 in FIG.
102 and 103 are in an output state of a logical value 0 or 1 according to a data input when the 3-state control input has a logical value of 0, and are in a high impedance state when the 3-state control input has a logical value of 1. To do.

The six boundary scan cells (BSC) 104, 105, 106, 107, 10 shown in FIG.
Reference numerals 8 and 109 form a part of the boundary scan test circuit. Each BSC has one parallel input terminal, one parallel output terminal, one serial input terminal, and one serial output terminal. The three BSCs 105, 107, 109 output the output data signals 120, 122, 1 provided to their respective parallel input terminals.
24 is supplied to each parallel output terminal as a data input of the three-state output buffers 101, 102 and 103 during the normal operation of the integrated circuit 300. In the following description, these three BSCs 105, 107, 109 are referred to as the first BSC (BSC1) or the output data BSC. The other three BSCs 104, 106, 108 have output control signals 119, applied to their respective parallel input terminals,
121 and 123 are supplied to respective parallel output terminals as 3-state control inputs of the 3-state output buffers 101, 102 and 103 during normal operation of the integrated circuit 300. In the following description, these three BSCs 104,
106 and 108 are referred to as a second BSC (BSC2) or an output control BSC.

Output control BSCs 104, 106, 108
And the output data BSCs 105, 107, 109 are
As shown in FIG. 8, each serial output terminal and each serial input terminal are connected in a daisy chain. Integrated circuit 3
During the test operation of 00, a test data string is sent from an external terminal (scan input pin) (not shown) to the serial input terminal of the BSC of the first stage in FIG. Is supplied, and the scan output signal 111 is obtained from the serial output terminal of the sixth stage BSC in FIG. 8, that is, the output data BSC 109. The scan output signal 111 is supplied to an external terminal (scan output pin) (not shown) via another BSC (not shown).

The internal configuration of one output control BSC 104 is shown in FIG. The other two output control BSCs 106, 1
08 and 3 output data BSCs 105, 107, 1
09 also has the same internal configuration as in FIG.

As shown in FIG. 9, the BSC 10 for output control is used.
4 is a parallel input terminal 51 and a parallel output terminal 52
, Serial input terminal 53, and serial output terminal 54
A first multiplexer 61, a first flip-flop 62, a second flip-flop 63, and a second
And a multiplexer 64 of.

From a test access port controller (TAP controller) (not shown) forming a part of the boundary scan test circuit, the first selection signal C1 is sent to the first multiplexer 61 by the second multiplexer 64. A second select signal C2 is provided to the first and second flip-flops 62 and 63, respectively. The first multiplexer 61 selects one of the signal supplied to the parallel input terminal 51 and the test signal supplied to the serial input terminal 53 according to the first selection signal C1, and selects the selected signal as the first signal. 1 flip-flop 62 as a data input. The output signal of the first flip-flop 62 is supplied to the serial output terminal 54 and also to the second flip-flop 63 as a data input. The second multiplexer 64 selects one of the signal supplied to the parallel input terminal 51 and the output signal of the second flip-flop 63 according to the second selection signal C2, and the selected signal is parallelized. It is supplied to the output terminal 52.

The operation of the conventional boundary scan test circuit configured as above will be described.

During normal operation of the integrated circuit 300, the output control BSCs 104, 106 and 108 and the output data BS are provided.
In all of C105, 107 and 109, the signal supplied to the parallel input terminal 51 is selected by the second multiplexer 64. As a result, the output control signals 119, 121, 123 from the internal circuit and the output data signal 1
20, 122, and 124 are 3-state output buffers 10.
As a result of being supplied to 1, 102, 103, the 3-state output buffers 101, 102, 103 are controlled by an internal circuit.

During test operation of integrated circuit 300, various test modes may be set in the TAP controller. In one of these modes, the output control BSC10
4, 106, 108 and BSC 105, 10 for output data
In all of 7, 109, the first multiplexer 6
A first selection signal C1 is provided so that 1 selects the signal provided to the serial input terminal 53. At this time, 6
First flip-flop 62 in each of the BSCs
Are connected in a daisy chain to form one scan path, and as a result, in synchronization with the clock signal supplied to the first flip-flops 62, six first flip-flops 62 are connected. The scan-in operation of the test data string is executed in 6 cycles. If the signal from the parallel input terminal 51 is held in the first flip-flop 62 in advance via the first multiplexer 61,
The scan-out operation of the internal circuit data can be achieved in parallel with the scan-in operation of the test data string.

When the clock signal is applied to the second flip-flop 63 after the scan-in operation of the test data string to the first flip-flop 62 is completed as described above, the scan-in operation is performed. The test data string is transferred to the second flip-flop 63. At this time, the second multiplexer 64 makes the second flip-flop
When the second control signal C2 is supplied to select the output signal of the flop 63, regardless of the operation of the internal circuit,
The 3-state output buffers 101, 102, 103 operate according to the scanned-in test data sequence.
In addition, the test data string is transferred to the second flip-flop 6
After the transfer to 3, the new test data string can be scanned in to the first flip-flop 62 while the test data string is held in the second flip-flop 63.

FIG. 10A shows the test data string "1,
The scan-in operation of 0,0,0,1,0 "is shown in FIG.
(B) shows the operations of the three-state output buffers 101, 102, and 103 according to the scan-in test data sequence. In this example, output control B
As a result of SC 104, 106, and 108 all outputting logical value 0 in parallel, 3-state output buffer 101,
102 and 103 are output data BSCs 105 and 10.
The output state becomes the logical value 1 or 0 according to the parallel output of 7,109. Therefore, the output pins 11, 12, 13
Therefore, regardless of the operation of the internal circuit, "1", "0",
"1" is output.

[0015]

In the conventional boundary scan test circuit described above, the output pins 11, 12,
The output logical value of 13 is set to “1”, “0” in FIG.
From “1” to “0”, as shown in FIG.
To change to "0" or "0", the test data string "0,0,0,0,0,0" is input as shown in FIG.
Scan-in must be performed. That is,
Even when only the output logical value is changed while the three-state output buffers 101, 102 and 103 are kept in the output state, the logical value 0 must be again scanned in the output control BSCs 104, 106 and 108. . This leads to an increase in test data length, an increase in test time, and a waste of test resources.

An object of the present invention is to provide a boundary scan test circuit capable of efficiently controlling a 3-state output buffer.

[0017]

In order to achieve the above-mentioned object, the invention of claim 1 is a method for scanning a test data string.
After the input, the output control BSC is separated from the scan path, and the test data already scanned in is stored / held in the output control BSC during the subsequent scan-in operation. Further, according to the invention of claim 2, when the 3-state output buffer is controlled to the high impedance state, not only the output control BSC but also the output data BSC is separated from the scan path.

Specifically, in the invention of claim 1, FIGS.
In a boundary scan test circuit for an integrated circuit having a 3-state output buffer 101, a first BSC (output data BSC) 10 shown in FIG.
5 and the second BSC (output control BSC) 104, in addition to the scan input signal 110 and the signal of the serial output terminal of the second BSC 104 during the test operation, the second BSC 104 serial First selecting means 112 for selecting to provide as a test signal to the input terminal and a second BSC if the first selecting means 112 selects the scan input signal 110 during a test operation.
The signal from the serial output terminal 104 of the first selection means 1
When 12 selects the signal of the serial output terminal of the second BSC 104, the second selection means 113 for selecting the scan input signal 110 to be provided as the test signal to the serial input terminal of the first BSC 105, respectively. The configuration with and was adopted.

Specifically, in the invention of claim 2, FIG. 4 to FIG.
As illustrated in FIG.
If the signal 2 selects the signal of the serial output terminal of the second BSC 104 and the signal of the parallel output terminal of the second BSC 104 is a signal for controlling the 3-state output buffer 101 to the high impedance state, the first BSC 10
The signal from the serial input terminal 5 is the first signal in other cases.
The configuration further including third selecting means 201, 204 for selecting the signal of the serial output terminal of the BSC 105 as the scan input signal of the next stage is adopted.

[0020]

According to the first aspect of the present invention, during the test operation, the first selecting means 112 changes the scan input signal 110 to the second input signal.
When the selection means 113 of 1 selects the signals of the serial output terminals of the second BSC 104, as shown in FIG.
A scan path 151 is constructed that passes through both the second BSC 104 and the first BSC 105. As a result, the test data string can be scanned in to both BSCs 104 and 105, and the operation of the 3-state output buffer 101 according to the test data string is achieved. Moreover, after the scan-in of the test data string, as shown in FIG.
The second selection means 113 is controlled to select the scan input signal 110 from the output signal of the serial output terminal 104. As a result, the scan path 152 that bypasses the second BSC 104 is configured, and the scan-in of new test data to only the first BSC 105 can be executed. Meanwhile, the second BSC 104
Since the signal of its own serial output terminal will be fed back to its own serial input terminal, it stores and holds the test data already scanned in.
That is, the 3-state control input of the 3-state output buffer 101 is held. Therefore, the first B
The operation of the 3-state output buffer 101 according to the test data newly scanned into the SC 105 is achieved.

According to the second aspect of the present invention, the first selection means 112 causes the scan input signal 11 during the test operation.
0, when the second selecting means 113 selects the signal of the serial output terminal of the second BSC 104, the third selecting means 201, 204 outputs the signal of the serial output terminal of the first BSC 105 to the next stage. Since it is selected as the scan input signal of the second BSC 104, as shown in FIG.
Scan path 2 through both the first and the first BSC 105
51 is configured. As a result, both BSCs 104, 10
The scan-in of the test data string to 5 can be executed, and the operation of the 3-state output buffer 101 according to the test data string is achieved. At this time, the second BSC
The signal at the parallel output terminal of the second BSC 104 becomes 3 depending on the test data scanned in to the 104.
There are cases where the state output buffer 101 is controlled to the output state (first case) and cases where the three-state output buffer 101 is controlled to the high impedance state (second case).

In the first case in which the 3-state output buffer 101 is controlled to the output state, after the scan-in of the test data string, the first selection means 112 causes the second BSC 104 to operate as shown in FIG. The second selection unit 113 outputs the output signal of the serial output terminal of the scan input signal 1
10, the third selection means 201, 204 is the first BSC
As a result of being controlled so as to select the signals of the serial output terminals of 105, the scan path 252 bypassing the second BSC 104 is configured, and as in the case of the invention of claim 1, the second BSC 104 already has the scan path 252. While storing and retaining the scanned-in test data,
Scan new test data to BSC105
Inn can be executed.

On the other hand, in the second case where the 3-state output buffer 101 is controlled to the high impedance state, after the scan-in of the test data string, as shown in FIG. Second BSC10
The output signal of the serial output terminal 4 is the second selection means 1
Reference numeral 13 designates the scan input signal 110 as the third selection means 20.
1, 204 are controlled to select the signals of the serial input terminals of the first BSC 105, respectively, and as a result, the scan path 253 that bypasses both the second BSC 104 and the first BSC 105 is configured. This is because the scan path 253 is configured so as not to pass an unnecessary BSC in consideration that the data input is ignored when the 3-state output buffer 101 is controlled to the high impedance state. is there. Moreover, even in this case, the second BSC 104 holds the test data already scanned in, and as a result, the 3-state output buffer 101 is continuously controlled to the high impedance state.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A boundary scan test circuit according to an embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows the configuration of a boundary scan test circuit according to the first embodiment of the present invention. In the integrated circuit 100 of FIG. 1, the first selector 112, 114, 116 and the second selector 11 are added to the configuration of FIG.
3,115,117 are added. Reference numeral 118 represents a mode selection signal for selection control of these six selectors 112 to 117, and the mode selection signal 118 is supplied from a TAP controller (not shown). 6 BS
The internal configuration of C104, 105, 106, 107, 108 and 109 is as shown in FIG.

The first selector 112 for the 3-state output buffer 101 is connected to another BSC (not shown) from an external terminal (scan input pin) not shown when the mode selection signal 118 has a logical value of 0. When the mode selection signal 118 has the logical value 1, the signals of the serial output terminals of the output control BSC 104 are respectively selected as the scan input signal 110 provided by the output control signal BS, and the selected signal is output to the output control BS.
It is supplied to the serial input terminal of C104. The second selector 113 outputs the signal of the serial output terminal of the output control BSC 104 when the mode selection signal 118 has a logical value of 0, and the scan input signal 110 when the mode selection signal 118 has a logical value of 1, respectively. A selected signal is supplied to the serial input terminal of the output data BSC 105.

The first selector 114 for the 3-state output buffer 102 outputs the scan input signal provided from the output data BSC 105 of the preceding stage when the mode selection signal 118 has the logical value 0, and the mode selection signal 118. In the case of the logical value 1, the signal of the serial output terminal of the output control BSC 106 is selected, and the selected signal is supplied to the serial input terminal of the output control BSC 106. The second selector 115 outputs the signal from the serial output terminal of the output control BSC 106 when the mode selection signal 118 has a logical value 0, and outputs the signal from the output data BSC 105 at the preceding stage when the mode selection signal 118 has a logical value 1. Each of the supplied scan input signals is selected, and the selected signal is supplied to the serial input terminal of the output data BSC 107.

The first selector 116 for the three-state output buffer 103 outputs the scan input signal provided from the output data BSC 107 of the preceding stage when the mode selection signal 118 has the logical value 0, and the mode selection signal 118. In the case of the logical value 1, the signal of the serial output terminal of the output control BSC 108 is selected, and the selected signal is supplied to the serial input terminal of the output control BSC 108. The second selector 117 outputs the signal of the serial output terminal of the output control BSC 108 when the mode selection signal 118 has the logical value 0, and from the output data BSC 107 of the previous stage when the mode selection signal 118 has the logical value 1. Each of the supplied scan input signals is selected, and the selected signal is supplied to the serial input terminal of the output data BSC 109.
The scan output signal 111 obtained from the serial output terminal of the output data BSC 109 is the other BSC (not shown).
Is supplied to an external terminal (scan output pin) not shown in the figure.

The operation of the boundary scan test circuit according to the first embodiment configured as described above will be described. The boundary of the integrated circuit 100 during normal operation
The operation of the scan / test circuit is the same as in the case of FIG.

When the mode selection signal 118 is set to the logic value 0 during the test operation of the integrated circuit 100, as shown in FIG. 2, the six BSCs 104, 105, 106, 107,
A scan path 151 passing through all 108 and 109 is configured. As a result, the scan-in of the test data string to all the BSCs is executed in 6 cycles, and the 3-state output buffers 101 and 102 corresponding to the scan-in test data string are executed as in the case of FIG. , 10
3 operations can be achieved.

After scanning in the test data string, the mode select signal 118 is switched to a logic one. As a result, as shown in FIG. 3, the output control BSC
A scan path 152 that bypasses 104, 106, and 108 is configured, and the output data BSCs 105 and 10 are provided.
Scan-in of a new test data string to only 7,109 can be executed in three cycles. On the other hand, in the output control BSCs 104, 106, and 108, since the signals of the respective serial output terminals are fed back to the respective serial input terminals, the output data BSC 105,
Even if the scan-in operation to 107 and 109 is executed,
The test data that has already been scanned in is stored and retained, respectively. That is, the 3-state output buffer 10
All of the three-state control inputs 1, 102, 103 are held. Therefore, BSC for output data
3-state output buffer 10 according to the test data sequence newly scanned in 105, 107, 109
The operations 1, 102, 103 are achieved.

As described above, according to the first embodiment, the output control BS is used after the scan-in of the test data string.
The CSCs 104, 106 and 108 are separated from the scan path, and the test data already scanned in is output from the BSC 10 for output control during the subsequent scan in operation.
Since the configuration for storing / holding in each of 4, 106 and 108 is adopted, the 3-state output buffers 101 and 10
It is possible to reduce the test data length and the required number of cycles required for the operation control of Nos. 2 and 103 to half as compared with the case of FIG. Therefore, it is possible to reduce the number of test data string generation steps and the test time.

(Embodiment 2) FIG. 4 shows the configuration of a boundary scan test circuit according to the second embodiment of the present invention. In the integrated circuit 200 of FIG. 4, AND circuits 201, 202 and 203, a third selector 204, and
205 and 206 are added. First selector 1
12, 114, 116 and second selectors 113, 11
The functions of 5, 117 are the same as in the case of FIG.
SC104, 105, 106, 107, 108, 109
The internal configuration of is as shown in FIG.

A for the 3-state output buffer 101
If the mode selection signal 118 has a logical value of 1 and the signal at the parallel output terminal of the output control BSC 104 is a signal having a logical value of 1 that controls the 3-state output buffer 101 to a high impedance state, the ND circuit 201 outputs the signal. A selection signal of logical value 1 and a selection signal of logical value 0 in other cases are supplied to the third selector 204, respectively. Third
When the selection signal from the AND circuit 201 has a logical value of 0, the selector 204 outputs the signal of the serial output terminal of the BSC 105 for output data, and when the selection signal from the AND circuit 201 has a logical value of 1, it outputs the signal for output data. Each signal of the serial input terminals of the BSC 105 is selected, and the selected signal is supplied as the scan input signal of the next stage. AND circuit 202 and third selector 205 for 3-state output buffer 102, AND circuit 203 and third selector 2 for 3-state output buffer 103
The function of 06 is the same as that of the AND circuit 201 and the third selector 204 for the 3-state output buffer 101.

The operation of the boundary scan test circuit according to the second embodiment having the above configuration will be described. The boundary of the integrated circuit 200 during normal operation
The operation of the scan / test circuit is the same as in the case of FIG.

When the mode selection signal 118 is set to the logical value 0 during the test operation of the integrated circuit 200, as shown in FIG. 5, the six BSCs 104, 105, 106, 107,
A scan path 251 passing through all 108 and 109 is formed. As a result, the scan-in of the test data string to all the BSCs is executed in 6 cycles, and the 3-state output buffers 101 and 102 corresponding to the scan-in test data string are executed as in the case of FIG. , 10
3 operations can be achieved. At this time, the output control BSCs 104, 106, and 108 are scanned in according to the test data strings, and the output control BSCs 104,
When the signals at the parallel output terminals of 106 and 108 are signals of logical value 0 for controlling the 3-state output buffers 101, 102 and 103 to the output state, and when the 3-state output buffers 101, 102 and 103 are set to the high impedance state. In some cases, it is a signal having a logical value 1 to be controlled.

Output control BSCs 104, 106, 108
When the signal at the parallel output terminal of is a logical value 0,
When the mode selection signal 118 is switched to the logical value 1,
As shown in FIG. 6, output control BSCs 104, 106,
A scan path 252 that bypasses 108 is configured. Therefore, as in the case of FIG.
BS for controlling output of test data with logical value 0
Scanning in of a new test data string to the output data BSC 105, 107, 109 can be executed in three cycles while being stored and held in the Cs 104, 106, 108, respectively.

On the other hand, the output control BSCs 104, 106,
When the signal at the parallel output terminal of 108 has a logical value of 1, when the mode selection signal 118 is switched to a logical value of 1, as shown in FIG.
A scan path 253 that bypasses all of 5, 106, 107, 108, and 109 is configured. Even in this case, the output control BSCs 104, 106 and 108 respectively store and hold the test data of the logical value 1 that has already been scanned in, and as a result, the 3-state output buffer 10
1, 102 and 103 are continuously controlled to the high impedance state.

As described above, according to the second embodiment, 3
The state output buffers 101, 102, 103 are set to high level.
When controlling to the impedance state, the output control BS
BS for output data as well as C104, 106, 108
Since C105, 107 and 109 are also separated from the scan path, the test data length and the required number of cycles of the integrated circuit can be further reduced as compared with the first embodiment. Therefore, it is possible to further reduce the number of test data string generation steps and the test time.

[0040]

As described above, according to the invention of claim 1, in the boundary scan test circuit for the integrated circuit having the 3-state output buffer,
B for output control after scan-in of test data string
Separate the SC from the scan path and
Since the input test data is stored / held in the output control BSC during the subsequent scan-in operation, the scan path length, test data length and test time can be shortened. Therefore, the waste of test resources can be eliminated.

According to the second aspect of the present invention, when controlling the 3-state output buffer to the high impedance state, not only the output control BSC but also the output data BS are controlled.
Since C is also separated from the scan path, the scan path length, the test data length, and the test time can be further shortened.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a boundary scan test circuit according to a first embodiment of the present invention.

2 is an explanatory diagram of a first test mode of the boundary scan test circuit of FIG. 1. FIG.

3 is an explanatory diagram of a second test mode of the boundary scan test circuit of FIG.

FIG. 4 is a circuit diagram showing a configuration of a boundary scan test circuit according to a second embodiment of the present invention.

5 is an explanatory diagram of a first test mode of the boundary scan test circuit of FIG.

6 is an explanatory diagram of a first mode of a second test mode of the boundary scan test circuit of FIG.

7 is an explanatory diagram of a second aspect of the second test mode of the boundary scan test circuit of FIG. 4. FIG.

FIG. 8 is a circuit diagram showing a configuration of a conventional boundary scan test circuit.

9 is a circuit diagram showing the internal configuration of one boundary scan cell in the boundary scan test circuit of FIG. 8. FIG.

10A is an explanatory diagram showing a scan-in operation of a certain test data string to the boundary scan test circuit of FIG. 8, and FIG. 10B is a diagram showing the scan-in test data string according to the scan-in test data string. It is explanatory drawing which shows the operation | movement of the 3 state output buffer which carried out.

11A is an explanatory diagram showing a scan-in operation of another test data string to the boundary scan test circuit of FIG. 8, and FIG. 11B is a diagram showing the scan-in test data string. It is explanatory drawing which shows operation | movement of the corresponding 3-state output buffer.

[Explanation of Codes] 11, 12, 13 Output Pins (External Terminals) 51 Parallel Input Terminals (First Terminals) 52 Parallel Output Terminals (Second Terminals) 53 Serial Input Terminals (Third Terminals) 54 Serial Output Terminals (Fourth terminal) 61, 64 Multiplexer 62, 63 Flip-flop 100, 200, 300 Integrated circuit 101, 102, 103 Three-state output buffer 104, 106, 108 Second boundary scan cell (BSC2: Output control) BSC) 105, 107, 109 first boundary scan cell (BSC1: BSC for output data) 110 scan input signal 111 scan output signal 112, 114, 116 first selector (first selection means) 113, 115, 117 second selector (second selection means) 118 mode selection Signals 119, 121, 123 Output control signals 120, 122, 124 Output data signals 151, 152 Scan paths 201, 202, 203 AND circuits (third selecting means) 204, 205, 206 Third selectors (third selector) Selection means) 251, 252, 253 scan path

Claims (2)

(57) [Claims] 1. A boundary scan test circuit for an integrated circuit having a 3-state output buffer connected to an external terminal and controlled by an internal circuit, comprising: a first, a second, a third and a fourth. An output data signal provided to the first terminal from the internal circuit during normal operation of the integrated circuit, is supplied to the second terminal as a data input of the three-state output buffer, and the integrated circuit During a test operation of the circuit, the test signal supplied to the third terminal is held, the held test signal is immediately supplied to the fourth terminal, and the held test signal is supplied to the second terminal at a certain timing. A first boundary scan cell for supplying the internal circuit to the internal circuit during normal operation of the integrated circuit. Is supplied to the second terminal as a 3-state control input of the 3-state output buffer to the second terminal, and is supplied to the third terminal during a test operation of the integrated circuit. Second boundary scan cell for holding the test signal and supplying the held test signal to the fourth terminal immediately and supplying the held test signal to the second terminal at a certain timing. And, during the test operation of the integrated circuit, one of the scan input signal and the output signal of the fourth terminal of the second boundary scan cell is set to the second boundary.
First selecting means for selecting to provide as a test signal to a third terminal of the scan cell, and the first selecting means selects the scan input signal during a test operation of the integrated circuit. Is the output signal of the fourth terminal of the second boundary scan cell,
When the first selection means selects the output signal of the fourth terminal of the second boundary scan cell, the scan input signal is supplied to the third boundary of the first boundary scan cell. A boundary scan test circuit comprising: second selecting means for selecting the terminal to provide it as a test signal. 2. The boundary scan test circuit according to claim 1, wherein during the test operation of the integrated circuit, the first selecting means outputs the fourth terminal of the second boundary scan cell. The first boundary scan cell when selecting a signal and the output signal of the second terminal of the second boundary scan cell is a signal for controlling the three-state output buffer to a high impedance state. The input signal at the third terminal of the cell, otherwise the output signal at the fourth terminal of the first boundary scan cell,
The third for selecting each as the scan input signal of the next stage
Boundary characterized by further comprising selection means of
Scan test circuit.