JPH1021109A - Circuit for testing arithmetic unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a testing circuit for reducing the number of testing terminals and test time required for the test of an arithmetic unit which operates data of a memory incorporated in LSI. SOLUTION: A test clock is inputted from an external input terminal 301 and test ROM address signals 311 and 312 are generated by couters 303 and 305 by the clock generated by a clock generating circuit 306. Then, data of ROM 316 and 317 as against the generated address are outputted to an adder 318. The coincidence of the addition result of the adder 318 with data of a serial/parallel conversion register 207, which is obtained by latching the expectation value of the addition result inputted from the external input terminal 302 is detected by a coincidence circuit 319 so that testing is executed in the adder and ROM.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit of a computing unit for computing data in a memory when testing an LSI.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram of a test circuit of an arithmetic unit (adder) for operating data of two memories (ROM) according to a first conventional technique. External input terminal 4
ROM 414 (4-bit address, 4
(Bit data) is input. A test address signal for the ROM 415 (4-bit address, 4-bit data) is input from the external input terminals 405 to 408. When the test mode signal 411 of the adder 416 is at the L level, the selectors 412 and 413 select the test address signals input from the external input terminals 401 to 408, respectively.
Is output to the ROM 415. ROM 414 and ROM 41
5 outputs each data corresponding to the input test address signal to the adder 416. The adder 416 outputs the addition result to the external output terminals 417 to 421 to test the adder.

[0005] FIG. 5 shows a second prior art.
FIG. 3 is a block diagram of a test circuit of a computing unit (adder) that computes data of two memories (ROM). External input terminal 5
01, a test address signal of the ROM 511 (4-bit address, 4-bit data) is input from the input device 101, and the input test address signal is converted into a 4-bit serial-parallel conversion register 504 by a test clock input from the external input terminal 503. Latch. Further, a test address signal of ROM 512 (4-bit address, 4-bit data) is input from the external input terminal 502, and the input test address signal is converted into a 4-bit serial signal by a test clock input from the external input terminal 503. -Latch by the parallel conversion register 505. Selector 50
9 and the selector 510 select the data of the serial-parallel conversion register 504 and the data of the serial-parallel conversion register 505 as a test address signal when the test mode signal 508 of the adder 513 is at the L level. Respectively. The ROM 511 and the ROM 512 output data corresponding to the input test address signal to the adder 513. The adder 513 converts the addition result into a 5-bit parallel
Output to the serial conversion register 514. The parallel-serial conversion register 514 latches the operation result with a test clock input from the external input terminal 503, and switches to a serial output with a control signal input from the external input terminal 515. This serial output is output to an external output terminal 516 in response to a test clock input from an external input terminal 503 to test the adder.

[0004]

In the test circuit of the arithmetic unit for operating data of two memories according to the first prior art, the number of external terminals increases due to the configuration of the memory and the arithmetic unit. In an LSI in which the number of external terminals is limited and the absolute amount is insufficient, it is difficult to provide a large number of external terminals for testing as described above. Therefore, it is required to reduce the number of external terminals for testing. I have. Further, in a test circuit of an arithmetic unit for operating data of two memories according to the second conventional technique, a serial-to-parallel conversion is performed for a test address input, and a test result output of the arithmetic unit is also parallelized. -The test time increases to perform the serial conversion. Therefore, a reduction in test time is required.

An object of the present invention is to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a test circuit of an arithmetic unit having a small number of external test terminals and a short test time.

[0006]

A test clock input from an external input terminal is counted by a first counter to generate a first test address signal, and an arbitrary value of the first counter is counted. The second counter generates a second test address signal. The first and second test address signals are applied to the respective memories to output respective data, and the data is added and output, thereby testing the adder and the memory.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An arithmetic unit test circuit according to the present invention provides a first counter which operates with a test clock input from an external input terminal at the time of a test, and an enable signal for an arbitrary value of the first counter. A second counter for counting a test clock, a first counter for selecting one of a test address signal of the first memory generated by the first counter and an address signal of the first memory during normal operation. A selector, and a second selector for selecting one of a test address signal for the second memory generated by the second counter and an address signal for a normal operation of the second memory; Is output to an external terminal to test the arithmetic unit.

Further, in addition to the above configuration, there is provided a first matching circuit which receives an expected output value of the arithmetic unit input from an external input terminal and an output of the arithmetic unit, and outputs an output of the first matching circuit to an external unit. It has a configuration that enables testing of the arithmetic unit by outputting to a terminal.

Further, in addition to the above configuration, a serial-parallel conversion register for latching an expected output value of an arithmetic unit input from an external terminal by a test clock, and a clock for a first counter and a second counter are provided. A clock generation circuit for generating the data, and a second circuit for detecting a match between the data of the serial-parallel conversion register and the output result of the arithmetic unit
And outputting the output of the second matching circuit to an external terminal to enable a test of the arithmetic unit.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

Embodiment 1 FIG. 1 is a block diagram of a test circuit of an adder 114 for adding data of ROMs 112 and 113, which are two read-only memories. This test circuit is incorporated in a large-scale integrated circuit (hereinafter, referred to as LSI). In FIG. 1, the counter 102 is a 4-bit counter. The decoder 103 is connected to the counter 102. The output terminal of the decoder 103 is connected to the ROM 112 and 113, and the output terminals of the 4-bit counter 104 selectors 110 and 111 are connected to the ROM 112 and 113, respectively. ROM1
Output terminals of 12 and 113 are connected to an adder 114 to be tested.

The operation of the test circuit of the adder 114 configured as described above will be described with reference to the waveform diagram of FIG. At the time of testing the LSI, a test clock (FIG. 4B) is input from the external input terminal 101. The counter 102 counts the test clock input from the external input terminal 101 when the test mode signal 109 (a in FIG. 4) is at the L level. The counter 102 indicates “000
By repeating the count of “0” to “1111” (BIN), the test ROM address signal 107
(C in FIG. 4). The decoder 103 decodes the value of “1111” of the counter 102 and outputs an H-level signal. The counter 104 counts the test clock input from the external input terminal 101 when the signal of the decoder 103 is at the H level. The counter 104 counts “0000” to “1111” (BIN) and generates a test ROM address 108 (d in FIG. 4) for the adder. The selector 110 controls the RO in the normal operation.
M address signal 106 and test ROM address signal 1
08, the test ROM address signal 108 is selected when the test mode signal 109 is at the L level.
Output to 2. The selector 111 is a ROM for normal operation.
Address signal 105 and test ROM address signal 10
7, when the test mode signal 109 (FIG. 4A) is at the L level, the test ROM address signal 107 is selected.
Output to the ROM 113. ROM 112 and ROM 113
Outputs the data (e, f in FIG. 4) at the address designated by the test ROM address signal 108 and the test ROM address signal 107 to the adder 114. The adder 114 outputs the addition result (g in FIG. 4) to the external output terminal 11.
5 to 119. The adder can be tested based on the result of the addition.

As described above, according to the first embodiment, it is possible to generate a test address signal for a memory by a test clock input from one external input terminal 101 and perform all tests of the operation pattern. By outputting the operation result to one external output terminal, a test of the operation unit can be performed. Therefore, the number of external input / output terminals for the test can be reduced and the memory can be tested. Also,
As shown in the conventional example of FIG. 8, since the parallel-serial conversion register is not used for the output signal of the test result of the arithmetic unit, the test time can be reduced as compared with the case using the register. It should be noted that the same test can be performed in a test of a computing unit that computes data of a plurality of memories by adding a counter for generating a test address signal.

Embodiment 2 FIG. 2 shows two ROMs 217,
FIG. 18 is a block diagram of a test circuit of an adder 219 for adding data of 218. In FIG. 2, the counter 207 is 4
This is a bit counter, and the count value is
Is applied. The counter 209 is a 4-bit counter. The configurations of the selectors 215 and 216, the ROMs 217 and 218, and the adder 219 to be tested are substantially the same as those of the corresponding parts in FIG. In the second embodiment, a coincidence circuit 220 is newly provided.

The operation of the test circuit of the adder configured as described above will be described with reference to the waveform diagram of FIG. At the time of testing the LSI, a test clock (FIG. 5B) is input from the external input terminal 201. Counter 20
Reference numeral 7 counts a test clock input from the external input terminal 201 when the test mode signal 214 (FIG. 5A) is at the L level. The counter 207 indicates “000
By repeating the count of "0" to "1111" (BIN), the test ROM address signal 212 (FIG.
C) is generated. The decoder 208 decodes the value of "1111" of the counter 207 and outputs an H level signal. The counter 209 counts the test clock input from the external input terminal 201 when the signal of the decoder 208 is at the H level.
The count from “0” to “1111” (BIN) is performed to generate the test ROM address 213 (d in FIG. 5) of the adder. The selector 216 determines that the test mode signal 214 is low.
Level, the ROM address signal 210 during normal operation
And the test R in the test ROM address signal 212
The OM address signal 212 is selected and output to the ROM 218. The selector 215 determines that the test mode signal 214 is low.
Level, the ROM address signal 211 during normal operation
And test ROM address signal 213,
The OM address signal 213 is selected and output to the ROM 217. The ROM 217 and the ROM 218 store the data of the address designated by the test ROM address signal 213 and the test ROM address signal 212 (e in FIG. 5,
f) is output to the adder 219. At this time, the expected value (h in FIG. 5) of the addition result is input to the external input terminals 202 to 206, and the output of the adder 219 (g in FIG.
And an expected value are detected and output to the external output terminal 221. (I in FIG. 5) A test of the adder is possible by detecting a coincidence signal of an H level output in the case of coincidence.

As described above, according to the second embodiment, a test address signal for a memory is generated by a test clock input from one external input terminal 201, and all tests of the operation pattern can be performed. External input terminal 202
The expected output value of the operation result is input from .about.206, the operation unit is tested by detecting coincidence with the operation result, and is output to one external output terminal 221. Since the number of external input / output terminals for testing is reduced and the memory can be tested, and because the parallel-serial conversion register is not used for the output signal of the test result of the arithmetic unit,
Test time can be reduced. It should be noted that the same test can be performed in a test of a computing unit that computes data in a plurality of memories by adding a counter for generating a test address signal.

<< Embodiment 3 >> FIG. 3 shows two ROMs 316,
FIG. 13 is a block diagram of a test circuit of an adder 318 for adding data 317. In FIG. 3, the counter 303 indicates 4
It is a bit counter, and the count value is
Is applied. The counter 305 is a 4-bit counter. The clock generation circuit 306 includes counters 303 and 305
It is connected to the. Serial-parallel conversion register 3
07 is a 5-bit register. Selectors 314 and 3
Reference numeral 15 selects the output of the ROMs 316 and 317, respectively. The outputs of the ROMs 316 and 317 are applied to an adder 318 to be tested. The output of the serial-parallel conversion register 307 and the output of the adder are applied to the matching circuit 319.

The operation of the test circuit of the adder 318 configured as described above will be described with reference to the waveform diagram of FIG. At the time of testing the LSI, a test clock (FIG. 6B) is input from the external input terminal 301. When the test mode signal 313 (a in FIG. 6) is at the L level, the clock generation circuit 306 converts five test clocks input from the external input terminal 301 into one clock and generates the generated clock 308 (FIG. 6). c). The counter 303 counts the generated clock 308 when the test mode signal 313 is at the L level. The counter 303 repeats counting from “0000” to “1111” (BIN), and repeats the test ROM address signal 31 for the adder.
1 (d in FIG. 6) is generated. The decoder 304 decodes the value of “1111” of the counter 303 and outputs an H level signal to the counter 305. The counter 305 is
When the signal of the decoder 304 is at the H level, the clock 308
Count. The counter 305 ranges from “0000” to “1”.
111 "(BIN) is counted to generate an adder test ROM address 312 (FIG. 6e). When the test mode signal 313 is at the L level, the selector 314 selects the test ROM address signal 312 from the ROM address signal 310 and the test ROM address signal 312 during normal operation, and outputs the selected signal to the ROM 316. When the test mode signal 313 is at L level, the selector 315 selects the ROM address signal 309 for normal operation and the test ROM address signal 311 from the test ROM address signal 311 and outputs the selected ROM address signal 311 to the ROM 317. RO
M316 and ROM 317 are respectively a test ROM address signal 312 and a test ROM address signal 311.
Outputs the data (g, h in FIG. 6) at the address designated by the adder 318 to the adder 318. The expected value of the addition result is input to the external input terminal 302, and is latched by the serial-parallel conversion register 307 according to the test clock input from the external input terminal 301. In the matching circuit 319, the adder 31
8 (h in FIG. 6) and the expected output value data latched in the serial-parallel conversion register 307 (FIG. 6).
(I) is detected and output to the external output terminal 320. When a match occurs, an adder test can be performed by detecting a match signal of an H level output in five clock cycles of the test clock.

As described above, according to the third embodiment, a test address signal for a memory is generated by a test clock input from one external input terminal 301, and all tests of the operation pattern can be performed. An expected value of the operation result is input from another external input terminal 302 and latched in a serial-parallel conversion register by a test clock. Then, the arithmetic unit is tested by detecting a match between the data of the operation result and the data of the serial-parallel conversion register and outputting the data to one external output terminal 320. Therefore, the number of external input / output terminals for testing can be reduced and the memory can be tested. In addition, since the parallel-serial conversion register is not used for the test result output signal of the arithmetic unit, the test time can be reduced. It becomes possible. It should be noted that the same test can be performed in a test of a computing unit that computes data in a plurality of memories by adding a counter for generating a test address signal.

[0020]

As described above, according to the present invention, a test address signal for a memory is generated by a test clock input from one external input terminal 101, and the operation result is output to one external output terminal. By outputting the data, a test of the arithmetic unit can be performed. Therefore, the number of external input / output terminals for the test can be reduced and the memory can be tested. Further, since the parallel-serial conversion register is not used for the output signal of the test result of the arithmetic unit, the test time can be reduced.

A test address signal for a memory is generated by a test clock input from one external input terminal 201, and the external input terminals 202 to 20 are generated.
6, the expected output value of the operation result is input, and the operation unit is tested by detecting the coincidence with the operation result, and is output to one external output terminal 221. The number of external input / output terminals for testing is reduced and the memory can be tested. In addition, since the parallel-serial conversion register is not used for the output signal of the test result of the computing unit, the test time can be reduced. It becomes possible.

Further, a test address signal for a memory is generated from one external input terminal 301 by a test clock, and an expected value of the operation result is input from another external input terminal 302. Latch into the serial-parallel conversion register. Then, the arithmetic unit is tested by detecting a match between the data of the operation result and the data of the serial-parallel conversion register and outputting the data to one external output terminal 320. Therefore, the number of external input / output terminals for testing can be reduced and the memory can be tested. In addition, since the parallel-serial conversion register is not used for the test result output signal of the arithmetic unit, the test time can be reduced. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram of a computing unit test circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a computing unit test circuit according to a second embodiment of the present invention;

FIG. 3 is a block diagram of a computing unit test circuit according to a third embodiment of the present invention;

FIG. 4 is an operation waveform diagram of a computing unit test circuit according to the first embodiment of the present invention.

FIG. 5 is an operation waveform diagram of a computing unit test circuit according to a second embodiment of the present invention.

FIG. 6 is an operation waveform diagram of a computing unit test circuit according to Embodiment 3 of the present invention.

FIG. 7 is a block diagram of an arithmetic unit test circuit according to a first conventional example;

FIG. 8 is a block diagram of an arithmetic unit test circuit according to a second conventional example.

[Explanation of symbols]

 101 Test clock external input terminal 102, 104 Counter 103 Decoder 105, 106 ROM address signal 107, 108 for normal operation ROM address signal 109 for test 109 Test mode signal of adder 110, 111 Selector 112, 113 ROM 114 Adder 115 To 119 adder data external output terminal 201 test clock external input terminal 202 to 206 adder output expected value external input terminal 207, 209 counter 208 decoder 210, 211 ROM address signal during normal operation 212, 213 test ROM address signal 214 Test mode signal of adder 215, 216 Selector 217, 218 ROM 219 Adder 220 Match circuit 221 Match circuit output signal external output terminal 301 Test clock external input terminal 302 Adder output expected value external input terminal 303, 305 Counter 304 Decoder 306 Clock generation circuit 307 Serial-parallel conversion register 308 Clock generated by clock generation circuit 309, 310 ROM address signal during normal operation 311, 312 Test ROM address signal 313 adder test mode signal 314,315 selector 316,317 ROM 318 adder 319 match circuit 320 match circuit output signal external output terminal

Claims (3)

[Claims] 1. A test circuit for counting a test clock input from an external input terminal during a test of a computing unit for computing data in a first memory and a second memory built in a large-scale integrated circuit (LSI). 1 counter; a second counter that counts the test clock using an arbitrary value of the first counter as an enable signal; and an address signal of the first memory generated by the first counter. And a first selector for selecting any one of the address signals during normal operation of the first memory; an address signal of the second memory generated by the second counter; and a normal selector of the second memory. A second selector for selecting one of the address signals during operation;
A computing unit that computes both outputs of the memory and the second memory and outputs output data to an external output terminal. 2. An arithmetic unit test according to claim 1, further comprising an external input terminal for inputting an expected value of an output result of said arithmetic unit, and a matching circuit for comparing said expected value with output data of said arithmetic unit. circuit. 3. A serial-to-parallel conversion register that latches an expected output value of the arithmetic unit with the test clock, and a clock that generates clocks of the first counter and the second counter with the test clock. A generating circuit, and a matching circuit for comparing data of the serial-parallel conversion register with output data of the arithmetic unit,
3. The test circuit according to claim 1, wherein the output of the match circuit is output to an external output terminal.