JPH1168322A - Multi-layer printed wiring board - Google Patents

Multi-layer printed wiring board

Info

Publication number
JPH1168322A
JPH1168322A JP22723197A JP22723197A JPH1168322A JP H1168322 A JPH1168322 A JP H1168322A JP 22723197 A JP22723197 A JP 22723197A JP 22723197 A JP22723197 A JP 22723197A JP H1168322 A JPH1168322 A JP H1168322A
Authority
JP
Japan
Prior art keywords
line
signal
layer
power supply
dielectric constant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22723197A
Other languages
Japanese (ja)
Other versions
JP3058608B2 (en
Inventor
Yasuji Hiramatsu
靖二 平松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP22723197A priority Critical patent/JP3058608B2/en
Publication of JPH1168322A publication Critical patent/JPH1168322A/en
Application granted granted Critical
Publication of JP3058608B2 publication Critical patent/JP3058608B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a multi-layer printed wiring board capable of raising density while reducing crosstalk noise and steepening the rise of the waveform of signals. SOLUTION: An inter-line insulation layer 36 for insulating a signal line 40S, a ground line 40G and a power supply line 40P is turned to a high dielectric constant and inter-layer insulation layers 30 and 130 for insulating layers are formed at a low dielectric constant. Since the coupling capacity of the signal lines 40S and 140S of upper and lower layers is lowered because the dielectric constant of the inter-layer insulation layer 30 is low, crosstalk between the signal lines of the upper and lower layers is reduced. Also, since the dielectric constant of the inter-line insulation layer 36 for insulating the signal line 40S, the ground line 40G and the power supply line 40P of the same conductor layer is high, it becomes similar to the case of equivalently bringing the signal line 40S and the ground line 40G and the power supply line 40P close and disposing them and the waveform of the signals (pulses) transmitted through the signal line is not made dull. That is, the leakage of an electric field becomes small and the rise of the waveform of the signals is quickened.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、同一の導体層に
おいて、電源線およびグランド線で信号線が挟まれる
か、もしくは同一の導体層において、電源線またはグラ
ンド線で信号線が囲まれてなり、上層と下層の導体回路
が層間絶縁剤により絶縁される多層プリント配線板に関
するものである。
The present invention relates to a power supply line and a ground line in a same conductor layer, or a power supply line or a ground line in a same conductor layer. The present invention relates to a multilayer printed wiring board in which upper and lower conductive circuits are insulated by an interlayer insulating agent.

【0002】[0002]

【従来の技術】多層プリント配線板は、信号線間のクロ
ストークノイズを低減すると共に、信号の波形の立ち上
がりが鈍るのを防ぐ必要がある。ここで、クロストーク
ノイズとは、1の信号線が隣接する他の信号線との容量
結合により、該他の信号線上の信号の影響を受けること
を言う。信号の波形の立ち上がりの鈍りとは、1の信号
線上に図7(A)に示すようにパルスPが伝送される際
に、他の信号線との間の影響を受けると、図7(B)に
示すようにパルスPの立ち上がりが鈍ることを言う。こ
こで、かかる立ち上がりの鈍りがあると、時刻T1にて
パルスを送出した際に、受信側でt時間遅延した時刻T
2にてパルスPの立ち上がりを検出することになり、信
号の伝送に遅れが発生する。かかる、伝送の遅れを最小
限に止めるため、波形の立ち上がりを急峻となるように
する必要がある。
2. Description of the Related Art In a multilayer printed wiring board, it is necessary to reduce crosstalk noise between signal lines and to prevent the rise of signal waveform from becoming dull. Here, the crosstalk noise means that one signal line is affected by a signal on another signal line due to capacitive coupling with an adjacent signal line. The blunt rising of the signal waveform means that when a pulse P is transmitted on one signal line as shown in FIG. 7A and is affected by another signal line, the signal P shown in FIG. ) Means that the rise of the pulse P becomes dull. Here, if there is such a slowdown in the rising, when the pulse is transmitted at the time T1, the time T delayed by the time t on the receiving side is obtained.
2, the rising of the pulse P is detected, and a delay occurs in signal transmission. In order to minimize such transmission delay, it is necessary to make the waveform rise steeply.

【0003】このように、信号線間のクロストークノイ
ズを低減すると共に、信号の波形の立ち上がりを急峻に
するために、図8(A)に示すように一層の全面に電源
膜40Pを設けた電源層L1を形成し、また、全面にグ
ランド340Gを設けたグランド層L4とし、その間の
層L2、L3に信号線40S、140Sを設ける構成が
採用されていた。しかしながら、図8(A)に示す構成
では、電源層L1およびグランド層L4に一層全てが費
やされるため、高密度化に一定の限界が見られた。そこ
で、図8(B)に示すように同一の導体層L2におい
て、信号線140Sをグランド線140Gおよび電源線
140Pで挟み、同様に導体層L1において、信号線4
0Sをグランド線40Gおよび電源線40Pで挟む構成
や、或いは、図8(C)に示すような信号線40Sをグ
ランド線40G(または電源線)で囲む構成が提案され
ている。
As described above, in order to reduce the crosstalk noise between signal lines and to make the rising of the signal waveform sharp, a power supply film 40P is provided on the entire surface as shown in FIG. The power supply layer L1 is formed, the ground layer 340G is provided on the entire surface as the ground layer L4, and the signal lines 40S and 140S are provided in the layers L2 and L3 therebetween. However, in the configuration shown in FIG. 8A, since all of the layers are consumed in the power supply layer L1 and the ground layer L4, there is a certain limit in increasing the density. Therefore, as shown in FIG. 8B, in the same conductor layer L2, the signal line 140S is sandwiched between the ground line 140G and the power supply line 140P.
A configuration in which 0S is sandwiched between a ground line 40G and a power supply line 40P, or a configuration in which a signal line 40S is surrounded by a ground line 40G (or a power supply line) as shown in FIG.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、図8
(B)及び図8(C)に示す構成ではクロストークノイ
ズが大きく、また、信号の波形の立ち上かりが遅いとい
う問題が見られた。本発明者は、この問題の原因が、信
号線−電源線間、信号線−グランド線間の材料と信号線
同士を絶縁する層間の材料が同一であり、誘電率が同じ
であることに問題があることを知見した。
However, FIG.
In the configurations shown in FIGS. 8B and 8C, there were problems that the crosstalk noise was large and the rise of the signal waveform was slow. The present inventor has found that the cause of this problem is that the material between the signal line and the power supply line and between the signal line and the ground line and the material between the layers that insulate the signal lines are the same and have the same dielectric constant. It was found that there is.

【0005】本発明は、上述した課題を解決するために
なされたものであり、その目的とするところは、クロス
トークノイズを低減し、信号の波形の立ち上がりを急峻
にしながら、高密度化を図れる多層プリント配線板を提
供することにある。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to reduce crosstalk noise and increase the density of a signal while steeply rising a signal waveform. It is to provide a multilayer printed wiring board.

【0006】[0006]

【課題を解決するための手段】請求項1の発明は、上記
目的を達成するため、同一の導体層において、電源線お
よびグランド線で信号線が挟まれるか、もしくは同一の
導体層において、電源線またはグランド線で信号線が囲
まれてなる構成を、少なくとも2層以上有する多層プリ
ント配線板において、線間を絶縁する材料は層間を絶縁
する材料よりも誘電率が高いことを技術的特徴とする。
According to a first aspect of the present invention, in order to achieve the above object, a signal line is sandwiched between a power supply line and a ground line in the same conductor layer, or a power supply line is provided in the same conductor layer. In a multilayer printed wiring board having at least two or more layers in which a signal line is surrounded by a line or a ground line, a technical feature is that a material for insulating between lines has a higher dielectric constant than a material for insulating between layers. I do.

【0007】請求項2では、請求項1において、同一の
導体層において、電源線およびグランド線で、もしく
は、電源線またはグランド線で複数の信号線が囲まれて
なることを技術的特徴する。
According to a second aspect of the present invention, in the first aspect, a plurality of signal lines are surrounded by a power supply line and a ground line, or a plurality of signal lines are surrounded by the power supply line and the ground line in the same conductor layer.

【0008】請求項3では、請求項1又は2において、
前記線間を絶縁する材料、及び、前記層間を絶縁する材
料は、樹脂に無機粒子を添加してなることを技術的特徴
とする。
[0008] In claim 3, in claim 1 or 2,
A technical feature is that the material for insulating between the lines and the material for insulating between the layers are obtained by adding inorganic particles to a resin.

【0009】請求項1では、層間を絶縁する材料の誘電
率が低いため、上下層の信号線の結合容量が低下するの
で、上下の層の信号線間でのクロストークが低減され
る。また、同一導体層の信号線間を絶縁する材料が誘電
率が高いために、等価的に信号線に隣接する電源線又は
グランド線と近接させて配設したのと同様になり、信号
線を伝送される信号(パルス)を波形を鈍らせなくな
る。即ち、電界の漏れが小さくなり、信号の波形の立ち
上がりが速くなる。
According to the first aspect, since the dielectric constant of the material that insulates the layers is low, the coupling capacitance of the signal lines in the upper and lower layers is reduced, so that the crosstalk between the signal lines in the upper and lower layers is reduced. In addition, since the material that insulates between signal lines in the same conductor layer has a high dielectric constant, it is equivalent to being disposed close to a power supply line or a ground line equivalently adjacent to a signal line. The transmitted signal (pulse) is not blunted. That is, the leakage of the electric field is reduced, and the rise of the signal waveform is accelerated.

【0010】請求項2では、複数の信号線を、電源線お
よびグランド線、もしくは、電源線またはグランド線で
挟むことで、配線中の信号線の割合を高め、多層プリン
ト配線板の高密度化を図ることが可能となる。
According to a second aspect of the present invention, a plurality of signal lines are sandwiched between a power supply line and a ground line, or a power supply line or a ground line, thereby increasing the ratio of signal lines in the wiring and increasing the density of the multilayer printed wiring board. Can be achieved.

【0011】請求項3では、線間を絶縁する材料及び層
間を絶縁する材料を、樹脂に無機粒子を添加して構成す
るため、容易に誘電率を調整することができる。ここ
で、無機粒子としては、アルミナ、チタニア、ガラスな
どがよい。
According to the third aspect of the present invention, since the material for insulating between lines and the material for insulating between layers are formed by adding inorganic particles to a resin, the dielectric constant can be easily adjusted. Here, as the inorganic particles, alumina, titania, glass and the like are preferable.

【0012】[0012]

【発明の実施の形態】以下、本発明の第1実施形態に係
る多層プリント配線板について図を参照して説明する。
先ず、多層プリント配線板の構成について、図4(A)
を参照して説明する。この第1実施形態のプリント配線
板は、第1の導体層L1と第2の相対層L2とを絶縁す
る層間絶縁層130が低い誘電率となるように構成され
ている。また、第1導体層L1上に配設される信号線4
0Sが、グランド線40Gと電源線40Pとの間に配設
され、該信号線40S、グランド線40G、電源線40
Pを絶縁する線間絶縁層36の誘電率が、上述した層間
絶縁層30の誘電率よりも高いように構成されている。
同様に、第2導体層L2上の信号線140S、グランド
線140G、電源線140P、及び、線間絶縁層136
が形成されている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer printed wiring board according to a first embodiment of the present invention will be described below with reference to the drawings.
First, the configuration of the multilayer printed wiring board will be described with reference to FIG.
This will be described with reference to FIG. The printed wiring board of the first embodiment is configured such that the interlayer insulating layer 130 that insulates the first conductor layer L1 and the second relative layer L2 has a low dielectric constant. Also, the signal line 4 provided on the first conductor layer L1
0S is disposed between the ground line 40G and the power supply line 40P, and the signal line 40S, the ground line 40G, and the power supply line 40P.
The dielectric constant of the line insulating layer 36 that insulates P is configured to be higher than the dielectric constant of the interlayer insulating layer 30 described above.
Similarly, the signal line 140S, the ground line 140G, the power supply line 140P, and the line insulating layer 136 on the second conductor layer L2
Are formed.

【0013】ここで、第1導体層L1上の信号線40S
と、第2導体層L2上の信号線140Sとの間を層間絶
縁層130は、誘電率が低く構成されているため、該信
号線40Sと信号線140Sとの間の容量結合係数が下
がり、両信号線40S、140S間のクロストークが軽
減される。
Here, the signal line 40S on the first conductor layer L1
And the signal line 140S on the second conductor layer L2, the interlayer insulating layer 130 is configured to have a low dielectric constant, so that the capacitive coupling coefficient between the signal line 40S and the signal line 140S decreases, Crosstalk between both signal lines 40S and 140S is reduced.

【0014】また、信号線40Sと電源線40P又はグ
ランド線40Gとの間の線間絶縁層36は、誘電率が高
いため、等価的に信号線40Sに隣接する電源線40P
又はグランド線40Gと近接させて配設したのと同等に
なり、信号線40Sを伝送される信号(パルス)を波形
を鈍らせなくなる。即ち、電界の漏れが小さくなり、信
号の波形の立ち上がりが速くなる。
The inter-layer insulating layer 36 between the signal line 40S and the power supply line 40P or the ground line 40G has a high dielectric constant, and is equivalently equivalent to the power supply line 40P adjacent to the signal line 40S.
Alternatively, it is equivalent to being disposed close to the ground line 40G, and the waveform of the signal (pulse) transmitted on the signal line 40S is not dulled. That is, the leakage of the electric field is reduced, and the rise of the signal waveform is accelerated.

【0015】この現象について、図5(A)及び図5
(B)を参照して説明する。図5(A)は、信号線40
Sとグランド線40Pとを離して配置した場合の磁力線
分布を破線で示し、電力線分布を実線で示している。ま
た、図5(B)に信号線40Sとグランド線40Pとを
近接させて配置した場合の磁力線分布及び電力線分布を
示している。図5(A)に示すように信号線40Sとグ
ランド線40Pとを離して配置した場合には、第1導体
層L1の信号線40Sからの磁力線及び電力線が、第2
導体層L2の信号線140Sと多く交差している。これ
に対して、図5(B)に示すように信号線40Sとグラ
ンド線40Pとを近接して配置した場合には、第1導体
層L1の信号線40Sからの磁力線及び電力線が、第2
導体層L2の信号線140Sと交差し難くなる。ここ
で、該信号線40Sとグランド線40Pと間を絶縁する
線間絶縁層36(図4(A)参照)の誘電率を高めるこ
とは、等価的に図5(B)に示すように信号線40Sと
グランド線40Pとを近接して配置することに相当し、
第1導体層L1の信号線40Sからの影響を第2導体層
L2の信号線140Sが受け難くなる。このため、図7
(A)、図7(B)を参照して上述したように信号線4
0Sを伝送される信号(パルス)の波形を鈍らせなくな
り、等価的にパルスの伝送速度を高めることが可能とな
る。
FIG. 5A and FIG.
This will be described with reference to FIG. FIG. 5A shows the signal line 40.
The magnetic field line distribution when S and the ground line 40P are arranged apart from each other is indicated by a broken line, and the power line distribution is indicated by a solid line. FIG. 5B shows a distribution of magnetic force lines and a distribution of power lines when the signal line 40S and the ground line 40P are arranged close to each other. When the signal line 40S and the ground line 40P are arranged apart from each other as shown in FIG. 5A, the magnetic lines and the power lines from the signal line 40S of the first conductor layer L1 are connected to the second line.
Many intersect with the signal line 140S of the conductor layer L2. On the other hand, when the signal line 40S and the ground line 40P are disposed close to each other as shown in FIG. 5B, the magnetic lines and the power lines from the signal line 40S of the first conductor layer L1
It becomes difficult to cross the signal line 140S of the conductor layer L2. Here, increasing the dielectric constant of the line insulating layer 36 (see FIG. 4A) that insulates the signal line 40S from the ground line 40P is equivalent to increasing the dielectric constant as shown in FIG. 5B. This corresponds to disposing the line 40S and the ground line 40P close to each other,
The signal lines 140S of the second conductor layer L2 are less likely to be affected by the signal lines 40S of the first conductor layer L1. Therefore, FIG.
(A), the signal line 4 as described above with reference to FIG.
The waveform of the signal (pulse) transmitted through the 0S is not dulled, and the transmission speed of the pulse can be equivalently increased.

【0016】引き続き、該低誘電率の層間絶縁剤と、高
誘電率の線間絶縁剤の製造方法に付いて述べる。ここで
は、先ず、層間絶縁剤の調製について説明する。 (a)脂環式エポキシ樹脂(大日本インキ株式会社製、
EPlCLONHP−7200)を45重量部、感光性
モノマー(東亜合成製:商品名アロニックスM315)
10重量部、消泡剤(サンノプコ製 S−65)0.5
重量部、NMPを3.6重量部を撹拌混合する。
Subsequently, a method of manufacturing the low dielectric constant interlayer insulating material and the high dielectric constant line insulating material will be described. Here, first, the preparation of the interlayer insulating agent will be described. (A) Alicyclic epoxy resin (manufactured by Dainippon Ink and Chemicals, Inc.
45 parts by weight of EPlCLONHP-7200) and a photosensitive monomer (trade name: Aronix M315, manufactured by Toagosei Co., Ltd.)
10 parts by weight, 0.5 of defoamer (S-NOPCO S-65)
Parts by weight and 3.6 parts by weight of NMP are stirred and mixed.

【0017】(b)ポリフェニレンエーテル(PPE)
12重量部、エポキシ樹脂粒子(三洋化成製 商品名
ポリマーポール)の平均粒径1.0μmを7.2重量
部、平均粒径0.5μmのものを3.09重量部を混合
した後、さらにNMP30重量部を添加し、ビーズミル
で撹拌混合する。
(B) Polyphenylene ether (PPE)
12 parts by weight, epoxy resin particles (trade name of Sanyo Chemical Industries, Ltd.)
After mixing 7.2 parts by weight of an average particle diameter of 1.0 μm and 3.09 parts by weight of an average particle diameter of 0.5 μm, further add 30 parts by weight of NMP, and stir and mix with a bead mill.

【0018】(c)イミダゾール硬化剤(四国化成製:
商品名2E4MZ−CN)2重量部、光開始剤(チバガ
イギー製 イルガキュア l−907)2重量部、光増
感剤(日本化薬製:DETX−S)0.2重量部、NM
Pl.5重量部を撹拌混合する。これら(a)、
(b)、(c)を混合して層間絶縁剤を得る。誘電率は
約3.3である。
(C) imidazole curing agent (Shikoku Chemicals:
2E4MZ-CN (trade name), 2 parts by weight of photoinitiator (Irgacure 1-907, Ciba-Geigy), 0.2 part by weight of photosensitizer (DETX-S, manufactured by Nippon Kayaku), NM
Pl. Stir and mix 5 parts by weight. These (a),
(B) and (c) are mixed to obtain an interlayer insulating agent. The dielectric constant is about 3.3.

【0019】引き続き、線間絶縁剤の製造について説明
する。 (d)クレゾールノポラック型エポキシ樹脂(日本化薬
製)のエポキシ基50%をアクリル化した感光性付与の
オリゴマー(分子量4000)を100重量部、メチル
エチルケトンに溶解させた20重量%のビスフェノール
A型エポキシ樹脂(油化シェル製 エピコート100
1)32重量部、感光性モノマーである多価アクリルモ
ノマー(日本化薬製 R604)6.4重量部、同じく
感光性モノマーである多価アクリルモノマー(共栄社化
学製、DPE6A)3.2重量部を混合し、さらにレベ
リング剤(共栄社化学製 ポリフローNo.75)を全
重量100重量部に対して0.5重量部混合して撹拌混
合する。
Next, the production of the line insulating agent will be described. (D) 20 parts by weight of bisphenol A type obtained by dissolving 100 parts by weight of a photosensitizing oligomer (molecular weight 4000) obtained by acrylate of 50% of an epoxy group of cresol nopolak type epoxy resin (manufactured by Nippon Kayaku) in methyl ethyl ketone Epoxy resin (Epicoat 100 made by Yuka Shell)
1) 32 parts by weight, 6.4 parts by weight of a polyacrylic monomer which is a photosensitive monomer (Nippon Kayaku R604), 3.2 parts by weight of a polyvalent acrylic monomer which is also a photosensitive monomer (DPE6A, manufactured by Kyoeisha Chemical) , And 0.5 part by weight of a leveling agent (Polyflow No. 75 manufactured by Kyoeisha Chemical Co., Ltd.) with respect to 100 parts by weight of the total weight, and then stirring and mixing.

【0020】(e)イミダゾール硬化剤(四国化成製:
商品名2E4MZ−CN)3.4重量部、光開始剤(チ
バガイギー製 イルガキュア I−907)2重量部、
光増感剤(日本化薬製:DETX−S)0.2重量部、
チタニア(平均粒径1.6μm)を60重量部、NMP
1.5重量部を撹拌混合する。これら(d)、(e)を
混合して線間絶縁剤を得る。誘電率は約4.7である。
(E) Imidazole curing agent (Shikoku Chemicals:
3.4 parts by weight of trade name 2E4MZ-CN), 2 parts by weight of a photoinitiator (Irgacure I-907 manufactured by Ciba Geigy),
0.2 parts by weight of a photosensitizer (DETX-S manufactured by Nippon Kayaku)
60 parts by weight of titania (average particle size 1.6 μm), NMP
Stir and mix 1.5 parts by weight. These (d) and (e) are mixed to obtain a line insulating agent. The dielectric constant is about 4.7.

【0021】引き続き、上述した層間絶縁剤及び線間絶
縁剤を用いる多層プリント配線板の製達行程について、
図1〜図3を参照して説明する。 (1)厚さ1mmのガラスエポキシ樹脂またはBT(ビ
スマレイミドトリアジン)樹脂からなる基板20の両面
に18μmの銅箔22がラミネートされている銅張積層
板20aを出発材料とする(図1(A))。まず、この
銅張積層板20aをドリル削孔し、スルーホール用の通
孔24を形成してから、めっきレジストを形成した後、
無電解めっき処理してスルーホール26を形成する(図
1(B))さらに、銅箔22を常法に従いパターン状に
エッチングすることにより、基板20の両面に内層銅パ
ターン28を形成する(図1(C))。
Subsequently, regarding the process of manufacturing a multilayer printed wiring board using the above-described interlayer insulating agent and line-to-line insulating agent,
This will be described with reference to FIGS. (1) A starting material is a copper-clad laminate 20a in which 18 μm copper foils 22 are laminated on both sides of a substrate 20 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 1 mm (FIG. 1 (A) )). First, this copper clad laminate 20a is drilled to form a through hole 24 for a through hole, and then a plating resist is formed.
Electroless plating is performed to form through-holes 26 (FIG. 1B). Further, copper foil 22 is etched in a pattern according to a conventional method to form inner layer copper patterns 28 on both surfaces of substrate 20 (FIG. 1B). 1 (C)).

【0022】(2)上述したように調製した樹脂絶縁剤
群(a)、(b)、(c)を撹拌混合し、樹脂絶縁剤を
調製した後、該樹脂絶縁剤を基板20表面にロールコー
タにて均一に塗布すると共に、スルーホール26内に充
填する。さらに水平状態で20分間放置してから、60
℃で30分の乾燥を行い、厚さ35μmの層間絶縁層3
0を形成する(図1(D))
(2) The resin insulating agent groups (a), (b) and (c) prepared as described above are stirred and mixed to prepare a resin insulating agent, and then the resin insulating agent is rolled on the surface of the substrate 20. It is applied uniformly by a coater and filled in the through holes 26. After standing for 20 minutes in a horizontal state,
Dried at 30 ° C. for 30 minutes to form an interlayer insulating layer 3 having a thickness of 35 μm.
0 (FIG. 1 (D))

【0023】(3)層間絶縁層30を形成した基板20
の両面に、85μmφの黒円32aが印刷されたフォト
マスクフィルム32を密着させ、超高圧水銀灯により5
00mJ/cm2 で露光する(図1(E))。これをD
MTG溶液でスプレー現像することにより、層間絶縁層
30に85μmφのバイアホールとなる開口を形成す
る。さらに、当該基板を超高圧水銀灯により3000m
J/cm2 で露光し、100℃で1時間、その後150
℃で5時間の加熱処理をすることにより、フォトマスク
フィルムに相当する寸法精度に優れた開口(バイアホー
ル形成用開口)30aを形成する。(図2(F))
(3) Substrate 20 on which interlayer insulating layer 30 is formed
A photomask film 32 on which a black circle 32a of 85 μmφ is printed is brought into close contact with both sides of
Exposure is performed at 00 mJ / cm 2 (FIG. 1E). This is D
By performing spray development with an MTG solution, an opening serving as a via hole of 85 μmφ is formed in the interlayer insulating layer 30. Further, the substrate was 3,000 m long using an ultra-high pressure mercury lamp.
Exposure at J / cm 2 , 1 hour at 100 ° C., then 150
By performing heat treatment at 5 ° C. for 5 hours, an opening (opening for forming a via hole) 30 a having excellent dimensional accuracy corresponding to a photomask film is formed. (FIG. 2 (F))

【0024】(4)開口30aの形成された基板20
を、クロム酸に2分間浸漬し、樹脂マトリックス中のエ
ポキシ樹脂粒子を溶解して、当該樹脂層間絶縁層30の
表面を粗面とし、その後、中和溶液(シプレイ社製)に
浸漬した後に水洗いする(図2(G))。
(4) The substrate 20 with the opening 30a formed
Is immersed in chromic acid for 2 minutes to dissolve the epoxy resin particles in the resin matrix to make the surface of the resin interlayer insulating layer 30 rough, and then immersed in a neutralizing solution (manufactured by Shipley Co.) and then washed with water. (FIG. 2 (G)).

【0025】(5)この粗面化処理(粗化深さ6μm)
を行った基板にパラジウム触媒(アトテック製)を付与
することにより、樹脂層間絶縁層30及びバイアホール
用開口30aに触媒核を付ける。
(5) This roughening treatment (roughening depth 6 μm)
By applying a palladium catalyst (manufactured by Atotech) to the substrate subjected to the above, a catalyst nucleus is attached to the resin interlayer insulating layer 30 and the via hole opening 30a.

【0026】(6)上述したように調整した線間絶縁層
の組成物(d)、(e)を撹拌混合し液状レジストを用
意する。 (7)上記の触媒核付与の処理を終えた基板の両面に、
上記液状レジストをロールコーターを用いて塗布し、6
0℃で30分の乾燥塊を行い厚さ30μmレジスト層3
2を形成する(図2(H))。
(6) The compositions (d) and (e) of the line insulating layer adjusted as described above are stirred and mixed to prepare a liquid resist. (7) On both surfaces of the substrate that has been subjected to the above-described process of providing catalyst nuclei,
The above liquid resist is applied using a roll coater, and 6
Dry lump for 30 minutes at 0 ° C, resist layer 3 of 30 μm thickness
2 (FIG. 2H).

【0027】(8)ついで、導体回路に対応するパター
ン34aの形成されたフォトマスクフィルム34を載置
して400mJ/cm2 の紫外線を照射し、露光する
(図2(I))。
(8) Next, the photomask film 34 on which the pattern 34a corresponding to the conductor circuit is formed is placed and irradiated with ultraviolet rays of 400 mJ / cm 2 (FIG. 2 (I)).

【0028】(9)フォトマスクフィルム34を取り除
き、レジスト層をDMTGで溶解現像し、基板20上に
導体回路パターン部の抜けたメッキ用レジストを形成
し、更に、超高圧水銀灯にて6000mJ/cm2 で露
光し、1000℃で1時間、その後、150℃で3時間
の加熱処理を行い、層間絶縁層30の上に線間絶縁層と
なる永久レジスト36を形成する(図3(J))。
(9) The photomask film 34 is removed, the resist layer is dissolved and developed with DMTG to form a plating resist on the substrate 20 from which the conductor circuit pattern has been removed, and furthermore, 6000 mJ / cm using an ultra-high pressure mercury lamp. Exposure is performed at 2 ° C., and heat treatment is performed at 1000 ° C. for 1 hour and then at 150 ° C. for 3 hours to form a permanent resist 36 to be a line insulating layer on the interlayer insulating layer 30 (FIG. 3 (J)) .

【0029】(10)上記永久レジスト36の形成され
た基板20に、予めめっき前処理(具体的には触媒核の
活性化)を施し、その後、無電解銅めっき浴による無電
解めっきによって、レジスト非形成部に厚さ15μm程
度の無電解銅めっき38を析出させて、外層銅パターン
(図4(A)中に示すグランド線40G、電源線40
P、信号線40S)40、バイアホール42を形成する
ことにより、アディティプ法による第1導体層L1を形
成する。 金属塩…CuSO4 ・5H2 O:8.6mM 錯化剤…TEA(トリエタノールアミン):0.15M 還元剤…HCHO : 0.02M その他…安定剤(ビピリジル、フェロシアン化カリウム
等):少量 析出速度は、6μm/時間
(10) The substrate 20 on which the permanent resist 36 has been formed is subjected to a pre-plating treatment (specifically, activation of a catalyst nucleus), and then the resist is formed by electroless plating in an electroless copper plating bath. An electroless copper plating 38 having a thickness of about 15 μm is deposited on the non-formed portion to form an outer layer copper pattern (a ground line 40G and a power line 40 shown in FIG. 4A).
P, the signal line 40S) 40 and the via hole 42 are formed to form the first conductor layer L1 by the additive method. Metal salt: CuSO4 .5H2 O: 8.6 mM Complexing agent: TEA (triethanolamine): 0.15 M Reducing agent: HCHO: 0.02 M Other: Stabilizer (bipyridyl, potassium ferrocyanide, etc.): small amount 6 μm / hour

【0030】(11)このようにしてアディティプ法に
よる導体層L1を形成した後、#600のベルト研磨紙
を用いたベルトサンダー研磨により、基板20の片面
を、永久レジスト36の表層とバイアホール42の銅
(無電解めっき)38の最上面とが揃うまで研磨する
(図3(L))。引き続き、ベルトサンダーによる傷を
取り除くためにバフ研磨を行う(バフ研磨のみでもよ
い)。そして、他方の面についても同様に研磨して、基
板両面が平滑なプリント配線基板を形成する。このプリ
ント配線板は、図4(A)を参照して上述したように電
源線40Pおよびグランンド線40Gにより信号線40
Sが挟まれている構成を採用した。
(11) After the conductor layer L1 is formed by the additive method in this manner, one surface of the substrate 20 is polished with the surface layer of the permanent resist 36 and the via holes 42 by belt sanding using # 600 belt polishing paper. (FIG. 3 (L)) until the top surface of the copper (electroless plating) 38 is aligned. Subsequently, buffing is performed to remove scratches caused by the belt sander (only buffing may be performed). Then, the other surface is polished in the same manner to form a printed wiring board having both surfaces smooth. This printed wiring board is connected to the signal line 40 by the power supply line 40P and the ground line 40G as described above with reference to FIG.
A configuration in which S is sandwiched was adopted.

【0031】(12)(2)〜(11)を繰り返して、
線間絶縁層136、及び層間絶縁層130、外層銅パタ
ーン140から成る第2導体層L2をビルトアップする
ことにより、多層プリント配線板を完成する(図3
(M))。
(12) By repeating (2) to (11),
The multilayer printed wiring board is completed by building up the second conductor layer L2 including the line insulation layer 136, the interlayer insulation layer 130, and the outer copper pattern 140 (FIG. 3).
(M)).

【0032】なお、図4(A)に示す多層プリント配線
板では、電源線40Pとグランド線40Gの間に1本の
信号線40Sを配設したが、電源線40Pと電源線40
Pとの間に信号線を配設することも、また、グランド線
40Gとグランド線40Gとの間に信号線40Sを配設
することも可能である。
In the multilayer printed wiring board shown in FIG. 4A, one signal line 40S is provided between the power supply line 40P and the ground line 40G.
It is also possible to arrange a signal line between P and P, and to arrange a signal line 40S between the ground line 40G and the ground line 40G.

【0033】更に、第1実施形態の多層プリント配線板
では、図4(B)に示すように、電源線40P−グラン
ド線40G間、電源線40P−電源線40P間、又は、
グランド線40G−グランド線40G間に複数の信号線
40Sを配設することも可能である。このように複数の
信号配線を配設することで、配線中の信号線の割合を高
め、多層プリント配線板の高密度化を図ることが可能と
なる。
Further, in the multilayer printed wiring board of the first embodiment, as shown in FIG. 4B, between the power supply line 40P and the ground line 40G, between the power supply line 40P and the power supply line 40P, or
It is also possible to arrange a plurality of signal lines 40S between the ground line 40G and the ground line 40G. By arranging a plurality of signal wirings in this manner, the ratio of signal lines in the wirings can be increased, and the density of the multilayer printed wiring board can be increased.

【0034】引き続き、本発明の第2実施形態に係る多
層プリント配線板について図6を参照して説明する。図
1〜図3を参照して上述したように第1実施形態の多層
プリント配線板においては、基板20の直上に形成され
ている内層銅パターン28間には高誘電率の線間絶縁層
が設けられていなかった。これに対して、図6に示すよ
うに第2実施形態の多層プリント配線板では、内層銅パ
ターン28間に高誘電率の線間絶縁層29が設けられ
て、該内層銅パターン28でのクロストークが低減さ
れ、信号(パルス)を波形の立ち上がりの改善が図られ
ている。
Next, a multilayer printed wiring board according to a second embodiment of the present invention will be described with reference to FIG. As described above with reference to FIGS. 1 to 3, in the multilayer printed wiring board according to the first embodiment, a high dielectric constant line insulating layer is provided between the inner copper patterns 28 formed directly on the substrate 20. Was not provided. On the other hand, as shown in FIG. 6, in the multilayer printed wiring board of the second embodiment, a high dielectric constant line insulating layer 29 is provided between the inner copper The talk is reduced, and the rise of the signal (pulse) waveform is improved.

【0035】[0035]

【発明の効果】以上のように、請求項1では、層間を絶
縁する材料の誘電率が低いため、上下層の信号線の結合
容量が低下するので、上下の層の信号線間でのクロスト
ークが低減される。また、同一導体層の信号線間を絶縁
する材料が誘電率が高いために、電界の漏れが小さくな
り、信号の波形の立ち上がりが速められる。
As described above, in the first aspect, since the dielectric constant of the material that insulates the layers is low, the coupling capacitance between the signal lines in the upper and lower layers is reduced, so that the cross between the signal lines in the upper and lower layers is reduced. Talk is reduced. In addition, since the material that insulates the signal lines of the same conductor layer has a high dielectric constant, the leakage of the electric field is reduced, and the rise of the signal waveform is accelerated.

【0036】請求項2では、複数の信号線を、電源線お
よびグランド線、もしくは、電源線またはグランド線で
挟むことで、配線中の信号線の割合を高め、多層プリン
ト配線板の高密度化を図ることが可能となる。
According to a second aspect of the present invention, a plurality of signal lines are sandwiched between a power supply line and a ground line, or a power supply line or a ground line, thereby increasing the ratio of signal lines in the wiring and increasing the density of the multilayer printed wiring board. Can be achieved.

【0037】請求項3では、線間を絶縁する材料及び層
間を絶縁する材料を、樹脂に無機粒子を添加して構成す
るため、容易に誘電率を調整することができる。
According to the third aspect of the present invention, since the material for insulating lines and the material for insulating layers are formed by adding inorganic particles to a resin, the dielectric constant can be easily adjusted.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1実施形態に係る多層プリント配線
板の製造を示す行程図である。
FIG. 1 is a process chart showing the manufacture of a multilayer printed wiring board according to a first embodiment of the present invention.

【図2】本発明の第1実施形態に係る多層プリント配線
板の製造を示す行程図である。
FIG. 2 is a process chart showing the manufacture of the multilayer printed wiring board according to the first embodiment of the present invention.

【図3】本発明の第1実施形態に係る多層プリント配線
板の製造を示す行程図である。
FIG. 3 is a process chart showing the manufacture of the multilayer printed wiring board according to the first embodiment of the present invention.

【図4】図4(A)、図4(B)は、第1実施形態の多
層プリント配線板の構成を示す説明図である。
FIGS. 4A and 4B are explanatory diagrams illustrating a configuration of a multilayer printed wiring board according to the first embodiment.

【図5】図5(A)、図5(B)は、信号線と電源線と
の距離に応じた磁力線分布及び電力線分布を示す説明図
である。
FIG. 5A and FIG. 5B are explanatory diagrams showing magnetic field line distribution and power line distribution according to the distance between a signal line and a power supply line.

【図6】図6は、第2実施形態に係る多層プリント配線
板の構成を示す説明図である。
FIG. 6 is an explanatory diagram illustrating a configuration of a multilayer printed wiring board according to a second embodiment.

【図7】図7(A)、図7(B)は信号線上のパルスの
伝送波形を示す波形図である。
FIGS. 7A and 7B are waveform diagrams showing transmission waveforms of pulses on a signal line.

【図8】図8(A)、図8(B)、図8(C)は、従来
技術に係る多層プリント配線板の構成を示す説明図であ
る。
8 (A), 8 (B), and 8 (C) are explanatory diagrams showing a configuration of a multilayer printed wiring board according to a conventional technique.

【符号の説明】[Explanation of symbols]

20 基板 22 銅箔 28 内層銅パターン 30 層間絶縁層 36 線間絶縁層 40 外層銅パターン 40S 信号線 40G グランド線 40P 電源線 42 バイヤホール Reference Signs List 20 board 22 copper foil 28 inner layer copper pattern 30 interlayer insulating layer 36 inter-layer insulating layer 40 outer layer copper pattern 40S signal line 40G ground line 40P power supply line 42 via hole

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 同一の導体層において、電源線およびグ
ランド線で信号線が挟まれるか、もしくは同一の導体層
において、電源線またはグランド線で信号線が囲まれて
なる構成を、少なくとも2層以上有する多層プリント配
線板において、 線間を絶縁する材料は層間を絶縁する材料よりも誘電率
が高いことを特徴とする多層プリント配線板。
1. A structure in which a signal line is sandwiched between a power supply line and a ground line in the same conductor layer, or a signal line is surrounded by a power supply line or a ground line in the same conductor layer. The multilayer printed wiring board having the above-mentioned structure, wherein a material for insulating between lines has a higher dielectric constant than a material for insulating between layers.
【請求項2】 同一の導体層において、電源線およびグ
ランド線で、もしくは、電源線またはグランド線で複数
の信号線が囲まれてなることを特徴する請求項1の多層
プリント配線板。
2. The multilayer printed wiring board according to claim 1, wherein a plurality of signal lines are surrounded by a power line and a ground line, or a plurality of signal lines are surrounded by a power line and a ground line in the same conductor layer.
【請求項3】 前記線間を絶縁する材料、及び、前記層
間を絶縁する材料は、樹脂に無機粒子を添加してなるこ
とを特徴とする請求項1又は請求項2の多層プリント配
線板。
3. The multilayer printed wiring board according to claim 1, wherein the material for insulating between the lines and the material for insulating between the layers are formed by adding inorganic particles to a resin.
JP22723197A 1997-08-09 1997-08-09 Multilayer printed wiring board Expired - Fee Related JP3058608B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22723197A JP3058608B2 (en) 1997-08-09 1997-08-09 Multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22723197A JP3058608B2 (en) 1997-08-09 1997-08-09 Multilayer printed wiring board

Publications (2)

Publication Number Publication Date
JPH1168322A true JPH1168322A (en) 1999-03-09
JP3058608B2 JP3058608B2 (en) 2000-07-04

Family

ID=16857573

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3058608B2 (en)

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WO2007094334A1 (en) * 2006-02-16 2007-08-23 Kyocera Corporation Power supply apparatus and portable electronic device
JP2009060150A (en) * 2008-12-17 2009-03-19 Panasonic Corp Differential-balanced signal transmitting board
JP2010245573A (en) * 2010-08-03 2010-10-28 Panasonic Corp Circuit board and method of manufacturing the same
JP2011101063A (en) * 2011-02-22 2011-05-19 Panasonic Corp Method for manufacturing circuit board

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JP2002368353A (en) * 2001-06-04 2002-12-20 Ibiden Co Ltd Printed wiring board
JP2007184341A (en) * 2006-01-05 2007-07-19 Yamaha Corp Semiconductor device and circuit board
WO2007094334A1 (en) * 2006-02-16 2007-08-23 Kyocera Corporation Power supply apparatus and portable electronic device
JPWO2007094334A1 (en) * 2006-02-16 2009-07-09 京セラ株式会社 Power supply device and portable electronic device
US8035339B2 (en) 2006-02-16 2011-10-11 Kyocera Corporation Power supply device and portable electronic device
JP2009060150A (en) * 2008-12-17 2009-03-19 Panasonic Corp Differential-balanced signal transmitting board
JP4659087B2 (en) * 2008-12-17 2011-03-30 パナソニック株式会社 Differential balanced signal transmission board
JP2010245573A (en) * 2010-08-03 2010-10-28 Panasonic Corp Circuit board and method of manufacturing the same
JP2011101063A (en) * 2011-02-22 2011-05-19 Panasonic Corp Method for manufacturing circuit board

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