JPH1155338A - Digital demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To sufficiently reduce a carrier wave frequency error, and to reduce an error rate in synchronization detection. SOLUTION: In this modulator, the orthogonal detection and phase conversion of a received DQPSK(differential quadrature phase shift keying) signal is operated, a phase at each symbol point is successively latched, carrier wave frequencies are corrected by a subtracting circuit 16, a phase error (a9) based on frequency deviation is detected from one symbol delay detection outputs of circuits 6 and 7 by a phase error detecting circuit 8, and an initial value a10 is obtained by an output circuit 9, and set in a circuit 13. Afterwards, a phase error a9 is inputted to a loop filter constituted of a gain circuit 11-adder circuit 12-initial value setting circuit 13-delay circuit 14-adder adder circuit 12, the filter output is integrated by a circuit 15, and supplied as frequency error components to the circuit 16. Then, a two symbol delay detection output is supplied to the phase error detecting circuit 8, and a three symbol delay detection output is supplied to the phase error detecting circuit 8 so that a carrier wave frequency error can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator for a differentially encoded 2 ⁿ (n is an integer equal to or greater than 1) phase modulation signal, such as DQPSK, used in a digital radio communication system. The present invention relates to a digital demodulator including an automatic frequency control circuit for correcting a carrier frequency error of a signal to be processed.

[0002]

2. Description of the Related Art FIG. 3 shows a configuration example of a conventional digital demodulator. Here, π / 4 shift DQPSK (Differen
(Trial Quadrature Phase Shift Keying) Shows a circuit configuration corresponding to a modulated signal.
IEICE Technical Report). In the figure, a received signal a1 converted to an intermediate frequency band is quadrature-detected by an output signal of a local oscillation circuit 2 by a quadrature detection circuit 1 to become a complex baseband signal a2, and further converted to a phase signal a3 by a phase detection circuit 3. You. The clock recovery circuit 4 detects the clock phase of the received signal from the phase signal a3 and outputs a recovered clock a4 synchronized with the symbol identification point. The latch 5 samples the phase signal a3 at a symbol identification point given by the reproduced clock a4 and outputs a clock-synchronized phase signal a5. The phase signal a5 is subjected to frequency conversion (frequency correction) by a subtraction circuit 16 as first carrier frequency error correction means, and then outputs a frequency conversion signal a6, which is input to a subtraction circuit 7 and a one-symbol delay circuit 6 delays the frequency conversion signal a6 by one symbol period and outputs a delay signal a7. The subtraction circuit 7 calculates the difference between the frequency conversion signal a6 and the delay signal a7 (a6-a7).
And a differential detection signal a for one symbol section
8 is output.

Here, when there is no carrier frequency error, the phase angle θ _j of the j-th sample of the differential detection signal a8
Satisfies the expression (1) on the IQ plane as indicated by a circle in FIG. θ _j = qπ / 2 + π / 4 (q = 0,1,2,3) (1) On the other hand, when there is a carrier frequency error Δf, the signal points are indicated by the crosses in FIG. To rotate from the regular position
A code error due to noise is likely to occur. The relationship between Δf and phase rotation Δθ is given by equation (2). T is a symbol period.

Δθ = 2πΔfT (2) The phase error detection circuit 8 detects the magnitude of the phase rotation Δθ, performs an operation shown in Expression (3) on the delayed detection signal a8, and performs a phase rotation signal a9 Is output. Δθ _j = φ _j −θ _j (3) where φ _j is the delay detection signal of the j-th sample, and θ _j is q when q is selected so as to take a value closest to φ _j in equation (1). Is the phase angle determination signal.

The frequency error detection circuit 9 performs the following processing on the phase rotation signal to detect a carrier frequency error. A plurality of paths for adding different fixed values φ _P to the phase rotation signal Δθ _j as shown in Expression (4) are prepared, and u
Averaging is performed after the modulo operation represented by (θ),
Obtain an average value S _{P. S P = (1 / N)} Σ i = 1 N u (Δθ j + φ P), (4) Then, the average value S _P is converted into a carrier frequency error Δf after subtracting the fixed value φ _P as shown in Expression (5).

[0006] Δf = (1 / (2πT) ) (S P -φ P) ......... (5) to select or combine the outputs of each path according to the phase rotation signal based on the detected carrier frequency error The carrier frequency error signal is detected by the
10 is output. On the other hand, the multiplication circuit 11 multiplies the loop gain given by the gain output circuit 10
To enter. The output of the adder circuit 12 and the carrier frequency error signal a10 obtained from the open loop component are input to the initial value setting circuit 13. This initial value setting circuit 13 is operated at the time of loop switching, that is, at the time of initial operation.
It is set so that a signal is output for the first time when the operation is performed for = 32 symbol periods. Once the initial settings are made,
The delay circuit 14 delays the output a11 of the initial value setting circuit,
The addition circuit 12 and the delay circuit 14 constitute a complete integration type loop filter. The carrier frequency error signal a11, which is the output of the initial value setting circuit, is input to an integrating circuit 15 used as a variable frequency oscillating means, and outputs a frequency conversion reference signal a12 according to a change in the input signal. In this closed loop configuration, the output of the phase error detection circuit 8 operates so as to approach zero, and the carrier frequency error is corrected.

The delay circuit 17 delays the phase signal a5 and outputs a delayed phase signal a13. The subtraction circuit 18 performs frequency conversion by subtracting the frequency conversion reference signal a12 from the delayed phase signal a13, and outputs a carrier frequency error correction signal a14. The carrier recovery circuit 19 outputs the carrier phase signal a15
Is detected. Thereafter, in the subtraction circuit 20, the carrier phase signal a15 is subtracted from the carrier frequency error correction signal a14, and synchronous detection is performed. The sign determination circuit 21 determines the sign of the synchronous detection signal a16 and outputs the output data signal a1.
7 is output.

[0008]

In the conventional configuration, FIG.
As shown in (1), a one-symbol delay circuit is used for phase error detection. There is a trade-off relationship between the detection range of the carrier frequency error that can be pulled in and the error detection accuracy with respect to the number M of differential symbols for differential detection (M ≧ 1: an integer). Equation (6) shows the carrier frequency error detection range that can be pulled in.
Here, 2 ⁿ indicates the number of phases of the transmission signal, and T indicates the symbol period.

| Δf | = (M2 ⁿ T) ⁻¹ (6) For this reason, in the conventional configuration in which the phase error detection is performed based on the one-symbol differential detection output, the error detection accuracy is limited and high. Accurate frequency error detection cannot be performed. In particular, the characteristics are deteriorated when used for synchronous detection requiring high accuracy of error detection.

An object of the present invention is to solve this problem and to provide a digital demodulator capable of compensating a carrier frequency error with high accuracy even when the carrier frequency error is large.

[0011]

In the conventional configuration, since the phase error is detected based on the output of the one-symbol delay circuit, there is a problem that the carrier frequency error cannot be detected with high accuracy. According to the present invention, the number of differential detection differential symbols used for error detection is increased at the timing of switching between open loop and closed loop in a digital demodulator. FIG. 2A shows an error detection circuit using an M symbol delay circuit. In multi-symbol differential detection, the detection output S
Since the / N ratio is improved, highly accurate carrier frequency error detection is possible. According to the present invention, since the error detection circuit based on the multi-symbol delay circuit is operated after the error is detected by the open loop error detection unit, the error can be detected with high accuracy even when the carrier frequency error is large.

[0012]

FIG. 1 shows an embodiment of a digital demodulator according to the present invention. In this embodiment, synchronous detection is applied to the carrier recovery method, and portions corresponding to those in FIG. 3 are denoted by the same reference numerals. In this embodiment, the frequency-converted signal a6 subjected to frequency conversion from the subtraction circuit 16, which is the first carrier frequency error correction means, is input to a plurality of delay circuits. Here, a case where three delay circuits are used is shown as an example. First, the frequency conversion signal a6 is input to the subtraction circuit 7 and the one-symbol delay circuit 6
The signal is delayed by one symbol section to become a delayed signal a7. The subtraction circuit 7 performs an operation of the difference (a6-a7), and outputs a one-symbol differential detection signal a8. In this embodiment, the frequency conversion signal a6 is further input to the subtraction circuit 30 and also to the two-symbol delay circuit 31. The two-symbol delay circuit 31 outputs a delayed signal a for two symbol periods.
26 is output. In the subtraction circuit 30, the difference (a6-a2)
6) is performed, and the two-symbol differential detection signal a27
Is output. Similarly, the frequency conversion signal a6 is input to the subtraction circuit 32 and also to the three-symbol delay circuit 33. The three-symbol delay circuit 33 outputs a delay signal a28 for three symbol periods. The subtraction circuit 32 performs an operation of the difference (a6-a28), and outputs a three-symbol differential detection signal a29. In the switching circuit 34, the first switching is performed when the loop is switched, and the switching circuit 34
The output signal a30 of the switching circuit 34, which is the output of the first circuit, is changed from the one-symbol delayed detection signal a8 to the two-symbol delayed detection signal a27
Switch to Switching from the two-symbol differential detection signal a27 to the three-symbol differential detection signal a29 can be performed at an arbitrary time in consideration of various parameters such as a loop gain.

The configuration from the subtraction circuit 30 to the switching circuit 34 is a feature of the digital demodulator of the present invention, and corresponds to the M symbol differential detection means and the M variable means, respectively. The symbol determination circuit 35 outputs a phase angle determination signal based on the output signal a30 of the switching circuit 34 so as to be closest to the normal determination angle. The subtraction circuit 36 outputs a phase rotation signal a9 based on the phase angle determination signal a31 output from the symbol determination circuit 35. That is, the symbol determination circuit 35 and the subtraction circuit 36 constitute the phase error detection circuit 8 in FIG. The frequency error detection circuit 9 performs carrier frequency error detection by performing averaging processing or the like on the phase rotation signal a30, and outputs a carrier frequency error signal a10.

On the other hand, the gain obtained by the gain output circuit 10 is multiplied by the multiplication circuit 11 and the addition circuit 12
To enter. The initial value setting circuit 13 receives the output of the adder circuit and the carrier frequency error signal a10 obtained from the open loop component. The initial value setting circuit 13 is set so that a signal is output for the first time when the loop is switched, as in the case of FIG. The delay circuit 14 delays the output a11 of the initial value setting circuit. Adder circuit 12 and delay circuit 1
4 constitutes a complete integration type loop filter. The carrier frequency error signal a11, which is the output of the initial value setting circuit, is input to the integration circuit 15 used as a variable frequency oscillating means, and the frequency conversion reference signal a11 is changed according to the change of the input signal.
12 is output. In the initial operation, the output of the subtraction circuit 7 is supplied to the phase error detection circuit 8, and after a period of, for example, about N = 32 symbols, the output a10 of the frequency error detection circuit 9 is set in the initial value setting circuit 13 and the initial value is set. A loop is formed from the output a11 of the setting circuit 13 through the delay circuit 14 and the addition circuit 12, and after about N = 64 symbols,
The output of the subtraction circuit 30 is supplied to the phase error detection circuit 8, and after about N = 96 symbols, the switching circuit 3 supplies the output of the subtraction circuit 32 to the phase error detection circuit 8.
Switch 4.

By sequentially switching in this manner, the correction accuracy of the carrier frequency is gradually improved. Delay circuit 1
The processes after 7 are the same as those in FIG. FIG.
3 shows a frame error rate characteristic with respect to a frequency error by a simulation of the demodulator shown by. In the simulation, π / 4 shift DQPSK is used for the modulation method, and synchronous detection is used for the detection method. AWGN (Additive White Gaussia)
n Noise) environment, E _b / N ₀ = 8 dB, (signal energy per bit to thermal noise power spectral density ratio) The symbol rate is 192 kHz, and the result is obtained when 32 symbols are used for integration. A circle indicates an embodiment of the present invention, and M
= 1, 2, 3, 4 in order to reduce the carrier frequency error. Thus, in the demodulator using the carrier frequency error detection of the conventional configuration, since the one symbol delay circuit is used, the influence of the carrier frequency error cannot be sufficiently suppressed. On the other hand, in the demodulator shown in FIG. 1, the influence of the carrier frequency error is suppressed with high accuracy. This is because carrier frequency error detection is performed with high accuracy using a multi-symbol delay circuit in the closed loop unit.

[0016]

As described above, the digital demodulator according to the present invention can detect a carrier frequency error with high accuracy even when the carrier frequency error is large even though the circuit scale is not significantly increased as compared with the prior art. Is possible. The present invention can improve the error rate even when applied to synchronous detection.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the invention described in claim 1;

FIG. 2A is an explanatory diagram of a multi-symbol frequency error detection circuit which is a feature of the configuration of the present invention, and FIG.
FIG. 10 is a diagram showing simulation results of each bit error rate characteristic of the configuration of the embodiment described in FIG.

FIG. 3 is a block diagram showing a configuration of a conventional demodulator.

FIG. 4 is an explanatory diagram showing a phase rotation due to a carrier frequency error after 1-symbol differential detection.

Claims (1)

[Claims] The frequency of a received signal is corrected by first frequency error correction means, the frequency-corrected signal is delay-detected by an M symbol period (M is a positive integer) delay detection means, and the phase of the delay detection output is detected. The amount of rotation is detected by the phase error detection means, the carrier frequency error of the received signal is detected by the frequency error detection means from the detected phase rotation amount, and the detected carrier frequency error is smoothed by the loop filter means. Means is initialized by the output of the frequency error detecting means by the initial value setting means, and a signal having a frequency corresponding to the output of the loop filter means is supplied from the variable frequency oscillating means to the first frequency error correcting means; The signal is delayed by the delay means, and the delayed received signal is frequency-compensated by the second frequency error correction means by the output of the variable frequency oscillation means. Digital demodulator, and the digital demodulator its frequency corrected signal synchronous detection, wherein the variable to means provided the value of M (a positive real number) in the differential detection circuit.