JPH05110617A - Adaptive maximum likelihood series estimating device - Google Patents

Adaptive maximum likelihood series estimating device

Info

Publication number
JPH05110617A
JPH05110617A JP3264566A JP26456691A JPH05110617A JP H05110617 A JPH05110617 A JP H05110617A JP 3264566 A JP3264566 A JP 3264566A JP 26456691 A JP26456691 A JP 26456691A JP H05110617 A JPH05110617 A JP H05110617A
Authority
JP
Japan
Prior art keywords
phase
received signal
estimated
value
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3264566A
Other languages
Japanese (ja)
Other versions
JP2986261B2 (en
Inventor
Haruhiro Shiino
玄博 椎野
Norio Yamaguchi
法夫 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
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Filing date
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Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP3264566A priority Critical patent/JP2986261B2/en
Priority to US07/904,337 priority patent/US5303263A/en
Publication of JPH05110617A publication Critical patent/JPH05110617A/en
Application granted granted Critical
Publication of JP2986261B2 publication Critical patent/JP2986261B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To compensate a phase variation amount over a frequency offset of a wide range. CONSTITUTION:The device is provided with a phase rotating section 40 rotating a phase of a reception signal Yn to compensate a phase variation of the reception signal, a Viterbi algorithm processing section 60, a transmission line estimating section 70 estimating the impulse response of a transmission line and a phase estimating section 80A estimating the phase to give the phase estimating value to the phase rotating section 40. Then the phase estimating section 80A and the phase rotating section 40 compensate the phase variation amount. In this case, an integration means 90 is provided in a loop filter 82A to implement in the compensation of the phase fluctuation by a frequency offset and phase jitter by using a quadratic phase synchronization loop, thereby compensating a steady-state phase rotation by the frequency offset. Thus, the transmission symbol is estimated with less error ratio over the wide range of frequency offset.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、ディジタル通信の受信
機等において、伝送路の歪みを補償し正しい送信信号を
得る等化器等に用いられる適応最尤系列推定器、特に搬
送波の周波数オフセットによる位相変動を補償しながら
等化を行う位相補償型適応等化器等に適用される適応最
尤系列推定器に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adaptive maximum likelihood sequence estimator used in an equalizer or the like for compensating for distortion of a transmission path and obtaining a correct transmission signal in a receiver for digital communication, and more particularly, a carrier frequency offset. The present invention relates to an adaptive maximum likelihood sequence estimator applied to a phase compensation type adaptive equalizer or the like that performs equalization while compensating for the phase fluctuation due to.

【0002】[0002]

【従来の技術】従来、このような分野の技術としては、
例えば次のような文献に記載されるものがあった。 文献;アイイーイーイー トランスアクション オン
コミュニケーションズ(IEEE Transaction on Communic
ations)、COM−22[5](1974-5)(米)G.U
ngerboeck“アダプティブ マキシマム−ライ
クリフッド レシーバ フォア キャリイ−モデュレイ
ティッド データ−トランスミッション システムズ(A
daptive Maximum-LikelihoodReceiver for Carrier-Mod
ulated Data-Transmission Systems)”P.624−6
36 近年、ディジタル移動通信の開発が急速に行われている
が、陸上移動通信では遅延を伴なう多数の干渉波と移動
端末が高速に移動することによって周波数選択性フェー
ジングが発生し、受信信号波形が著しく歪むため、等化
器によってこの歪みを補償する必要がある。この等化器
に適用される最尤系列推定は、周波数選択性フェージン
グのように、伝送路の遅延特性に起因して歪んだ受信信
号波形から、正しい送信データを得るための最も有効な
等化方式の一つである。
2. Description of the Related Art Conventionally, as a technique in such a field,
For example, some documents were described in the following documents. Literature; IEE Trance Action On
Communications (IEEE Transaction on Communic
ations), COM-22 [5] (1974-5) (US) G.I. U
ngerboeck “Adaptive Maximum-Like Lifted Receiver Fore-Carry-Modulated Data-Transmission Systems (A
daptive Maximum-Likelihood Receiver for Carrier-Mod
Calculated Data-Transmission Systems) "P.624-6
36 In recent years, digital mobile communication has been rapidly developed, but in land mobile communication, a large number of interfering waves with delays and high-speed movement of mobile terminals cause frequency-selective fading, resulting in reception signals. Since the waveform is significantly distorted, it is necessary to compensate for this distortion by the equalizer. The maximum likelihood sequence estimation applied to this equalizer is the most effective equalization for obtaining correct transmission data from the received signal waveform distorted due to the delay characteristic of the transmission line, such as frequency selective fading. It is one of the methods.

【0003】図2は、従来のディジタル移動通信におけ
る送受信機の構成例を示すブロック図である。この送受
信機は、入力データbm に基づき信号sc (t)を送信
する送信機10を有し、該信号sc (t)が伝送路20
を介して受信機30に受信されるようになっている。送
信機10は、符号化器11、送信ローパスフィルタ(以
下、送信LPFという)12、及び変調器13より構成
されている。また、受信機30は、復調器31、受信ロ
ーパスフィルタ(以下、受信LPFという)32、適応
等化器33、及び復号器34より構成されている。
FIG. 2 is a block diagram showing a configuration example of a transmitter / receiver in a conventional digital mobile communication. The transceiver input data b m has a transmitter 10 which transmits signals s c (t) is based on, the signal s c (t) is the transmission line 20
The signal is received by the receiver 30 via. The transmitter 10 includes an encoder 11, a transmission low-pass filter (hereinafter, referred to as a transmission LPF) 12, and a modulator 13. Further, the receiver 30 includes a demodulator 31, a reception low-pass filter (hereinafter, referred to as reception LPF) 32, an adaptive equalizer 33, and a decoder 34.

【0004】送信機10では、入力データbm を符号化
器11で送信シンボルxn に変換し、送信LPF12に
より帯域制限して送信複素ベースバンド信号s(t)を
生成し、変調器13へ送る。変調器13では、信号s
(t)を周波数fc なる搬送波によって変調し、信号s
c (t)を伝送路20を介して受信機30へ送信する。
受信機30では、復調器31で送信搬送波周波数fc
等しい周波数によって同期検波を行い、伝送路20を通
った信号rc (t)を複素ベースバンド信号r(t)に
変換し、さらに受信LPF32を通して帯域制限された
受信複素ベースバンド信号y(t)を得る。この信号y
(t)をシンボル間隔Tでサンプリングする。
In the transmitter 10, the input data b m is converted into a transmission symbol x n by the encoder 11, and the transmission LPF 12 limits the band to generate a transmission complex baseband signal s (t), which is sent to the modulator 13. send. In the modulator 13, the signal s
Modulate (t) with a carrier of frequency f c to obtain the signal s
c (t) is transmitted to the receiver 30 via the transmission line 20.
In the receiver 30, the demodulator 31 performs synchronous detection at a frequency equal to the transmission carrier frequency f c , converts the signal r c (t) passing through the transmission line 20 into a complex baseband signal r (t), and further receives the signal. A band-limited reception complex baseband signal y (t) is obtained through the LPF 32. This signal y
(T) is sampled at symbol intervals T.

【0005】適応等化器33では、信号y(t)のサン
プル値yn から周波数選択性フェージングによる伝送路
20の特性を補償し、送信シンボルを推定する。ここ
で、送信搬送波周波数と受信機30の復調周波数の周波
数オフセットや位相ジッタにより、受信信号の位相が変
動するので、適応等化器33は、最尤系列推定により、
受信信号の位相変動を補償しながら送信シンボルの推定
を行う。最後に、復号器34で送信シンボルの推定値E
n (但し、Eは推定を表す)を復号し、送信されたデ
ータEbm を得る。
The adaptive equalizer 33 compensates the characteristics of the transmission line 20 due to frequency selective fading from the sample value y n of the signal y (t) and estimates the transmission symbol. Here, since the phase of the received signal changes due to the frequency offset and the phase jitter of the transmission carrier frequency and the demodulation frequency of the receiver 30, the adaptive equalizer 33 uses the maximum likelihood sequence estimation to
The transmission symbol is estimated while compensating for the phase fluctuation of the received signal. Finally, the decoder 34 estimates the transmitted symbol E
Decode X n (where E represents the estimate) to obtain the transmitted data Eb m .

【0006】最尤系列推定は、ある有限区間での受信信
号系列BYn ={y1 ,y2 ,…,yN }(但し、Bは
ベクトルを表す)が得られたときに、伝送路20のイン
パルス応答h(t)を既知としてBYN を実現する確率
(尤度)の最も大きい送信シンボル系列BXN
{x1 ,x2 ,…,xN }を推定するものであり、前記
文献に記載されているように、畳み込み符号の復号法と
して知られるビタビ・アルゴリズムを用いて効率的に計
算される。
Maximum-likelihood sequence estimation is performed when a received signal sequence BY n = {y 1 , y 2 , ..., Y N } (where B represents a vector) in a finite interval is obtained. With the 20 impulse responses h (t) known, the transmission symbol sequence BX N = which has the highest probability (likelihood) of achieving BY N.
{X 1 , x 2 , ..., X N } are estimated and are efficiently calculated using the Viterbi algorithm known as the decoding method of the convolutional code, as described in the above-mentioned document.

【0007】図3は、図2中の適応等化器33に適応さ
れる従来の適応最尤系列推定器の機能ブロック図であ
る。この適応最尤系列推定器は、集積回路等を用いた個
別回路、あるいはプロセッサを用いたプログラム制御等
により構成されるもので、位相回転部40、遅延手段5
0、ビタビ・アルゴリズム処理部60、伝送路推定部7
0、及び位相推定部80を備えている。なお、各機能ブ
ロック間を接続する実線は実数、一点鎖線は複素数、二
点鎖線は複素ベクトルをそれぞれ表す。
FIG. 3 is a functional block diagram of a conventional adaptive maximum likelihood sequence estimator adapted to the adaptive equalizer 33 in FIG. This adaptive maximum likelihood sequence estimator is configured by an individual circuit using an integrated circuit or the like, or program control using a processor, and the phase rotating unit 40 and the delay unit 5 are provided.
0, Viterbi algorithm processing unit 60, transmission path estimation unit 7
0 and the phase estimation part 80 are provided. A solid line connecting the functional blocks represents a real number, a one-dot chain line represents a complex number, and a two-dot chain line represents a complex vector.

【0008】位相回転部40は、位相推定値Eφn に基
づき、受信信号のサンプル値Yn を位相回転させて周波
数オフセットや位相ジッタによる位相変動を補償した受
信信号のサンプル値crn (但し、cは補償を表す)を
出力する機能を有し、演算手段41及び乗算手段42よ
り構成されている。遅延手段50は、ビタビ・アルゴリ
ズムの判定遅延を補償するためのもので、受信信号のサ
ンプル値crn を所定時間遅延し、その遅延した値cr
n-M を伝送路推定部70及び位相推定部80へ与える機
能を有している。ビタビ・アルゴリズム処理部60は、
サンプル値crn を入力し、伝送路推定部70からの伝
送路20のインパルス応答推定値Ehj に基づき、ビタ
ビ・アルゴリズムに従って送信シンボルの推定を行い、
推定送信シンボル系列EXn-M を出力する機能を有して
いる。
The phase rotation unit 40 phase-rotates the sample value Y n of the received signal based on the estimated phase value Eφ n to compensate the phase variation due to the frequency offset and the phase jitter cr n (however, c represents a compensation) and is composed of an arithmetic means 41 and a multiplication means 42. The delay means 50 is for compensating the decision delay of the Viterbi algorithm, delays the sample value cr n of the received signal for a predetermined time, and delays the delayed value cr n.
It has a function of giving nM to the transmission path estimation unit 70 and the phase estimation unit 80. The Viterbi algorithm processing unit 60
The sample value cr n is input, the transmission symbol is estimated according to the Viterbi algorithm based on the impulse response estimation value Eh j of the transmission line 20 from the transmission line estimation unit 70,
It has a function of outputting the estimated transmission symbol sequence EX nM .

【0009】伝送路推定部70では、実際の伝送路20
のインパルス応答が未知であるため、それを推定して伝
送路のインパルス応答推定値Ehj をビタビ・アルゴリ
ズム処理部60へ与える機能を有し、受信信号再生手段
71、インパルス応答適応更新手段72、及び減算手段
73より構成されている。
In the transmission path estimation unit 70, the actual transmission path 20
Has a function of estimating it and giving the impulse response estimated value Eh j of the transmission path to the Viterbi algorithm processing unit 60, the received signal reproducing means 71, the impulse response adaptive updating means 72, And subtraction means 73.

【0010】受信信号再生手段71では、推定送信シン
ボル系列{EXn ,EXn-1 ,…,EXn-L }と伝送路
20のインパルス応答推定値Ehj とから、次式(1)
のような受信信号の推定値Ern を発生する。 これを減算手段73で、次式(2)のように、位相変動
を補償した受信信号crn から差し引いて誤差信号en
を得る。 en =crn −Ern ・・・(2) インパルス応答適応更新手段72では、次式(3)で示
されるLMS(リースト・ミーン・スケヤーズ)アルゴ
リズムにより、伝送路20のインパルス応答推定値Eh
j (j=0,1,…,L)を更新する。 Ehj n+1 =Ehj n +β・en ・EX* n-j ・・・(3) 但し、j=0,1,…,L *;複素共役 β;ステップサイズと呼ばれる正の定数 位相推定部80は、周波数オフセットや位相ジッタによ
る位相変動量を次式(4)により推定し、その位相推定
値Eφn+1 を位相回転部40へ与え、該位相回転部40
でその位相変動量を補償させるように働く。 Eφn+1 =Eφn +α・Im[en ・cr* n ] ・・・(4) 但し、Im[ ];複素数の虚数部 α;正の定数 位相推定部80及び位相回転部40による位相変動量の
補償は、1次の位相同期ループと等価である。そのた
め、位相推定部80は、位相同期ループ(PLL)の位
相誤差検出回路81、ループフィルタ82、及び電圧制
御発振器(以下、VCOという)83より構成されてい
るといえる。
The received signal reproducing means 71 uses the following equation (1) from the estimated transmission symbol sequence {EX n , EX n-1 , ..., EX nL } and the impulse response estimation value Eh j of the transmission line 20.
An estimated value Er n of the received signal is generated. This is subtracted by the subtraction means 73 from the received signal cr n which has been compensated for the phase fluctuation by the following equation (2), and the error signal e n is obtained.
To get e n = cr n -Er the n · · · (2) the impulse response adaptive update means 72, by LMS (Least Mean Sukeyazu) algorithm represented by the following formula (3), the impulse response estimate Eh of the transmission line 20
Update j (j = 0, 1, ..., L). Eh j n + 1 = Eh j n + β · e n · EX * nj ··· (3) where, j = 0,1, ..., L *; positive constant phase estimator called step size; complex conjugate beta Reference numeral 80 estimates the amount of phase fluctuation due to frequency offset and phase jitter by the following equation (4), gives the phase estimation value Eφ n + 1 to the phase rotation unit 40, and the phase rotation unit 40
Works to compensate for the amount of phase fluctuation. Eφ n + 1 = Eφ n + α · Im [e n · cr * n] ··· (4) where, Im []; the imaginary part of the complex alpha; positive constant phase estimator 80 and phase by the phase rotation section 40 The fluctuation compensation is equivalent to a first-order phase locked loop. Therefore, it can be said that the phase estimation unit 80 includes a phase error detection circuit 81 of a phase locked loop (PLL), a loop filter 82, and a voltage controlled oscillator (hereinafter, referred to as VCO) 83.

【0011】位相誤差検出回路81は、遅延手段50の
出力crn-M からその複素共役cr * n-M を求める複素
共役算出手段81aと、複素共役cr * n-M と推定誤差
n- M とを乗算する乗算手段81bと、その乗算結果よ
り虚数部を抽出して位相誤差△φn を出力する虚数部抽
出手段81cとで、構成されている。フィルタ82は、
位相誤差△φn に対して乗数αを乗算する乗算手段82
aで構成されている。VCO83は、乗算手段82aの
出力に対して前の時刻の位相推定値Eφn-1 を加算する
加算手段83aと、該加算手段83aの出力を遅延する
レジスタ等の遅延手段83bとで、構成されている。
[0011] The phase error detecting circuit 81, the multiplication that multiplies a complex conjugate calculation unit 81a for obtaining the complex conjugate cr * nM from the output cr nM delay means 50, the complex conjugate cr * nM and the estimated error e nM Means 81b and imaginary part extracting means 81c for extracting the imaginary part from the multiplication result and outputting the phase error Δφ n . The filter 82 is
Multiplier 82 for multiplying the phase error Δφ n by a multiplier α
a. The VCO 83 is composed of an adding means 83a for adding the phase estimation value Eφ n-1 at the previous time to the output of the multiplying means 82a, and a delay means 83b such as a register for delaying the output of the adding means 83a. ing.

【0012】[0012]

【発明が解決しようとする課題】しかしながら、従来の
適応最尤系列推定器では、位相変動量の補償を1次の位
相同期ループを用いて行っているため、搬送波の周波数
オフセットや位相ジッタによる位相変動量のうち、周波
数オフセットによる定常的な位相回転を充分に補償でき
ない。そのため、周波数オフセット量が大きくなると、
誤り率が増大してしまうため、適用できる周波数オフセ
ット(送受信機の搬送波のずれ)の範囲が狭く、それに
よって復号精度が劣化するという問題があり、それを解
決することが困難であった。
However, in the conventional adaptive maximum likelihood sequence estimator, the phase fluctuation amount is compensated by using the first-order phase-locked loop. Of the fluctuation amount, steady phase rotation due to frequency offset cannot be sufficiently compensated. Therefore, if the frequency offset amount increases,
Since the error rate increases, there is a problem in that the range of applicable frequency offset (shift of carrier wave of transceiver) is narrow, and thereby the decoding accuracy deteriorates, which is difficult to solve.

【0013】本発明は、前記従来技術が持っていた課題
として、搬送波の周波数オフセットによる定常的な位相
回転を充分に補償できないという点について解決し、広
い範囲の周波数オフセットにわたって位相変動量を補償
できる適応最尤系列推定器を提供するものである。
The present invention solves the problem that the above-mentioned prior art has, that the stationary phase rotation due to the frequency offset of the carrier cannot be sufficiently compensated, and the phase fluctuation amount can be compensated over a wide range of frequency offsets. An adaptive maximum likelihood sequence estimator is provided.

【0014】[0014]

【課題を解決するための手段】第1の発明は、前記課題
を解決するために、位相推定値に基づき受信信号の位相
を回転させて該受信信号の位相変動を補償する位相回転
部と、前記補償後の受信信号を入力し、伝送路のインパ
ルス応答推定値に基づきビタビ・アルゴリズムに従って
送信シンボルの推定を行い、推定送信シンボル系列を出
力するビタビ・アルゴリズム処理部と、伝送路のインパ
ルス応答を推定する伝送路推定部と、位相推定部とを、
備えた適応最尤系列推定器において、積分手段と加算手
段とを設けている。
In order to solve the above-mentioned problems, a first aspect of the present invention includes a phase rotating section for rotating the phase of a received signal based on a phase estimation value to compensate for a phase fluctuation of the received signal. The received signal after the compensation is input, the transmission symbol is estimated according to the Viterbi algorithm based on the impulse response estimation value of the transmission line, and the Viterbi algorithm processing unit that outputs the estimated transmission symbol sequence and the impulse response of the transmission line are output. A transmission path estimation unit for estimating and a phase estimation unit,
The adaptive maximum likelihood sequence estimator provided is provided with an integrating means and an adding means.

【0015】ここで、伝送路推定部は、前記推定送信シ
ンボル系列と前記伝送路のインパルス応答推定値とから
受信信号の推定値を算出する受信信号再生手段を有し、
前記補償後の受信信号から該受信信号の推定値を差し引
いて推定誤差を算出し、該推定誤差及び前記推定送信シ
ンボル系列に基づき、適応アルゴリズムに従い伝送路の
インパルス応答を更新して新しい前記伝送路のインパル
ス応答推定値を前記ビタビ・アルゴリズム処理部及び受
信信号再生手段に与える機能を有している。位相推定部
は、前記補償後の受信信号及び前記推定誤差を用いて位
相誤差を検出し、該位相誤差を位相修正値として位相推
定値に加えて新しい前記位相推定値を前記位相回転部に
与えるものである。
Here, the transmission path estimation unit has a reception signal reproduction means for calculating an estimation value of a reception signal from the estimated transmission symbol sequence and an impulse response estimation value of the transmission path,
An estimated error is calculated by subtracting the estimated value of the received signal from the compensated received signal, and the impulse response of the transmission line is updated according to an adaptive algorithm based on the estimated error and the estimated transmission symbol sequence, and the new transmission line is updated. It has a function of giving the impulse response estimated value of to the Viterbi algorithm processing section and the received signal reproducing means. The phase estimation unit detects a phase error by using the received signal after the compensation and the estimation error, adds the phase error as a phase correction value to the phase estimation value, and gives a new phase estimation value to the phase rotation unit. It is a thing.

【0016】積分手段は前記位相誤差を積分する機能を
有し、さらに加算手段は該積分手段の出力を前記位相誤
差に加えて前記位相修正値を生成する機能を有してい
る。第2の発明は、第1の発明において、前記位相誤差
を、前記補償後の受信信号の短時間パワーで規格化する
規格化手段を設けている。
The integrating means has a function of integrating the phase error, and the adding means has a function of adding the output of the integrating means to the phase error to generate the phase correction value. In a second aspect based on the first aspect, a normalizing means is provided for normalizing the phase error with the short-time power of the compensated received signal.

【0017】[0017]

【作用】第1の発明によれば、以上のように適応最尤系
列推定器を構成したので、位相推定部に設けられた積分
手段及び加算手段は、2次の位相同期ループを用いて周
波数オフセットによる位相変動の補償を行うように働
く。
According to the first aspect of the present invention, since the adaptive maximum likelihood sequence estimator is configured as described above, the integrating means and the adding means provided in the phase estimating section use a quadratic phase-locked loop to generate the frequency. It works to compensate for phase fluctuations due to offset.

【0018】第2の発明によれば、規格化手段は、位相
同期ループで抽出された位相誤差を受信信号の短時間平
均パワーで規格化するように働く。従って、前記課題を
解決できるのである。
According to the second aspect of the invention, the normalizing means functions to normalize the phase error extracted by the phase locked loop with the short-time average power of the received signal. Therefore, the above problem can be solved.

【0019】[0019]

【実施例】第1の実施例 図1は、本発明の第1の実施例を示す適応最尤系列推定
器の機能ブロック図であり、従来の図3中の要素と共通
の要素には共通の符号が付されている。この適応最尤系
列推定器は、従来と同様、図2に示すディジタル移動通
信における送受信機中の適応等化器33に適応されるも
ので、集積回路等を用いた個別回路、あるいはプロセッ
サによるプログラム制御等により構成されている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a functional block diagram of an adaptive maximum likelihood sequence estimator showing a first embodiment of the present invention, in which elements common to those in FIG. Is attached. This adaptive maximum likelihood sequence estimator is adapted to the adaptive equalizer 33 in the transmitter / receiver in the digital mobile communication shown in FIG. 2 as in the conventional case. The adaptive maximum likelihood sequence estimator is an individual circuit using an integrated circuit or a program by a processor. It is composed of controls and the like.

【0020】この適応最尤系列推定器では、従来の図3
中の位相推定部80に代えて、構成の異なる位相推定部
80Aが設けられている。位相推定部80Aは、従来と
同様の位相誤差検出回路81及びVCO83と、従来と
異なるループフィルタ82Aとで、構成されている。
In this adaptive maximum likelihood sequence estimator, the conventional maximum likelihood sequence estimator shown in FIG.
Instead of the phase estimation unit 80 in the inside, a phase estimation unit 80A having a different configuration is provided. The phase estimation unit 80A is composed of a phase error detection circuit 81 and a VCO 83 similar to the conventional one, and a loop filter 82A different from the conventional one.

【0021】位相誤差検出回路81は、従来と同様、遅
延手段50の出力crn-M から複素共役cr * n-M を求
める複素共役算出手段81aと、複素共役cr * n-M
減算手段73からの推定誤差en-M とを乗算する乗算手
段81bと、該乗算手段81bの出力から虚数部を抽出
して位相誤差△φn を出力する虚数部抽出手段81cと
で、構成されている。
The phase error detection circuit 81, conventional manner, the estimated error e from the complex conjugate calculation unit 81a for obtaining the complex conjugate cr * nM from the output cr nM delay means 50, the complex conjugate cr * nM subtraction means 73 It is composed of a multiplication means 81b for multiplying nM and an imaginary part extraction means 81c for extracting an imaginary part from the output of the multiplication means 81b and outputting a phase error Δφ n .

【0022】ループフィルタ82Aは、従来のループフ
ィルタ82を構成する乗算手段82aに、積分手段90
及び加算手段94を付加した構成である。積分手段90
は、虚数部抽出手段81cから出力される位相誤差△φ
n を積分する機能を有し、位相誤差△φn に乗数α1を
乗算する乗算手段91と、加算手段92と、該加算手段
92の出力を遅延するレジスタ等の遅延手段93とで構
成されている。加算手段94は、位相誤差△φn と積分
手段90の出力とを加算して乗算手段82aへ出力する
機能を有している。乗算手段82aは、加算手段94の
出力に乗数α2を乗算して位相修正量△Eφn+1 をVC
O83へ出力する機能を有している。
The loop filter 82A includes a multiplication means 82a which constitutes the conventional loop filter 82 and an integration means 90.
And addition means 94 are added. Integrating means 90
Is the phase error Δφ output from the imaginary part extraction means 81c.
It has a function of integrating n, and comprises a multiplication means 91 for multiplying the phase error Δφ n by a multiplier α1, an addition means 92, and a delay means 93 such as a register for delaying the output of the addition means 92. There is. The adding means 94 has a function of adding the phase error Δφ n and the output of the integrating means 90 and outputting the result to the multiplying means 82a. The multiplication means 82a multiplies the output of the addition means 94 by a multiplier α2 to obtain the phase correction amount ΔEφ n + 1 as VC.
It has a function of outputting to O83.

【0023】VCO83は、従来と同様、位相修正量△
Eφn+1 を入力して位相推定値Eφn を位相回転部40
へ与える機能を有し、加算手段83aと、レジスタ等の
遅延手段83bとで構成されている。
The VCO 83 has a phase correction amount Δ as in the conventional case.
n + 1 is input and the phase estimation value Eφ n is input to the phase rotation unit 40.
It has a function of giving to, and is composed of an adding means 83a and a delay means 83b such as a register.

【0024】次に、動作を説明する。例えば、受信信号
のサンプル値yn を yn =rn exp[jφn ] ・・・(5) のように表す。ここで、φn は周波数オフセットや位相
ジッタによる位相変動量、rn はこれらの位相変動がな
い場合の受信信号のサンプル値で、インパルス応答ベク
トルBhn 、及び送信シンボルベクトルBXn を用いて
次式(6)のように表される。 rn =Bhn T ・Bxn ・・・(6) 但し、Bhn ={h0 n ,h1 n ,…,hL n T Bxn ={xn ,xn-1 ,…,xn-LT T;ベクトルの転置 図2の受信機30において、シンボル間隔Tでサンプリ
ングされた受信信号のサンプル値Yn が位相回転部40
に入力されると、該位相回転部40では、位相推定部8
0Aで推定された位相推定値Eφn から演算手段41で
位相回転量exp[−jEφn ]を求め、これを乗算手
段42で受信信号のサンプル値Yn に乗じて位相を補償
した次式(7)のような受信信号のサンプル値cr
n を、遅延手段50及びビタビ・アルゴリズム処理部6
0へ出力する。 crn =rn ・exp[j(φn −Eφn )] ・・・(7) 遅延手段50は受信信号のサンプル値crn を遅延し、
その遅延した値crn- M を位相誤差検出回路81内の複
素共役算出手段81a、及び伝送路推定部70内の減算
手段73へ与える。
Next, the operation will be described. For example, the sample value y n of the received signal is expressed as y n = r n exp [jφ n ] ... (5). Here, phi n is the phase deviation due to frequency offset and phase jitter, using the sample values of the received signal when r n is not have these phase fluctuations, the impulse response vector Bh n, and a transmission symbol vector BX n following It is expressed as in Expression (6). r n = Bh n T · Bx n (6) Here, Bh n = {h 0 n , h 1 n , ..., h L n } T Bx n = {x n , x n-1 , ..., x nL } T T; Transposition of vector In the receiver 30 of FIG. 2, the sample value Y n of the received signal sampled at the symbol interval T is the phase rotation unit 40.
Is input to the phase rotation unit 40, the phase estimation unit 8
The phase rotation amount exp [−jEφ n ] is calculated by the calculating means 41 from the phase estimated value Eφ n estimated at 0 A, and is multiplied by the sample value Y n of the received signal by the multiplying means 42 to compensate the phase ( Sample value cr of received signal like 7)
n is the delay means 50 and the Viterbi algorithm processing unit 6
Output to 0. cr n = r n · exp [ j (φ n -Eφ n)] ··· (7) the delay means 50 delays the sample value cr n of the received signal,
The delayed value cr n- M is given to the complex conjugate calculating means 81a in the phase error detecting circuit 81 and the subtracting means 73 in the transmission path estimating section 70.

【0025】ビタビ・アルゴリズム処理部60では、受
信信号のサンプル値crn を入力し、インパルス応答適
応更新手段72で推定された伝送路20のインパルス応
答推定値Ehj に基づき、送信シンボル系列を推定し、
その推定送信シンボル系列{Exn ,Exn-1 ,…,E
n-L }を出力する。
The Viterbi algorithm processing unit 60 inputs the sample value cr n of the received signal and estimates the transmission symbol sequence based on the impulse response estimation value Eh j of the transmission path 20 estimated by the impulse response adaptive updating means 72. Then
The estimated transmission symbol sequence {Ex n , Ex n-1 , ..., E
x nL } is output.

【0026】伝送路推定部70内の受信信号再生手段7
1は、推定送信シンボル系列{Exn ,Exn-1 ,…,
Exn-L }と伝送路20のインパルス応答推定値Ehj
とに基づき、受信信号の推定値Ern-M を求め、減算手
段73へ与える。減算手段73は、遅延手段50からの
受信信号のサンプル値crn-M から推定値Ern-M を減
算し、推定誤差en-M を求め、それを位相誤差検出回路
81内の乗算手段81bとインパルス応答適応更新手段
72とに与える。
Received signal reproducing means 7 in the transmission path estimating section 70
1 is the estimated transmission symbol sequence {Ex n , Ex n-1 , ...,
Ex nL } and impulse response estimation value Eh j of the transmission line 20
Based on and, the estimated value Er nM of the received signal is obtained and given to the subtraction means 73. Subtracting means 73 subtracts the estimated value Er nM from the sample value cr nM of the received signal from the delay means 50, the estimation error determined for e nM, it multiplication means 81b and the impulse response adaptive update in the phase error detection circuit 81 And means 72.

【0027】位相誤差検出回路81では、遅延手段50
で遅延された受信信号のサンプル値crn-M から複素共
役算出手段81aで複素共役cr * n-M を算出し、その
複素共役cr * n-M と伝送路の推定誤差en-M とを乗算
手段81bで乗算する。この乗算結果から、虚数部抽出
手段81cで虚数部を抽出し、次式(8)のような位相
誤差△φn を求め、ループフィルタ82Aへ与える。 △φn =φn −Eφn ・・・(8) ループフィルタ82A内の積分手段90では、位相誤差
△φn と乗数α1とを乗算手段91で乗算し、その乗算
結果と遅延手段93の出力とを加算手段92で加算し、
該加算結果を遅延手段93で遅延させて該加算手段92
にフィードバック入力する。これにより、積分手段90
では、位相誤差△φn を積分してその平均値を求め、そ
の積分結果と位相誤差△φn とを加算手段94で加算さ
せる。加算手段94の出力は、乗算手段82aで乗数α
2と乗算され、位相修正量△Eφn+1 が求められてVC
O83へ送られる。
In the phase error detection circuit 81, the delay means 50
In calculating the complex conjugate cr * nM complex conjugate calculation unit 81a from the sample value cr nM of the delayed received signals, multiplying the estimation error e nM of the transmission line and its complex conjugate cr * nM multiplication unit 81b. From this multiplication result, the imaginary part extracting means 81c extracts the imaginary part, obtains the phase error Δφ n as in the following equation (8), and supplies it to the loop filter 82A. In △ φ n = φ n -Eφ n ··· (8) integrating means 90 in the loop filter 82A, multiplies the phase error △ phi n and multipliers α1 multiplication unit 91, the multiplication result of the delay means 93 The output is added by the addition means 92,
The addition result is delayed by the delay means 93 by the delay means 93.
Give feedback to. Thereby, the integration means 90
Then, the phase error Δφ n is integrated to obtain its average value, and the integration result and the phase error Δφ n are added by the adding means 94. The output of the adding means 94 is the multiplier α in the multiplying means 82a.
It is multiplied by 2 to obtain the phase correction amount ΔEφ n + 1 and VC
It is sent to O83.

【0028】VCO83では、加算手段83aで、位相
推定値Eφn に位相修正量△Eφn+ 1 を加算し、遅延手
段83bで遅延し、新たな位相推定値Eφn+1 として位
相回転部40へ出力する。
In the VCO 83, the adding means 83a adds the phase correction amount ΔEφ n + 1 to the estimated phase value Eφ n , and the delaying means 83b delays it to the phase rotating section 40 as a new estimated phase value Eφ n + 1 . Output.

【0029】以上のように、この第1の実施例では、次
のような利点を有している。位相推定部80A及び位相
回転部40による位相変動量の補償は、積分手段90で
計算される位相誤差の平均成分を、瞬時的な位相誤差△
φn に加算することによって位相推定値に一定の増分を
加えている。そのため、周波数オフセットによる定常的
な位相回転を補償することができ、2次の位相同期ルー
プと等価である。このように、2次の位相同期ループを
用いて周波数オフセットや位相ジッタによる位相変動の
補償を行うようにしたので、周波数オフセットによる定
常的な位相回転を補償することができる。従って、広い
範囲の周波数オフセットにわたって少ない誤り率で、送
信シンボルの推定を行うことができる。
As described above, the first embodiment has the following advantages. In the compensation of the amount of phase fluctuation by the phase estimation unit 80A and the phase rotation unit 40, the average component of the phase error calculated by the integration means 90 is converted into the instantaneous phase error Δ.
A fixed increment is added to the phase estimate by adding to φ n . Therefore, the stationary phase rotation due to the frequency offset can be compensated, and it is equivalent to the secondary phase locked loop. In this way, since the phase variation due to the frequency offset and the phase jitter is compensated by using the secondary phase locked loop, it is possible to compensate the steady phase rotation due to the frequency offset. Therefore, the transmission symbol can be estimated with a small error rate over a wide range of frequency offsets.

【0030】この効果の一例として、2波モデルの周波
数選択性フェージング伝送路の場合の周波数オフセット
対ビット誤り率のシミュレーション結果を図4に示す。
図4中の波形201は本実施例の特性、波形202は従
来の特性、波形203は位相変動を補償しない場合の特
性を示す。
As an example of this effect, FIG. 4 shows a simulation result of frequency offset versus bit error rate in the case of a frequency selective fading transmission line of a two-wave model.
Waveform 201 in FIG. 4 shows the characteristic of this embodiment, waveform 202 shows the conventional characteristic, and waveform 203 shows the characteristic when phase fluctuation is not compensated.

【0031】図4のシミュレーション条件は、シンボル
間隔T41μsec、最大ドップラー周波数80Hz、
遅延波の遅延は1.0T、Eb/N0(1ビット当りの
信号電力対雑音電力密度比)20dBである。図4より
明らかなように、10-2以下のビット誤り率が得られる
周波数オフセットの範囲が、従来の適応最尤系列推定器
では約±150Hzであったのが、本実施例では±1k
Hzの範囲の周波数オフセットまで誤り率は周波数オフ
セットがない場合と比べて全く劣化しない。従って、本
実施例による効果は非常に大きい。
The simulation conditions in FIG. 4 are as follows: symbol interval T41 μsec, maximum Doppler frequency 80 Hz,
The delay of the delay wave is 1.0T and Eb / N0 (signal power to noise power density ratio per bit) is 20 dB. As is clear from FIG. 4, the range of the frequency offset at which the bit error rate of 10 −2 or less is obtained is about ± 150 Hz in the conventional adaptive maximum likelihood sequence estimator, but is ± 1 k in the present embodiment.
The error rate does not deteriorate at all up to the frequency offset in the range of Hz as compared with the case without the frequency offset. Therefore, the effect of this embodiment is very large.

【0032】第2の実施例 図5は、本発明の第2の実施例を示す適応最尤系列推定
器の機能ブロック図であり、図1中の要素と共通の要素
には共通の符号が付されている。この適応最尤系列推定
器では、図1の位相推定部80Aに代えて、構成の異な
る位相推定部80A−1を設けている。位相推定部80
A−1は、図1と異なる位相誤差検出回路81Aと、図
1と同様のループフィルタ82A及びVCO83とで、
構成されている。位相誤差検出回路81Aには、図1の
位相誤差検出回路81を構成する複素共役算出手段81
a、乗算手段81b及び虚数部抽出手段81cの他に、
受信信号の短時間平均パワーによる規格化手段100が
付加されている。
Second Embodiment FIG. 5 is a functional block diagram of an adaptive maximum likelihood sequence estimator showing a second embodiment of the present invention. Elements common to those in FIG. It is attached. In this adaptive maximum likelihood sequence estimator, a phase estimator 80A-1 having a different configuration is provided instead of the phase estimator 80A of FIG. Phase estimation unit 80
A-1 is a phase error detection circuit 81A different from FIG. 1, and a loop filter 82A and a VCO 83 similar to FIG.
It is configured. The phase error detection circuit 81A includes a complex conjugate calculation means 81 which constitutes the phase error detection circuit 81 of FIG.
a, multiplication means 81b, and imaginary part extraction means 81c,
A normalizing means 100 based on the short-time average power of the received signal is added.

【0033】規格化手段100は、複素共役cr * n-M
に遅延手段50の出力crn-M を乗算する乗算手段10
1と、該乗算結果を平均化する平均化手段102と、虚
数部抽出手段81cの出力に対して平均化手段102の
出力で除算する除算手段103とで、構成されている。
The normalizing means 100 calculates the complex conjugate cr * nM.
Means 10 for multiplying the output cr nM of the delay means 50 by
1, an averaging means 102 for averaging the multiplication results, and a dividing means 103 for dividing the output of the imaginary part extracting means 81c by the output of the averaging means 102.

【0034】図1の位相誤差検出回路81の出力につい
て考えると、(2)式より、 Im[en ・crn * ]=Im[(crn −Ern )crn * ] =Im[Ern * ・crn ] ・・・(9) と表される。ここで、伝送路推定部70及び位相推定部
80Aの推定動作が充分行われているとすると、(9)
式は、結局、 Im[en ・crn * ]=A・H2 ・sin(△φn ) ≒A・H2 ・△φn ・・・(10) となる。但し、Aは送信シンボルベクトルの2乗平均値
であり、変調方式によって決まる値である。また、Hは
伝送路20のインパルス応答ベクトルの絶対値であり、
例えば陸上移動通信における周波数選択性フェージング
伝送路では、時間と共に変動する量である。従って、
(10)式による位相誤差抽出では、(4)式の乗数αを
固定とした場合に、推定位相の修正量として位相誤差と
は無関係な周波数選択性フェーシング伝送路の変動が含
まれてしまう。一方、位相を補償した受信信号のパワー
は(7),(6)式より、 |crn 2 =crn ・crn * =rn ・rn * =A・H2 ・・・(11) となるから、(10)式を(11)式で割れば位相誤差△φ
n だけを抽出できる。しかし、周波数選択性フェージン
グの場合、受信信号のレベルは瞬間的に非常に小さくな
ることがあり、この時、(11)式による除算は計算でき
なくなるので、その代わりに、図5の規格化手段100
で求めた数サンプル程度の短時間平均パワーA[crn
・crn *](但し、A[・]は平均を表わす)を用
い、次式(12)によって位相誤差だけを抽出することが
できる。
[0034] Considering the output of the phase error detection circuit 81 in FIG. 1, (2) from the equation, Im [* e n · cr n] = Im [(cr n -Er n) cr n *] = Im [Er n * · cr n ] ... (9) Here, assuming that the estimation operations of the transmission path estimation unit 70 and the phase estimation unit 80A are sufficiently performed, (9)
After all, the formula is Im [e n · cr n * ] = A · H 2 · sin (Δφ n ) ≈A · H 2 · Δφ n (10) However, A is the root mean square value of the transmission symbol vector and is a value determined by the modulation method. H is the absolute value of the impulse response vector of the transmission line 20,
For example, in a frequency selective fading transmission line in land mobile communication, it is an amount that changes with time. Therefore,
In the phase error extraction by the equation (10), when the multiplier α in the equation (4) is fixed, the variation of the frequency selective facing transmission line unrelated to the phase error is included as the correction amount of the estimated phase. On the other hand, the power of the received signal to compensate for phase (7) and (6), | cr n | 2 = cr n · cr n * = r n · r n * = A · H 2 ··· (11 ), The phase error Δφ can be obtained by dividing equation (10) by equation (11).
Only n can be extracted. However, in the case of frequency-selective fading, the level of the received signal may become very small instantaneously, and at this time, the division by equation (11) cannot be calculated. Instead, the normalization means of FIG. 100
Short-time average power A [cr n
· Cr n *] (where, A [·] represents an average) with, by the following equation (12) can be extracted by the phase error.

【0035】[0035]

【数1】 [Equation 1]

【0036】従って、第1の実施例とほぼ同様の効果が
得られる。
Therefore, an effect similar to that of the first embodiment can be obtained.

【0037】なお、本発明は上記実施例に限定されず、
種々の変形が可能である。その変形例としては、例えば
次のようなものがある。 (a)図1及び図5において、ループフィルタ82Aの
乗数α1,α2を乗算する位置は、図示の位置に限定さ
れるものではなく、これと同じ効果を与えるならば、他
の位置で乗数α1,α2を乗算しても良い。例えば、虚
数部抽出手段81cの出力側に乗算手段82aを設け、
該虚数部抽出手段81cの出力に対して乗数α2を乗算
する等である。
The present invention is not limited to the above embodiment,
Various modifications are possible. Examples of such modifications include the following. (A) In FIGS. 1 and 5, the position at which the multipliers α1 and α2 of the loop filter 82A are multiplied is not limited to the position shown in the figure. , Α2 may be multiplied. For example, the multiplication means 82a is provided on the output side of the imaginary part extraction means 81c,
For example, the output of the imaginary part extraction means 81c is multiplied by a multiplier α2.

【0038】(b)適応最尤系列推定器の構成として、
図1または図5のビタビ・アルゴリズム処理部60の入
力側に信号対雑音比(S/N比)を低減するための整合
フィルタや白色化整合フィルタを設け、該フィルタの出
力をビタビ・アルゴリズム処理部60に入力する構成例
がある。これらの構成の適応最尤系列推定器は、ビタビ
・アルゴリズム処理部60内の計算が異なるだけであ
り、これらの構成の適応最尤系列推定器にも、上記実施
例を全く同様に適用できる。
(B) As a configuration of the adaptive maximum likelihood sequence estimator,
A matched filter or a whitened matched filter for reducing the signal-to-noise ratio (S / N ratio) is provided on the input side of the Viterbi algorithm processing unit 60 of FIG. 1 or 5, and the output of the filter is subjected to the Viterbi algorithm processing. There is a configuration example of inputting to the unit 60. The adaptive maximum likelihood sequence estimator having these configurations is different only in the calculation in the Viterbi algorithm processing unit 60, and the above embodiment can be applied to the adaptive maximum likelihood sequence estimator having these configurations in exactly the same manner.

【0039】(c)上記実施例の適応最尤系列推定器
は、ディジタル移動通信の適応等化器33に適用される
場合について説明したが、固定通信網におけるデータ通
信の適応等化器等としても、当然、適用可能である。
(C) The adaptive maximum likelihood sequence estimator of the above embodiment has been described as applied to the adaptive equalizer 33 of digital mobile communication, but as an adaptive equalizer of data communication in a fixed communication network, etc. Is, of course, also applicable.

【0040】[0040]

【発明の効果】以上詳細に説明したように、第1の発明
によれば、積分手段及び加算手段を設け、2次の位相同
期ループを用いて周波数オフセットや位相ジッタによる
位相変動の補償を行うようにしたので、周波数オフセッ
トによる定常的な位相回転を補償することができる。従
って、広い範囲の周波数オフセットにわたって少ない誤
り率で、送信シンボルの推定を精度良く行うことができ
る。
As described above in detail, according to the first aspect of the present invention, the integrating means and the adding means are provided to compensate for the phase fluctuation due to the frequency offset and the phase jitter by using the secondary phase locked loop. Since this is done, it is possible to compensate for the stationary phase rotation due to the frequency offset. Therefore, it is possible to accurately estimate a transmission symbol with a small error rate over a wide range of frequency offsets.

【0041】第2の発明によれば、規格化手段を設け、
位相同期ループで抽出された位相誤差を受信信号の短時
間平均パワーで規格化するようにしたので、周波数選択
性フェージング伝送路等において第1の発明とほぼ同様
に、送信シンボルの推定を精度良く行うことができる。
According to the second invention, the standardizing means is provided,
Since the phase error extracted by the phase-locked loop is standardized by the short-time average power of the received signal, the transmission symbol can be accurately estimated in the frequency-selective fading transmission line or the like, almost like the first invention. It can be carried out.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を示す適応最尤系列推定
器の機能ブロック図である。
FIG. 1 is a functional block diagram of an adaptive maximum likelihood sequence estimator showing a first embodiment of the present invention.

【図2】一般的なディジタル移動通信における送受信機
の機能ブロック図である。
FIG. 2 is a functional block diagram of a transceiver in general digital mobile communication.

【図3】従来の適応最尤系列推定器の機能ブロック図で
ある。
FIG. 3 is a functional block diagram of a conventional adaptive maximum likelihood sequence estimator.

【図4】従来と本実施例の周波数オフセット対ビット誤
り率のシミュレーション結果を示す図である。
FIG. 4 is a diagram showing simulation results of frequency offset vs. bit error rate of the conventional example and the present example.

【図5】本発明の第2の実施例を示す適応最尤系列推定
器の機能ブロック図である。
FIG. 5 is a functional block diagram of an adaptive maximum likelihood sequence estimator showing a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

40 位相回転部 50 遅延手段 60 ビタビ・アルゴ
リズム処理部 70 伝送路推定部 71 受信信号再生手
段 72 インパルス応答
適応更新手段 73 減算手段 80A,80A−1 位相推定部 81,81A 位相誤差検出回
路 82A ループフィルタ 83 VCO 90 積分手段 100 規格化手段
40 phase rotation part 50 delay means 60 Viterbi algorithm processing part 70 transmission path estimation part 71 received signal reproduction means 72 impulse response adaptive updating means 73 subtraction means 80A, 80A-1 phase estimation part 81, 81A phase error detection circuit 82A loop filter 83 VCO 90 integrating means 100 normalizing means

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 位相推定値に基づき受信信号の位相を回
転させて該受信信号の位相変動を補償する位相回転部
と、 前記補償後の受信信号を入力し、伝送路のインパルス応
答推定値に基づきビタビ・アルゴリズムに従って送信シ
ンボルの推定を行い、推定送信シンボル系列を出力する
ビタビ・アルゴリズム処理部と、 前記推定送信シンボル系列と前記伝送路のインパルス応
答推定値とから受信信号の推定値を算出する受信信号再
生手段を有し、前記補償後の受信信号から該受信信号の
推定値を差し引いて推定誤差を算出し、該推定誤差及び
前記推定送信シンボル系列に基づき、適応アルゴリズム
に従い伝送路のインパルス応答を更新して新しい前記伝
送路のインパルス応答推定値を前記ビタビ・アルゴリズ
ム処理部及び受信信号再生手段に与える伝送路推定部
と、 前記補償後の受信信号及び前記推定誤差を用いて位相誤
差を検出し、該位相誤差を位相修正値として位相推定値
に加えて新しい前記位相推定値を前記位相回転部に与え
る位相推定部とを、備えた適応最尤系列推定器におい
て、 前記位相誤差を積分する積分手段と、前記積分手段の出
力を前記位相誤差に加えて前記位相修正値を生成する加
算手段とを、設けたことを特徴とする適応最尤系列推定
器。
1. A phase rotation unit for rotating a phase of a received signal based on the phase estimated value to compensate for a phase fluctuation of the received signal, and a received signal after the compensation, which is input to an impulse response estimated value of a transmission line. Based on the Viterbi algorithm, the transmission symbol is estimated, and the estimated value of the received signal is calculated from the Viterbi algorithm processing unit that outputs the estimated transmission symbol sequence and the estimated transmission symbol sequence and the impulse response estimation value of the transmission path. An impulse response of the transmission line according to an adaptive algorithm based on the estimated error and the estimated transmission symbol sequence, the estimated signal error is calculated by subtracting the estimated value of the received signal from the compensated received signal. To provide a new impulse response estimation value of the transmission line to the Viterbi algorithm processing unit and the received signal reproducing means. A transmission path estimation unit, a phase error is detected using the received signal after the compensation and the estimation error, the phase error is added to the phase estimation value as a phase correction value, and a new phase estimation value is added to the phase rotation unit. An adaptive maximum likelihood sequence estimator provided with a phase estimator for giving an integrating means for integrating the phase error, and an adding means for adding the output of the integrating means to the phase error to generate the phase correction value. , An adaptive maximum likelihood sequence estimator provided.
【請求項2】 請求項1記載の適応最尤系列推定器にお
いて、 前記位相誤差を、前記補償後の受信信号の短時間パワー
で規格化する規格化手段を設けたことを特徴とする適応
最尤系列推定器。
2. The adaptive maximum likelihood sequence estimator according to claim 1, further comprising a normalizing means for normalizing the phase error by a short time power of the received signal after the compensation. Likelihood sequence estimator.
JP3264566A 1991-06-25 1991-10-14 Adaptive maximum likelihood sequence estimator Expired - Fee Related JP2986261B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP3264566A JP2986261B2 (en) 1991-10-14 1991-10-14 Adaptive maximum likelihood sequence estimator
US07/904,337 US5303263A (en) 1991-06-25 1992-06-24 Transmission channel characteristic equalizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3264566A JP2986261B2 (en) 1991-10-14 1991-10-14 Adaptive maximum likelihood sequence estimator

Publications (2)

Publication Number Publication Date
JPH05110617A true JPH05110617A (en) 1993-04-30
JP2986261B2 JP2986261B2 (en) 1999-12-06

Family

ID=17405070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3264566A Expired - Fee Related JP2986261B2 (en) 1991-06-25 1991-10-14 Adaptive maximum likelihood sequence estimator

Country Status (1)

Country Link
JP (1) JP2986261B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995012926A1 (en) * 1993-11-05 1995-05-11 Ntt Mobile Communications Network Inc. Replica producing adaptive demodulating method and demodulator using the same
WO1995017052A1 (en) * 1993-12-15 1995-06-22 Ntt Mobile Communications Network Inc. Adaptive equalizer
US6473470B1 (en) 1998-05-11 2002-10-29 Nec Corp. Phase-locked loop circuits for communication system
US6504868B1 (en) 1998-03-13 2003-01-07 Nec Corporation Adaptive equalizer
CN103460659A (en) * 2011-02-07 2013-12-18 日本电信电话株式会社 Digital signal processing device
KR20210046734A (en) * 2018-10-01 2021-04-28 료지 쿠와하타 Biological stimulation device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995012926A1 (en) * 1993-11-05 1995-05-11 Ntt Mobile Communications Network Inc. Replica producing adaptive demodulating method and demodulator using the same
US5602507A (en) * 1993-11-05 1997-02-11 Ntt Mobile Communications Network Inc. Adaptive demodulating method for generating replica and demodulator thereof
WO1995017052A1 (en) * 1993-12-15 1995-06-22 Ntt Mobile Communications Network Inc. Adaptive equalizer
US6504868B1 (en) 1998-03-13 2003-01-07 Nec Corporation Adaptive equalizer
US6473470B1 (en) 1998-05-11 2002-10-29 Nec Corp. Phase-locked loop circuits for communication system
CN103460659A (en) * 2011-02-07 2013-12-18 日本电信电话株式会社 Digital signal processing device
KR20210046734A (en) * 2018-10-01 2021-04-28 료지 쿠와하타 Biological stimulation device

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