JPH1154505A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH1154505A
JPH1154505A JP9220011A JP22001197A JPH1154505A JP H1154505 A JPH1154505 A JP H1154505A JP 9220011 A JP9220011 A JP 9220011A JP 22001197 A JP22001197 A JP 22001197A JP H1154505 A JPH1154505 A JP H1154505A
Authority
JP
Japan
Prior art keywords
silicon nitride
film
nitride film
gate
plasma cvd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9220011A
Other languages
Japanese (ja)
Inventor
Keiichirou Motofusa
敬市郎 本房
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsumi Electric Co Ltd
Original Assignee
Mitsumi Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsumi Electric Co Ltd filed Critical Mitsumi Electric Co Ltd
Priority to JP9220011A priority Critical patent/JPH1154505A/en
Publication of JPH1154505A publication Critical patent/JPH1154505A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To reduce hydrogen content of silicon nitride film, by forming a silicon nitride film to be used as a passivation film covering a semiconductor substrate surface and/or an interlayer insulating film by using a plasma CVD method, and heat-treating the silicon nitride film in a vacuum atmosphere. SOLUTION: A gate 6 is laminated on a gate oxide film 4. A source electrode 7 is in contact with a source region 2. A drain electrode 8 is in contact with a drain region 3. The gate 6, the source electrode 7 and the drain electrode 8 are composed of Al material. As to the gate 6, poly-Si also is much used for a gate electrode. Surfaces of Al wiring layers 6-8 and a field oxide film 5 are covered with a silicon nitride film 9 for passivation, which is a P-SiN film formed by a plasma CVD method. The composition is SiNy Hz . By heat- treating the P-SiN film 9 in a vacuum atmosphere, the hydrogen content of the film is reduced.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、プラズマCVD法
により形成されたシリコン窒化膜の水素含有量を低減す
る半導体装置の製造方法に関する。
The present invention relates to a method for manufacturing a semiconductor device for reducing the hydrogen content of a silicon nitride film formed by a plasma CVD method.

【0002】[0002]

【従来の技術】シリコン窒化膜(Si34)は水分やナ
トリウム(Na)の拡散防止機能、および放射線遮断機
能等に優れるため、シリコン(Si)基板の半導体集積
回路(IC/LSI)のパシベーション膜や層間絶縁膜
として使用される。このシリコン窒化膜はまた、シリコ
ン基板の選択酸化時マスクとしても使用される。
2. Description of the Related Art Since a silicon nitride film (Si 3 N 4 ) is excellent in a function of preventing diffusion of moisture and sodium (Na) and a function of blocking radiation, a silicon (Si) substrate has a semiconductor integrated circuit (IC / LSI). Used as a passivation film or an interlayer insulating film. This silicon nitride film is also used as a mask during selective oxidation of the silicon substrate.

【0003】シリコン窒化膜は、熱CVD、光CVD、
プラズマCVD等、種々の方法で形成される。プラズマ
CVD法により形成されるシリコン窒化膜(以下、他の
方法によるシリコン窒化膜と区別するためP−SiNと
呼ぶ)は、膜中に比較的多量の水素(H2)を含む。水
素含有量は成長条件に依存する。プラズマCVDにより
形成されたシリコン窒化膜(P−SiN)の組成は、厳
密にはSi34ではなく、水素がSi−H及びN−Hの
形でSiおよびNに結合したSixNy Hzの形態を
とる。
A silicon nitride film is formed by thermal CVD, optical CVD,
It is formed by various methods such as plasma CVD. A silicon nitride film formed by a plasma CVD method (hereinafter, referred to as P-SiN to be distinguished from a silicon nitride film formed by another method) contains a relatively large amount of hydrogen (H 2 ) in the film. The hydrogen content depends on the growth conditions. The composition of the silicon nitride film formed by plasma CVD (P-SiN) is strictly not the Si 3 N 4 is SixNy Hz form in which a hydrogen is bound to Si and N in the form of Si-H and N-H Take.

【0004】プラズマCVDは、例えば低圧CVDの処
理温度(700−800℃)より低い処理温度(250
−350℃)でシリコン窒化膜を成長させることができ
る利点がある反面、水素含有量(20−25原子%)が
大きく、低圧CVDの水素含有量(4−8原子%)の数
倍に達する。
In plasma CVD, for example, a processing temperature (250 ° C.) lower than the processing temperature (700-800 ° C.) of low pressure CVD
Although there is an advantage that a silicon nitride film can be grown at −350 ° C.), the hydrogen content (20-25 atomic%) is large, and reaches several times the hydrogen content (4-8 atomic%) of low-pressure CVD. .

【0005】シリコン窒化膜を使用したMOS型の半導
体装置では、窒化膜中から遊離した水素がゲート酸化膜
中へ入ると、電子トラップを形成し、デバイス特性の不
安定要因となる。シリコン窒化膜を使用したバイポーラ
型の半導体装置では、窒化膜中の水素がSi基板に入る
と、電流増幅率hFEの変動要因になる。
In a MOS type semiconductor device using a silicon nitride film, when hydrogen liberated from the nitride film enters the gate oxide film, an electron trap is formed, which causes unstable device characteristics. In a bipolar semiconductor device using a silicon nitride film, when hydrogen in the nitride film enters the Si substrate, it causes a change in the current amplification factor hFE.

【0006】プラズマCVDで形成されるシリコン窒化
膜中の水素含有量を低減するために、(1)成長時のガ
スに酸素(O2)を添加してSiO2とSi34が混合さ
れた窒化酸化膜とするか、(2)プラズマ発生の電源周
波数を低下させる方法が知られている。
In order to reduce the hydrogen content in a silicon nitride film formed by plasma CVD, (1) oxygen (O 2 ) is added to a gas during growth to mix SiO 2 and Si 3 N 4. (2) A method of lowering the power supply frequency of plasma generation is known.

【0007】[0007]

【発明が解決しようとする課題】上述した(1)の酸素
添加法、あるいは(2)の電源周波数低下法は、プラズ
マCVD工程に付加条件を付けるものであるため、シリ
コン窒化膜の成長を制御するプラズマCVD本来の条件
設定が制限される問題がある。この点が本発明で解決し
ようとする課題である。
The above-mentioned method (1) for adding oxygen or the method (2) for lowering the power supply frequency imposes additional conditions on the plasma CVD process, and therefore controls the growth of the silicon nitride film. There is a problem that the setting of the original conditions of the plasma CVD is limited. This is a problem to be solved by the present invention.

【0008】本発明は、プラズマCVD法によるシリコ
ン窒化膜の形成に制限を加えることなく、形成後のシリ
コン窒化膜の水素含有量を低減することができる半導体
装置の製造方法を提供することを目的としている。
It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of reducing the hydrogen content of a formed silicon nitride film without restricting the formation of the silicon nitride film by a plasma CVD method. And

【0009】[0009]

【課題を解決するための手段】本発明の上記目的は、半
導体基板表面を覆うパシベーション膜及び/又は層間絶
縁膜として使用するシリコン窒化膜をプラズマCVD法
により形成する工程と、前記シリコン窒化膜を真空雰囲
気中で熱処理して水素含有量を減少させる工程とを備え
る半導体装置の製造方法で達成できる。
SUMMARY OF THE INVENTION An object of the present invention is to form a silicon nitride film used as a passivation film and / or an interlayer insulating film covering a semiconductor substrate surface by a plasma CVD method. Heat-treating in a vacuum atmosphere to reduce the hydrogen content.

【0010】シリコン窒化膜を形成するプラズマCVD
工程の後に、シリコン窒化膜の水素含有量を低減する工
程を設けると、プラズマCVD工程では、成長しようと
するシリコン窒化膜の膜厚、組成等のシリコン窒化膜に
係る条件だけを念頭においてプラズマCVDを実行でき
る。後工程としての熱処理は、真空雰囲気中で行われ、
シリコン窒化膜中に含有される水素を効率よく脱離させ
る。この結果、水素とホットキャリアとの反応が低減さ
れ、素子特性の劣化が防止される。
[0010] Plasma CVD for forming a silicon nitride film
If a step for reducing the hydrogen content of the silicon nitride film is provided after the step, the plasma CVD step is performed by plasma CVD with only the conditions relating to the silicon nitride film such as the thickness and composition of the silicon nitride film to be grown in mind. Can be executed. Heat treatment as a post-process is performed in a vacuum atmosphere,
Hydrogen contained in the silicon nitride film is efficiently desorbed. As a result, the reaction between hydrogen and hot carriers is reduced, and deterioration of device characteristics is prevented.

【0011】[0011]

【発明の実施の形態】以下、図面に示した実施形態を参
照して、本発明を詳細に説明する。図1は本発明の第1
の実施形態を示すMOS型半導体装置の断面図である。
図中、1はp型シリコン(Si)半導体基板、2および
3は基板1の表面に拡散形成されたn+型のソース領域
及びドレイン領域、4は基板1表面のチャネル領域の上
層を酸化して形成した薄いゲート酸化膜(SiO2)、
5は基板1の表面を酸化した厚いフィールド酸化膜(S
iO2)、6はゲート酸化膜4上に積層されたゲート、
7はソース領域2に接触するソース電極、8はドレイン
領域3に接触するドレイン電極である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to embodiments shown in the drawings. FIG. 1 shows the first embodiment of the present invention.
FIG. 2 is a cross-sectional view of a MOS semiconductor device according to the first embodiment.
In the figure, 1 is a p-type silicon (Si) semiconductor substrate, 2 and 3 are n + -type source and drain regions diffusedly formed on the surface of the substrate 1, and 4 is a layer for oxidizing an upper layer of a channel region on the substrate 1 Gate oxide film (SiO 2 )
5 is a thick field oxide film (S
iO 2 ), 6 are gates stacked on the gate oxide film 4,
Reference numeral 7 denotes a source electrode that contacts the source region 2, and 8 denotes a drain electrode that contacts the drain region 3.

【0012】ゲート6、ソース電極7、ドレイン電極8
は、いずれもアルミニウム(Al)素材である。このう
ちゲート6は、ゲート電極はpoly−siも多用され
る。これらのAl配線層6,7,8およびフィールド酸
化膜5の表面は、パシベーション用のシリコン窒化膜9
で覆われる。このシリコン窒化膜9はプラズマCVDで
形成されたP−SiNであり、組成はSixNyHzで
ある。本発明では、このP−SiN膜9を真空雰囲気中
で熱処理し、膜中の水素含有量を低減する。
Gate 6, source electrode 7, drain electrode 8
Are all aluminum (Al) materials. Of these gates, the gate electrode is often poly-si. The surfaces of these Al wiring layers 6, 7, 8 and field oxide film 5 are covered with a silicon nitride film 9 for passivation.
Covered with. This silicon nitride film 9 is P-SiN formed by plasma CVD, and has a composition of SixNyHz. In the present invention, the P-SiN film 9 is heat-treated in a vacuum atmosphere to reduce the hydrogen content in the film.

【0013】図2は本発明の第2の実施形態を示すバイ
ポーラ型半導体装置の断面図である。図中、11はn型
Si半導体基板、12はこの基板11の表面に深く拡散
形成されたp型のベース領域、13はこのベース領域1
2の表面に薄く拡散形成されたn+型のエミッタ領域、
14はn型基板11の表面に薄く拡散形成されたn+
のコレクタ取り出し領域(コレクタ領域はn型基板11
そのもの)、15は基板11の表面を酸化したフィール
ド酸化膜(SiO2)、16、17、18はAl素材の
ベース、エミッタ、コレクタの各電極、19は表面全体
を覆うパシベーション用のシリコン窒化膜である。
FIG. 2 is a sectional view of a bipolar semiconductor device according to a second embodiment of the present invention. In the figure, 11 is an n-type Si semiconductor substrate, 12 is a p-type base region formed by deep diffusion on the surface of the substrate 11, and 13 is this base region 1.
An n + -type emitter region which is thinly diffused on the surface of
Reference numeral 14 denotes an n + -type collector extraction region which is thinly diffused and formed on the surface of the n-type substrate 11 (the collector region is the n-type substrate 11
15) is a field oxide film (SiO 2 ) obtained by oxidizing the surface of the substrate 11, 16, 17, and 18 are base, emitter and collector electrodes of Al material, and 19 is a silicon nitride film for passivation which covers the entire surface. It is.

【0014】このシリコン窒化膜19はプラズマCVD
で形成されたP−SiNであり、組成はSixNyHz
ある。本発明では、このP−SiN膜19を真空雰囲
気中で熱処理し、膜中の水素含有量を低減する。
This silicon nitride film 19 is formed by plasma CVD.
Is a P-SiN formed at a composition of SixNyHz
is there. In the present invention, the P-SiN film 19 is heat-treated in a vacuum atmosphere to reduce the hydrogen content in the film.

【0015】図3は本発明の第3の実施形態を示す2層
配線式のバイポーラ型半導体装置の断面図である。図
中、11はn型Si半導体基板、12はこの基板11の
表面に深く拡散形成されたp型のベース領域、13はこ
のベース領域12の表面に薄く拡散形成されたn+型の
エミッタ領域、14はn型基板11の表面に薄く拡散形
成されたn+型のコレクタ取り出し領域(コレクタ領域
はn型基板11そのもので、15は基板11の表面を酸
化したフィールド酸化膜(SiO2)、16、17、1
8はAl素材のベース、エミッタ、コレクタの各電極、
19は層間絶縁用の第1層のシリコン窒化膜である。
FIG. 3 is a cross-sectional view of a bipolar semiconductor device of a two-layer wiring type showing a third embodiment of the present invention. In the figure, 11 is an n-type Si semiconductor substrate, 12 is a p-type base region deeply formed on the surface of the substrate 11, and 13 is an n + -type emitter region thinly formed on the surface of the base region 12. Reference numeral 14 denotes an n + -type collector extraction region which is thinly diffused and formed on the surface of the n-type substrate 11 (the collector region is the n-type substrate 11 itself, 15 is a field oxide film (SiO 2 ) obtained by oxidizing the surface of the substrate 11, 16, 17, 1
8 is a base, emitter and collector electrode of Al material,
Reference numeral 19 denotes a first layer silicon nitride film for interlayer insulation.

【0016】第1層のシリコン窒化膜19上には第2層
のAl配線層20、21、22が形成され、更にその表
面全体がパシベーション用の第2層のシリコン窒化膜2
3で覆われる。シリコン窒化膜19、23は何れもプラ
ズマCVDで形成されたP−SiNであり、組成はSi
xNyHzである。本発明では、第1および第2層のP
−SiN膜19、23を真空雰囲気中で熱処理し、膜中
の水素含有量を低減する。
A second layer of Al wiring layers 20, 21, and 22 are formed on the first layer of silicon nitride film 19, and the entire surface thereof is formed of a second layer of silicon nitride film 2 for passivation.
Covered with 3. Each of the silicon nitride films 19 and 23 is P-SiN formed by plasma CVD, and has a composition of Si.
xNyHz. In the present invention, the P and P of the first and second layers are
Heat treating the SiN films 19 and 23 in a vacuum atmosphere to reduce the hydrogen content in the films;

【0017】[実施例1]図1〜図3に示した半導体装
置のP−SiN膜9、19、23は処理温度(400
℃)、処理時間(230sec)のプラズマCVDで膜
厚(6500Å)に形成し、その後、真空度(2×10
-5Torr)、処理温度(350℃)、処理時間(30
sec)の条件で真空熱処理した。
[Embodiment 1] The P-SiN films 9, 19 and 23 of the semiconductor device shown in FIGS.
° C) and a processing time (230 sec) by plasma CVD to a film thickness (6500 °).
-5 Torr), processing temperature (350 ° C.), processing time (30
Vacuum heat treatment was performed under the conditions of sec).

【0018】[0018]

【発明の効果】以上述べたように本発明によれば、プラ
ズマCVD法によるシリコン窒化膜の形成に制限を加え
ることなく、形成後のシリコン窒化膜の水素含有量を低
減することができる半導体装置の製造方法を提供するこ
とができる。
As described above, according to the present invention, it is possible to reduce the hydrogen content of a formed silicon nitride film without limiting the formation of the silicon nitride film by the plasma CVD method. Can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施形態を示すMOS型半導体
装置の断面図である。
FIG. 1 is a cross-sectional view of a MOS semiconductor device according to a first embodiment of the present invention.

【図2】本発明の第2の実施形態を示すバイポーラ型半
導体装置の断面図である。
FIG. 2 is a cross-sectional view of a bipolar semiconductor device according to a second embodiment of the present invention.

【図3】本発明の第3の実施形態を示す2層配線式のバ
イポーラ型半導体装置の断面図である。
FIG. 3 is a cross-sectional view of a two-layer wiring type bipolar semiconductor device according to a third embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1,11 Si半導体基板 2 ソース領域 3 ドレイン領域 4 ゲート酸化膜 5,15 フィールド酸化膜 6 ゲート 7 ソース電極 8 ドレイン電極 9,19,23 シリコン窒化膜(P−SiN) 12 ベース領域 13 エミッタ領域 14 コレクタ取り出し領域 16 ベース電極 17 エミッタ電極 18 コレクタ電極 20,21,22 第2層のAl配線層 1,11 Si semiconductor substrate 2 source region 3 drain region 4 gate oxide film 5,15 field oxide film 6 gate 7 source electrode 8 drain electrode 9,19,23 silicon nitride film (P-SiN) 12 base region 13 emitter region 14 Collector extraction region 16 Base electrode 17 Emitter electrode 18 Collector electrode 20, 21, 22 Second Al wiring layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板表面を覆うパシベーション膜
及び/又は層間絶縁膜として使用するシリコン窒化膜を
プラズマCVD法により形成する工程と、 前記シリコン窒化膜を真空雰囲気中で熱処理して水素含
有量を減少させる工程とを備えることを特徴とする半導
体装置の製造方法。
A step of forming a silicon nitride film used as a passivation film and / or an interlayer insulating film covering a surface of a semiconductor substrate by a plasma CVD method, and a heat treatment of the silicon nitride film in a vacuum atmosphere to reduce a hydrogen content. A method of manufacturing a semiconductor device, comprising:
JP9220011A 1997-07-30 1997-07-30 Manufacture of semiconductor device Pending JPH1154505A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9220011A JPH1154505A (en) 1997-07-30 1997-07-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9220011A JPH1154505A (en) 1997-07-30 1997-07-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH1154505A true JPH1154505A (en) 1999-02-26

Family

ID=16744541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9220011A Pending JPH1154505A (en) 1997-07-30 1997-07-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH1154505A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007194394A (en) * 2006-01-19 2007-08-02 Renesas Technology Corp Method for manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007194394A (en) * 2006-01-19 2007-08-02 Renesas Technology Corp Method for manufacturing semiconductor device

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