JPH1141488A - Digital image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital image processor which decreases the number of buffer memories and is adaptive to variation in delay time accompanying alteration of process contents in an image processing part. SOLUTION: Image processing parts PY1 to PYn are connected in series and a buffer memory BY is arranged behind them to constitute an image processing system 2. The image processing parts PY1 to PYn are each provided with a signal processing part 4 and a delay part 5. The signal processing part 4 is so constituted as to switch processings which are different in time needed for image processing. The delay part 5 generates a delayed synchronizing signal obtained by delaying a synchronizing signal by a delay time corresponding to processing contents. The image signal after the image processing and the delayed synchronizing signal which is delayed by the image processing time are supplied to a following-stage image processing part. After the image signal processed by the final-stage image processing part is written in a buffer memory BY according to the delayed synchronizing signal outputted by the final-stage image processing part, the image processed signal is read out according to an input reference synchronizing signal RS.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-stage cascade-type digital image processing apparatus constituted by serially connecting a plurality of image processing units for performing digital image processing on image signals. The present invention relates to a digital image processing apparatus in which a section delays a synchronization signal by a time required for image processing and supplies the signal to a next-stage image processing section.

[0002]

2. Description of the Related Art Generally, an apparatus for processing image data converted from a television signal or the like into a digital signal in real time comprises a plurality of serially connected image processing units which operate on input image data. Have been. These image processing units perform various processes on image data based on a synchronization signal such as a clock signal in units of pixels, a horizontal synchronization signal, and a vertical synchronization signal. The synchronization signal is generated by controlling the timing by a single or a plurality of timing controllers.

Incidentally, the time required for each image processing unit to process image data differs depending on the content of the processing.
Therefore, the delay time from when the image data is supplied to when the image data subjected to the predetermined processing is output is:
It differs depending on each image processing unit. Therefore, the timing control unit needs to supply synchronization signals at different timings to the image processing units according to the respective delay times of the image processing units connected in series.

FIG. 8 is a block diagram of a conventional digital image processing device, and FIG. 9 is a block diagram of another conventional digital image processing device. A conventional digital image processing apparatus 101 shown in FIG. 8 includes two image processing systems 102 and 103.
, The timing control unit 104, the buffer memory 105
It is composed of In the first image processing system 102, a plurality of image processing units 102-1 to 102-n are connected in series. In the second image processing system 103, a plurality of image processing units 103-1 to 103-n are connected in series.

FIG. 8 shows an example in which the first image processing system 102 performs image processing on an input luminance signal YI and the second image processing system 103 performs image processing on an input chrominance signal CI. ing. Image-processed luminance signal 102Y
After the color difference signal 103C subjected to image processing is temporarily stored in the buffer memory 105, the input reference synchronization signal D
Based on K, the luminance signal YO subjected to image processing and the color difference signal CO subjected to image processing are read out from the buffer memory 105 and output.

[0006] The timing control unit 104, based on the input synchronization signal DI, the first stage image processing unit 102-1 of the first system.
Generates and outputs a synchronization signal D11 for
A synchronization signal D21 for the first-stage image processing unit 103-1 of the second system is generated and output. Here, the delay time until the image (luminance) data subjected to the predetermined image processing is output from the first-stage image processing unit 102-1 of the first system is TY.
Assuming that the synchronization signal D1 is 1, the timing control unit 104 generates a synchronization signal that is delayed by the delay time TY1 with respect to the synchronization signal D11 for the first-stage image processing unit 102-1 of the first system, and generates the synchronization signal as the first synchronization signal. It is output as a synchronization signal D12 to the image processing unit 102-2 of the second stage of the system.

If the delay time until the image (color difference) data subjected to the predetermined image processing is output from the first-stage image processing unit 103-1 of the second system is TC1, the timing control unit 104 First-stage image processing unit 103-1
Is generated by delaying the synchronization signal D21 with respect to the synchronization signal D21 by the delay time TC1.
It is output as a synchronization signal D22 to the image processing unit 103-2 in the second stage of the system. As described above, the timing control unit 104 is configured to generate and output a synchronization signal to be supplied to the next-stage image processing unit in accordance with each delay time of the plurality of image processing units connected in series. ing.

Further, some of the plurality of image processing units, for example, the image processing unit 102-2 in the second stage of the first system has two types of processing contents (processing A and processing B). Is required to be selectively switched, the delay time also changes with the change in the processing content. For this reason, the timing control unit 104 determines the timing of the synchronization signal for each of the image processing units in the next and subsequent stages by using the image processing unit 102 in the second stage of the first system.
-2 corresponds to the timing Tna corresponding to the case where the process A is performed.
It is necessary to change the timing to the timing Tnb corresponding to the case where the process B is performed.

As described above, in the conventional digital image processing apparatus 101 shown in FIG. 8, the timing control section 104 must generate a synchronization signal having a different timing for each image processing section. Since the timing of the synchronization signal to be supplied to the subsequent image processing unit must be changed in response to the change in the delay time due to the change in the processing contents in the above, the configuration of the timing control unit 104 becomes complicated. is there.

Therefore, in the digital image processing device 111 shown in FIG. 9, each of the image processing units 102-1 to 102-n, 1
03-1 to 103-n, buffer memories 115-1 to 115-n and 116-1 to 1-5 in the FIFO format, respectively.
116-n, and changes in the treatment delay are stored in these buffer memories 115-1 to 115-n and 116-1 to 116.
-N so that the delay change is not transmitted to the subsequent stage. In FIG. 9, reference numerals 112, 1
Reference numeral 13 denotes first and second image processing systems, and reference numeral 114 denotes a timing control unit.

Japanese Patent Application Laid-Open No. 6-44351 discloses that
An analog image signal, a vertical synchronizing signal, and a horizontal synchronizing signal are separated from the input composite image signal, the analog image signal is converted into a digital image signal, and the non-linear density conversion, contour enhancement, and binarization processing of the digital image signal is performed. In the image processing method and the image processing apparatus in which the processed data is written to the frame memory, read by the microprocessor, and computer-processed by the microprocessor or the image processor, a vertical trigger pulse is separated from the separated vertical synchronization signal into a horizontal synchronization signal. , A horizontal trigger pulse and a pixel clock pulse corresponding to the number of pixels are generated, and the conversion and processing of an analog image signal into a digital image signal is performed by performing pixel processing using a pixel clock pulse for each pixel clock. Terminate and perform each process at the stage of performing each process The image processing method and image processing apparatus where only data transmission lag was to transmit delays each pulse generated has been described.

[0012]

The conventional digital image processing apparatus 101 shown in FIG.
, It is necessary to generate a synchronization signal at a different timing for each image processing unit, and furthermore, a synchronization signal to be supplied to a subsequent image processing unit in response to a change in delay time due to a change in processing content in the image processing unit. Since the signal timing must be changed, there is a problem that the configuration of the timing control unit 104 is complicated.

In another conventional digital image processing apparatus 111 shown in FIG. 9, buffer memories 115-1 to 115-n and 116-1 to 116-of a FIFO format are provided between image processing units.
n, the change in the treatment delay is absorbed by these buffer memories 115-1 to 115-n and 116-1 to 116-n, and the delay change is not transmitted to the subsequent stage. Processing delay occurs,
The apparatus becomes large and expensive due to the provision of a large number of buffer memories.

In the image processing method and the image processing apparatus described in Japanese Patent Application Laid-Open No. 6-44351, the horizontal trigger pulse and the vertical trigger pulse in which each process is delayed by a delay due to the previous process, and the pixel clock synchronized therewith. Although it is performed in real time on the basis of this, it is not possible to cope with a change in delay time due to a change in processing content in the image processing unit.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and reduces the number of buffer memories, does not cause unnecessary processing delay, and
It is an object of the present invention to provide a digital image processing apparatus capable of coping with a change in delay time due to a change in processing content in an image processing unit.

[0016]

According to the present invention, there is provided a digital image processing apparatus comprising: a plurality of image processing units each including a plurality of image processing units connected in series and a buffer memory; In the side-by-side digital image processing device, the image processing unit includes a signal processing unit having a known processing delay time, and a delay unit that delays and outputs the input synchronization signal by the processing delay time. The signal processing unit is configured so that its processing content can be changed by hardware or software, and the delay unit is configured to change the time for delaying the synchronization signal in response to the change in the processing delay time accompanying the change in the processing content. It is characterized by having done.

In a digital image processing apparatus according to the present invention, in a digital image processing apparatus in which a plurality of image processing units are connected in series, the image processing unit selectively switches a plurality of processes having different processing times. In addition to the possible configuration, a delay unit is provided which delays and outputs a synchronization signal input to the image processing unit by a processing time required for the selected processing.

Preferably, the synchronization signal is one or more of a horizontal synchronization signal, a vertical synchronization signal, and a field identification signal.

Each image processing section delays the synchronization signal input to each image processing section by the processing time required for image processing in the image processing section, and outputs the delayed synchronization signal. Therefore, the processing time of the entire image processing unit group including the plurality of image processing units connected in series can be minimized. In addition, each image processing unit, when the processing time is changed due to the change of the processing content,
Since the input synchronization signal is configured to be delayed by the changed processing time and output, each image processing unit can switch the processing content independently of the other image processing units.

[0020]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of a digital image processing apparatus according to the present invention. A digital image processing apparatus 1 according to the present invention performs an image processing system 2 for a luminance signal that performs various digital image processing on an input luminance signal Y0 and outputs an output luminance signal YP subjected to the image processing.
And an image processing system 2 for a color difference signal that performs various digital image processing on the input color difference signal C0 and outputs an output color difference signal CP that has been subjected to the image processing.

The luminance signal image processing system 2 includes a luminance signal image processing group in which a plurality of image processing units PY1 to PYn are connected in series, and a luminance signal buffer memory BY. The image processing system 3 for color difference signals includes a plurality of image processing units P
An image processing group for color difference signals in which C1 to PCn are connected in series, and a buffer memory CY for color difference signals are provided. Each of the image processing units PY1 to PYN and PC1 to PCN includes a signal processing unit 4 and a delay unit 5. Although FIG. 1 shows a configuration in which each of the image processing systems 2 and 3 includes an n-stage image processing unit, the number of stages of the image processing units connected in series for each of the image processing systems 2 and 3 is different. There may be.

The digitized input luminance signal Y0 is supplied to the first stage image processing section PY1 in the luminance signal image processing system 2. The digitized input color difference signal S0 is supplied to the first stage image processing unit PC1 in the color difference signal image processing system 3. The input synchronization signal S0 is supplied to the first-stage image processing unit PY1 in the image processing system 2 for luminance signals and the first-stage image processing unit PC1 in the image processing system 3 for color difference signals.

Here, the input synchronization signal S0 is a vertical synchronization signal, a horizontal synchronization signal, and a field identification signal. In addition,
The synchronization signal S0 may use only a vertical synchronization signal,
Only the horizontal synchronization signal may be used. Also, the synchronization signal S0
May use only the field identification signal. further,
As the input synchronization signal S0, two or more signals from among a vertical synchronization signal, a horizontal synchronization signal, and a field identification signal may be used. The image processing units PY1 to PYn and PC1 to PC
n is the input synchronization signal S0 or the delayed synchronization signals YS1 to YSn-1, CS1 to C1 supplied from the preceding image processing unit.
Based on Sn-1, the input luminance signal Y0, the input color difference signal C0, or the luminance signal Y supplied from the preceding image processing unit.
The vertical pixel position, the horizontal pixel position, and the field identification of the color difference signals C1 to Cn-1 are performed to perform predetermined image processing.

Each of the image processing units PY1 to PYn and PC1 to PCn connected in series in each of the image processing systems 2 and 3 performs different image processing. For example, the first stage image processing unit P
Y1 and PC1 perform horizontal filter processing, second-stage image processing units PY2 and PC2 perform vertical image processing, and n-th image processing units PYn and PCn perform noise reduction processing. These processes are all performed on a pixel-by-pixel reference clock (not shown).
The arithmetic processing is performed in synchronization with.

The first-stage image processing unit PY1 in the image processing system 2 for luminance signal performs predetermined image processing (for example, horizontal filter processing) on the input luminance signal Y0, and executes the processed luminance signal Y1. Is output. The luminance signal Y1 is supplied to the second-stage image processing unit PY2. The first-stage image processing unit PY1 in the image processing system 2 for the luminance signal receives the input synchronization signal S0
, And performs predetermined image processing (for example, horizontal filtering) on the input luminance signal Y0 while performing vertical synchronization, horizontal synchronization, field identification, and the like. The predetermined image processing is performed by the signal processing unit 4 in the image processing unit PY1.
Do.

The image processing unit PY1 at the first stage in the image processing system 2 for the luminance signal performs an image processing time from when the input luminance signal Y0 is supplied to when the luminance signal Y1 subjected to the predetermined image processing is output. It generates and outputs a delayed synchronization signal YS1 obtained by delaying the input synchronization signal Y0 by an amount. The delay synchronization signal YS1 is supplied to the second-stage image processing unit PY2. The generation and output of the delay synchronization signal YS1 are performed by the image processing unit P.
This is performed by the delay unit 5 in Y1.

The second-stage image processing unit PY2 performs vertical synchronization, horizontal synchronization, field identification, and the like of the luminance signal Y1 supplied from the preceding stage based on the delayed synchronization signal YS1 supplied from the preceding stage. A luminance signal Y2 obtained by subjecting the supplied luminance signal Y1 to predetermined image processing (for example, vertical filter processing) is output. Second stage image processing unit PY
2 generates and outputs a delay synchronization signal YS2 which is delayed from the delay synchronization signal YS1 supplied from the preceding stage by the image processing time in the second stage image processing unit PY2.

As described above, each image processing section supplies a luminance signal obtained by subjecting the input luminance signal to predetermined image processing to the subsequent image processing section, and also converts the input synchronization signal to image processing. A delayed synchronization signal delayed by the required time is generated and supplied to a subsequent image processing unit.

The luminance signal Yn output from the last stage image processing unit PYn is based on the delay synchronization signal YSn output from the last stage image processing unit PYn.
And then read as an output luminance signal YP based on the input reference synchronization signal RS.

Similar processing is performed in the color difference signal image processing system 3. The first-stage image processing unit PC1 performs vertical synchronization, horizontal synchronization, field identification, and the like of the input color difference signal C0 based on the input synchronization signal S0, and outputs the input color difference signal C0.
And outputs a color difference signal C1 that has been subjected to predetermined image processing. The first-stage image processing unit PC1 generates and outputs a delayed synchronization signal CS1 obtained by delaying the input synchronization signal S0 by the time required for image processing.

The second-stage image processing section PC2 performs predetermined image processing based on the color difference signal C1 and the delay synchronization signal CS1 supplied from the first-stage image processing section PC1, outputs a color difference signal C2, and outputs a delay signal. A delayed synchronization signal C obtained by delaying the synchronization signal CS1 by the time required for image processing.
S2 is output.

The color difference signal Cn output from the last-stage image processing unit PCn is based on the delay synchronization signal CSn output from the last-stage image processing unit PCn.
And then read out as an output color difference signal CP based on the input reference synchronization signal RS.

As described above, the digital image processing apparatus 1 according to the present invention includes the image processing units PY1 to PYn and PC1 to PCY1.
PCn are connected in series, and each of the image processing units PY1 to PYn,
Since each of the PCs 1 to PCn performs a different process with a different image processing time (delay time) and supplies the same to the subsequent image processing unit, all processes are performed from the time when the input luminance signal Y0 is supplied. The total processing delay time (luminance signal total processing time) until the luminance signal Yn is output, and the total processing delay time from when the input chrominance signal C0 is supplied to when the chrominance signal Cn subjected to all the processing is output. Is different from the processing delay time (color difference signal total processing time).

For this reason, each of the buffer memories BY and CY
Uses a memory capacity capable of absorbing a processing time difference between the total processing time of the luminance signal and the total processing time of the chrominance signal. The buffer memory BY for the luminance signal stores the luminance signal Yn output from the image processing unit PYn at the last stage.
Is written into the buffer memory BY by a write signal (not shown) generated based on the delay synchronization signal YSn output from the image processing unit PYn at the last stage. Further, in the buffer memory CY for the color difference signal, a write signal generated based on the delay synchronization signal CSn output from the image processor PCn at the last stage, and the color difference signal Cn output from the image processor PCn at the last stage. Buffer memory CY
Write to. And a buffer memory BY for the luminance signal.
The luminance signal Yn stored in the buffer memory CY and the color difference signal Cn stored in the buffer memory CY for the color difference signal are output from each of the buffer memories BY and CY by a read signal (not shown) generated based on the input reference synchronization signal RS. By reading, the output luminance signal YP and the output color difference signal CP are output as signals in phase with each other.

Each image processing section PY1 to PYn, PC1 to P
The signal processing unit 4 in Cn is configured so that a plurality of different image processing contents such as processing A and processing B can be switched by hardware or software. Further, the delay unit 4 in each of the image processing units PY1 to PYn and PC1 to PCn adjusts the input synchronization signal (delay synchronization) in response to a change in processing time accompanying a change in image processing content in the signal processing unit 4. The delay time for delaying and outputting the signal is changed. When the signal processing unit 4 performs the image processing of the process A, the delay unit 5 applies the processing time required for the processing A, that is, the delay time A associated with the processing A, to the synchronization signal (delayed synchronization signal) supplied from the previous stage. When the signal processing unit 4 performs image processing of the process B by generating and outputting a delayed synchronization signal delayed by an amount corresponding to the delay, the delay unit 5 processes the synchronization signal (delayed synchronization signal) supplied from the preceding stage. A delay synchronization signal is generated and output delayed by the processing time required for B, that is, the delay time B associated with processing B.

FIG. 2 is a timing chart for explaining signal delay in the image processing unit. FIG. 2A shows the reference clock in a state where the time axis is enlarged, and FIG. 2B shows the horizontal synchronization signal in a state where the time axis is enlarged. 2C illustrates a horizontal synchronization signal, FIG. 2D illustrates a vertical synchronization signal input to the image processing unit, FIG. 2E illustrates a field identification signal input to the image processing unit, and FIG. f) indicates a luminance signal or a color difference signal (luminance signal input or color difference signal input) input to the image processing unit. 2G shows a delayed horizontal synchronization signal output from the image processing unit, FIG. 2H shows a delayed vertical synchronization signal output from the image processing unit, and FIG. 2I shows an output from the image processing unit. FIG. 2 (j) shows a processed luminance signal or a processed color difference signal (luminance signal output or color difference signal output) which is processed and output by the image processing unit.

The signal processing section 4 in the image processing section is the same as that shown in FIG.
When a predetermined signal processing is performed on the luminance signal input or the color difference signal input shown in (f) and the processing time until the processed luminance signal or the processed color difference signal shown in FIG. , The delay unit 5 in the image processing unit
The horizontal synchronization signal, the vertical synchronization signal, and the field identification signal shown in (c) to (e) are respectively delayed by the processing delay time d, and the delayed horizontal synchronization signal and the delay shown in FIGS. A vertical synchronization signal and a delay field identification signal are output.

FIG. 3 is a timing chart showing the write operation to the buffer memory and the read operation from the buffer memory. FIG. 3A shows the image processing systems 2 and 3
The input synchronization signal S0 supplied to each of the first-stage image processing units PY1 and PC1 is shown in FIG.
3 (c) shows an input color difference signal C0 supplied to the first-stage image processing unit PC1. FIG. 3D shows the luminance delay synchronization signal YSn output from the last-stage image processing unit PYn of the luminance signal image processing unit group, and FIG. 3E shows the delay output from the same image processing unit PYn. The luminance signal Yn is shown. FIG. 3F shows the color difference delay synchronization signal CSn output from the last stage image processing unit PCn of the color difference signal image processing unit group.
Is a delayed color difference signal Cn output from the image processing unit PCn.
Is shown. FIG. 3H shows the reference synchronization signal RS, and FIG.
FIG. 3I shows the output luminance signal YP read from the luminance signal buffer memory BY, and FIG. 3J shows the output color difference signal CP read from the color difference signal buffer memory CY.

FIG. 3 shows an image processing unit group PY1 for a luminance signal.
The total luminance signal processing time (luminance signal total delay time) in PYn to PYn is less than the image processing unit groups PC1 to PC1 for color difference signals.
It shows a case where it is shorter than the total color signal processing time (total color signal delay time) of PCn. As shown in FIG. 3D, each of the image processing units PY1 to PYn for the luminance signal
, Yd1, Yd2,..., Yd
Assuming that n, the sum of each processing time (delay time) is the luminance signal total processing time (luminance signal total delay time).
As shown in FIG. 3F, each image processing unit P for the color difference signal
The processing time (delay time) of C1 to PCn is Cd1, Cd
Assuming that 2,..., Cdn, the sum of the respective processing times (delay times) becomes the color difference signal total processing time (color difference signal total delay time).

The delay time (Yd1 +) in each of the image processing units PY1 to PYn with respect to the input luminance signal Y0 shown in FIG.
The delayed luminance signal Yn output after being delayed by Yd2 +... + Ydn) is written to the luminance signal buffer memory BY at the timing shown in FIG. FIG.
Each of the image processing units P for the input color difference signal C0 shown in FIG.
Delay time at C1 to PCn (Cd1 + Cd2 +... + C
dn) and the delayed color difference signal Cn output after being delayed by
Are written to the color difference signal buffer memory CY at the timing shown in FIG.

Next, the video data stored in each of the buffer memories BY and CY (the processed luminance signal and the processed luminance signal and common signal) are generated by a common read pulse generated based on the input reference synchronization signal RS shown in FIG. By reading out the color difference signal), the output luminance signal YP and the output color difference signal CP in phase are obtained as shown in FIGS. 3 (i) and 3 (J). Note that BYd is a delay time from when the delayed luminance signal Yn is written to the buffer memory BY for luminance signal to when it is read out, and CYd is from when the delayed color difference signal Cn is written to the buffer memory CY for color difference signal until it is read out. Is the delay time.

As shown in FIG. 3, even if the processing delay time is different for each image processing unit, the luminance signal total processing time (the luminance signal total processing time) in the luminance signal image processing unit groups PY1 to PYn is different. Delay time) and the total color-difference signal processing time (color-difference signal total delay time) of the color-difference signal image processing units PC1 to PCn, even if the image-processed output luminance signal YP and output color-difference signal CP Can be output in a synchronized state.

In the digital image processing device 1 according to the present invention, the signal processing unit 4 in the image processing unit is configured to be able to switch processing contents by software or hardware. Here, it is assumed that the processing times (delay times) of the two signal processings are different. In this case, the delay unit 5 delays the synchronization signal by the same time as the processing time determined by the processing content. As a result, in the output of the image processing unit, no change occurs in the phase relationship between the processed image data and the synchronization signal. It does not affect the timing of the treatment section.
Here, switching of the processing content and switching of the delay time of the synchronization signal corresponding to the processing content will be described. It is assumed that the processing time (delay time) of each signal processing is known.

FIG. 4 is a block diagram showing a specific example of an image processing section for switching the processing contents and switching the delay time of the synchronization signal corresponding to the processing contents.
The signal processing unit 4 of the image processing unit P shown in FIG. 4 performs processing A on the input video signal (luminance signal or color difference signal).
, A second processor 42 for performing processing B on an input video signal (luminance signal or color difference signal), and one of the outputs of the processors 41 and 42 Processing output selection switch circuit 4 for selecting and outputting as a processing video signal (processing luminance signal or processing color difference signal)
3 is provided.

A delay unit 5 of the image processing unit P shown in FIG. 4 includes a first delay unit 51 for delaying an input synchronization signal by a processing time (delay time A) required for processing A, Delay unit 52 for delaying the output by a processing time (delay time B) required for processing B, and a delay output selection switch for selecting one of the outputs of the delay units 51 and 52 and outputting the selected output as a delay synchronization signal And a circuit 53. Processing output selection switch circuit 43 and delay output selection switch circuit 5
The switching operation is performed in conjunction with 3. The delay unit 5 corresponding to the switching of the processors 41 and 42
By switching between 1 and 52, the timing of the processed video signal and the timing of the delay synchronization signal are adjusted.

FIG. 5 is a block diagram showing another specific example of the image processing section for switching the processing contents and switching the delay time of the synchronization signal corresponding to the processing contents. The signal processing unit 40 of the image processing unit P illustrated in FIG. 5 includes a programmable processor 44 that changes processing contents based on a supplied program, and a program changing unit 45 that changes a supplied program. The delay unit 50 of the image processing unit P shown in FIG. 5 includes a programmable delay unit 54 that can change the delay time, and a delay time changing unit 5 that changes the delay time set in the programmable delay unit 54.
5 is provided. The program changing means 45 and the delay time changing means 55 are operated in conjunction with each other. When the program of the process A is supplied to the processor 44, the delay time A is set in the programmable delay unit 54,
When the program of the processing B is supplied to the processor 44, the delay time B is set in the programmable delay unit 54 so that the timing of the processing video signal and the timing of the delay synchronization signal are matched.

Although FIGS. 4 and 5 show an example in which two types of processing are switched, three or more types of processing may be switched.

Next, a specific circuit configuration of the delay unit for delaying the synchronization signal will be described. FIG. 6 is a block diagram showing a specific example of the delay unit, and FIG. 7 is a block diagram showing another specific example of the delay unit. FIG. 6 shows a delay device constituted by using two delay circuits 56 and 57 having different clock inputs. The input field identification signal and the vertical synchronizing signal are delayed by the first delay circuit 56 at a time interval of the horizontal synchronizing signal by a time equal to or less than a required delay amount,
A first delayed field identification signal HFV and a first delayed vertical synchronization signal HVD are obtained, and these signals HFV, HV
D is input to the second delay circuit 57. Further, the horizontal synchronization signal is input to the second delay circuit 57. In the second delay circuit 57, a first delay field identification signal HF is generated based on a reference clock which is a sampling clock of an image.
V, the first delayed vertical synchronizing signal HVD and the horizontal synchronizing signal are further delayed by an appropriate clock time delay,
The delay outputs (delayed field identification signal, delayed vertical synchronizing signal, delayed horizontal synchronizing signal) of the desired delay time are obtained in total by the two delay circuits 56 and 57.

FIG. 7 shows a delay circuit 5 such as a shift register.
8 illustrates a delay device configured using the reference numeral 8. All of the field identification signal, the vertical synchronization signal, and the horizontal synchronization signal are supplied to a delay circuit 58 such as a shift register, and these signals are delayed by a required number of clocks based on a reference clock.
A delay output (delayed field identification signal, delayed vertical synchronization signal, delayed horizontal synchronization signal) is obtained.

[0050]

As described above, in the digital image processing apparatus according to the present invention, each image processing section delays the synchronization signal input to each image processing section by the processing time required for image processing in the image processing section. When the processing time is changed due to the change of the processing content, the input synchronization signal is delayed by the changed processing time and output. The processing time of the entire image processing unit group including a plurality of image processing units connected in series can be minimized, and each image processing unit can switch processing contents independently of other image processing units. .

Therefore, it is possible to minimize the buffer memory and switch a plurality of processing contents, and the switching of the processing contents does not affect the operation of other image processing units in the apparatus or the entire processing delay time. A digital image processing device can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital image processing apparatus according to the present invention.

FIG. 2 is a timing chart illustrating signal delay in an image processing unit.

FIG. 3 is a timing chart showing a write operation to a buffer memory and a read operation from a buffer memory;

FIG. 4 is a block diagram showing a specific example of an image processing unit that switches processing contents and switches a delay time of a synchronization signal corresponding to the processing contents.

FIG. 5 is a block diagram showing another specific example of the image processing unit for switching the processing contents and switching the delay time of the synchronization signal corresponding to the processing contents.

FIG. 6 is a block diagram showing a specific example of a delay unit.

FIG. 7 is a block diagram showing another specific example of the delay unit.

FIG. 8 is a block diagram of a conventional digital image processing apparatus.

FIG. 9 is a block diagram of another conventional digital image processing apparatus.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Digital image processing apparatus, 2 ... Image processing system for a luminance signal, 3 ... Image processing system for a color difference signal, 4,40 ... Signal processing part, 5,50 ... Delay part, 41,42 ... Processor, 43 ... Processing output selection switch circuit, 44 ... Programmable processor, 45 ... Program changing means, 51, 52 ... Delay device,
53: delay output selection switch circuit, 54: programmable delay device, 55: delay time changing means, BC: buffer memory for color difference signal, BY: buffer memory for luminance signal, C0: input color difference signal, C1 to Cn ... , The output color difference signals, CS1 to CSn-1.
Delay synchronization signal in image processing system for color difference signal, PC1
... PVn, PY1 to PYn: image processing unit, RS: input reference synchronization signal, S0: input synchronization signal, Y0: input luminance signal, Y1 to Yn: processed luminance signal, YP: output luminance signal, YS1 Yn-1: a delay synchronization signal in the image processing system for the luminance signal.

Claims (4)

[Claims] 1. A digital image processing apparatus in which a plurality of image processing systems each including an image processing unit group in which a plurality of image processing units are connected in series and a buffer memory are arranged in parallel, wherein the image processing unit has a known processing delay time. And a delay unit for delaying the input synchronization signal by the processing delay time and outputting the same, and the signal processing unit is capable of changing its processing contents by hardware or software. The digital image processing apparatus, wherein the delay unit is configured to change a time for delaying the synchronization signal in response to a change in processing delay time accompanying a change in the processing content. 2. The digital image processing apparatus according to claim 1, wherein the synchronization signal is one or more of a horizontal synchronization signal, a vertical synchronization signal, and a field identification signal. 3. A digital image processing apparatus in which a plurality of image processing units are connected in series, wherein said image processing unit has a configuration capable of selectively switching a plurality of processes having different processing times, A digital image processing apparatus comprising: a delay unit that delays a synchronization signal input to a processing unit by a processing time required for the selected processing and outputs the delayed synchronization signal. 4. The digital image processing device according to claim 3, wherein the synchronization signal is one or more of a horizontal synchronization signal, a vertical synchronization signal, and a field identification signal.