JP2011109576A - Imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a sensitivity of an imaging apparatus, and to suppress reduction in a horizontal resolution and a vertical resolution to a minimum. <P>SOLUTION: The imaging apparatus includes: an imaging means (2); a signal processing means (6) for outputting a video signal of an interlaced scanning system based on an imaging signal read from the imaging means (2); and a pixel adding means (7), which includes a pixel extracting means (71) for delaying the imaging signal by the unit of a field or the unit of a line to simultaneously extract the respective pixel values in a pixel of interest and a plurality of reference pixels around the pixel of interest, and which adds, to a pixel of interest (P22) in a predetermined ratio, pixel values in first and second reference pixels (P11, P13) positioned in upper and lower directions of a screen before one field, and in third and fourth reference pixels (P31, P33) positioned in upper and lower directions of the screen after one field. The number and ratio of reference pixels to be added are switched according to a level of the imaging signal. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an imaging apparatus capable of obtaining a captured image with higher sensitivity in a low-illuminance imaging environment.

  The conventional imaging device is configured to realize double sensitivity by mixing charges of pixels adjacent in the horizontal direction (see, for example, Patent Document 1).

Japanese Examined Patent Publication No. 7-63181 (page 4, paragraph 0045)

  The conventional imaging device has a problem that the sensitivity can be increased only up to twice.

  The present invention has been made to solve the above-described problems, and can obtain a high-sensitivity image pickup device that can increase sensitivity more than twice as much and minimize the decrease in horizontal resolution and vertical resolution. With the goal.

In order to solve the above problems, an imaging apparatus according to the present invention provides:
Imaging means;
A signal processing means for outputting an interlaced scanning video signal based on the imaging signal read from the imaging means;
Pixel extraction means for delaying the imaging signal in field units and line units to simultaneously extract each pixel value of a target pixel and a plurality of reference pixels around it;
In the pixel of interest
A first reference pixel located directly above the screen one field before the target pixel;
A second reference pixel located in the direction directly below the screen one field before the target pixel;
The pixel values of the third reference pixel located in the direction directly above the screen one field after the target pixel and the fourth reference pixel located in the direction directly below the screen one field after the target pixel are added at a predetermined ratio. It is characterized by comprising a pixel addition means.

  According to the imaging apparatus of the present invention, the sensitivity can be improved up to 5 times while minimizing the degradation of the image resolution, and the subject can be visually recognized even in an extremely dark low-light environment.

It is a block block diagram which shows the imaging device of Embodiment 1 of this invention. FIG. 2 is a block configuration diagram illustrating an example of a pixel addition circuit in FIG. 1. It is a figure which shows the time and space arrangement | positioning of the pixel added by the pixel addition circuit of FIG. It is a figure which shows the spatial arrangement | positioning of the pixel added by the pixel addition circuit of FIG. FIG. 2 is a timing diagram illustrating data appearing in each unit of the imaging apparatus in FIG. 1. It is an internal block block diagram which shows an example of the pixel addition circuit used with the imaging device of Embodiment 2 of this invention. It is a block block diagram which shows the imaging device of Embodiment 3 of this invention. FIG. 8 is a timing diagram illustrating data appearing in each unit of the imaging apparatus in FIG. 7.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing an imaging apparatus according to Embodiment 1 of the present invention. Hereinafter, an image pickup apparatus compatible with NTSC television will be described as an example. In FIG. 1, the lens 1 focuses the subject image on the imaging surface of the solid-state imaging device 2. From the imaging signal photoelectrically converted and transferred and output by the solid-state imaging device 2, noise and the like are removed by the correlated double sampling processing circuit 3. The programmable gain amplifier circuit 4 amplifies the output signal of the correlated double sampling processing circuit 3 with a gain controlled by the control signal output from the control circuit 13 and outputs the amplified signal. The A / D conversion circuit 5 converts the output signal of the programmable gain amplification circuit 4 into a digital signal.

  The digital signal processing circuit 6 applies a defective pixel correction process, a color interpolation process, a gradation correction process, a noise reduction process, a contour correction process, a white balance adjustment process, a signal amplitude adjustment process to the output signal of the A / D conversion circuit 5. Then, color correction processing is added, and an interlaced scanning video signal is output.

When readout from the image sensor 2 is performed by all-pixel readout, an interlaced scanning video signal is generated by performing scanning line conversion on the readout imaging signal. When reading from the image sensor 2 is performed by two-line mixed reading, an interlaced scanning video signal can be obtained without performing the above-described scanning line conversion.
The digital signal processing circuit 6 also supplies an average level and noise level of the signal amplitude to the control circuit 13.

  The pixel addition circuit 7 adds predetermined peripheral pixels to each of the luminance signal, the RY color difference signal, and the BY color difference signal output from the digital signal processing circuit 6.

  The composite video signal generation circuit 8 generates a color subcarrier modulation color signal based on the RY color difference signal Cr and the BY color difference signal Cb output from the pixel addition circuit 7 and outputs the color subcarrier modulation color signal. A composite video signal is generated by superimposing the composite sync signal output from the sync signal generation circuit 12 and the color subcarrier modulation color signal on the luminance signal Y.

  The D / A conversion circuit 9 converts the output signal of the composite video signal generation circuit 8 into an analog signal. This analog signal is an NTSC television signal and is output via the output terminal 14.

  The digital signal processing circuit 6 further calculates an average level and noise level of the signal amplitude for each vertical scanning period, and supplies them to the control circuit 13.

  The calculated value ASA of the average level of the signal amplitude is obtained by dividing the sum of the pixel values of all effective pixels by the total number of effective pixels. Such calculation of the average level is executed by, for example, integration processing and division processing. The “calculated value” of the average level of the signal amplitude obtained as described above may be referred to as “detected value” of the average level of the signal amplitude.

  The calculated noise level ANL is obtained by extracting noise components by noise reduction processing, summing up absolute values of noise components in the entire effective pixel range, and dividing the sum by the total number of effective pixels. The noise reduction process outputs a noise reduction signal NRS in which the noise of the input signal is reduced. A noise component can be extracted by subtracting the noise reduction signal NRS from the input signal. The “calculated value” of the noise level obtained as described above may be referred to as “detected value”.

  Note that the division by the total number of effective pixels in the above-mentioned signal amplitude average level calculation and noise level calculation is realized by bit shift processing of a digital value when the number of pixels is given by 2 to the nth power (n is an integer). You may do it. Further, since the total number of effective pixels is a constant in the same system, division of the total number of effective pixels may be omitted.

  In the above example, the calculation of the average level of the signal amplitude and the calculation of the noise level are described as being performed every vertical scanning cycle. However, from the signal processing time in the digital signal processing circuit 6 and the digital signal processing circuit 6, In consideration of the transmission time to the control circuit 13, it may be performed only once every several vertical scans.

  The synchronization signal generation circuit 12 generates a vertical synchronization signal and a horizontal synchronization signal and supplies them to the digital signal processing circuit 6 and the timing generation circuit 11. Further, a vertical synchronizing signal (delayed vertical synchronizing signal) and a horizontal synchronizing signal (delayed horizontal synchronizing signal) having a timing delayed from the vertical synchronizing signal and the horizontal synchronizing signal by a predetermined time are generated and supplied to the composite video signal generating circuit 8.

  The timing generation circuit 11 generates a drive timing signal DRT for the solid-state imaging device 2 and supplies it to the drive circuit 10. The drive circuit 10 generates a drive signal DRS for the solid-state imaging device 2 based on the drive timing signal DRT output from the timing generation circuit 11. The solid-state imaging device 2 performs photoelectric conversion and charge transfer based on the drive signal DRS output from the drive circuit 10.

  Based on the magnitude of the image pickup signal, the control circuit 13 generates the control of the aperture of the lens 1 and the timing generation circuit 11 based on, for example, the detection value ASA of the average level of the signal amplitude supplied from the digital signal processing circuit 6. Control of charge readout timing and charge forced discharge timing from the photoelectric conversion element of the solid-state image pickup device 2 to be performed (accordingly, control of exposure time), control of amplification gain of the programmable gain amplification circuit 4, and pixel addition processing of the pixel addition circuit 7 Control.

Next, the detailed operation of the pixel addition circuit 7 will be described with reference to FIG. The digital signal processing circuit 6 outputs a luminance signal Y, an RY color difference signal Cr, and a BY color difference signal Cb.
The pixel addition circuit 7 performs processing on each of the luminance signal Y, the RY color difference signal Cr, and the BY color difference signal Cb. Since the processing is the same, the luminance signal Y will be described as a representative, and the RY color difference will be described. A description of the processing for the signals Cr and BY color difference signal Cb is omitted. Actually, there is a configuration in which luminance signal Y, RY color difference signal Cr, and BY color difference signal Cb are processed as pixel point sequential serial signals, and luminance signal Y, RY color difference signal Cr, BY There is also a parallel configuration in which a dedicated pixel addition circuit is provided for each color difference signal Cb. The same effect can be obtained with either configuration.

  The luminance signal Y output from the digital signal processing circuit 6 is applied to the input terminal 701 and supplied to the pixel extraction circuit 71. As will be described in detail later with reference to FIG. 3 and FIG. 4, the pixel extraction circuit 71 is positioned in the direction directly above the screen of the signal to be processed through the pixel of interest P22 and the previous field of the pixel of interest P22. The signal of the reference pixel P11, the signal of the reference pixel P13 located in the direction directly below the screen one field before the target pixel P22, and the signal of the reference pixel P31 located in the direction right above the screen one field after the target pixel P22 And a signal of the reference pixel P33 located in the direction directly below the screen after one field of the target pixel P22 is extracted. The 263 line delay circuit 702, the 1 line delay circuit 703, and the 525 line delay circuit 704 526 line delay circuit 705. In the following, symbols (“P22”, “P33”, etc.) representing each pixel are also used to represent the signal of the pixel.

  The luminance signal Y applied to the input terminal 701 is output from the pixel extraction circuit 71 as it is as a signal of the reference pixel P33 located in the direction directly below the screen after one field. The luminance signal Y applied to the input terminal 701 is sometimes called a “current signal” or a “current pixel signal”. The 263 line delay circuit 702 outputs a 263 line delay signal obtained by delaying the luminance signal Y (the signal of the current pixel P33) by 263 lines (one field) as a signal of the target pixel P22. The 1-line delay circuit 703 applies a 1-line delay signal obtained by delaying the signal (current signal) of the current pixel P33 by 1 line to the reference pixel P31 that is positioned directly above the screen one field after the target pixel P22. Output as a signal. The 525 line delay circuit 704 generates a 525 line delay signal obtained by delaying the signal of the current pixel P33 by 525 lines (2 fields), and a signal of the reference pixel P13 located in the direction immediately below the screen of the target pixel P22 one field before. Output as. The 526 line delay circuit 705 refers to a 526 line delay signal obtained by delaying the signal of the current pixel P33 by 526 lines (2 fields and 1 line) and positioned in the direction directly above the screen of the pixel of interest P22 one field before. Output as a signal of the pixel P11.

  The first adder circuit 706 outputs the signal of the current pixel P33 output from the pixel extraction circuit 71, the signal of the reference pixel P31 located in the direction directly above the screen one field after the target pixel P22, and the target pixel P22. The signal of the reference pixel P13 positioned in the direction immediately below the screen one field before and the signal of the reference pixel P11 positioned in the direction immediately above the screen of the target pixel P22 are added to output a four-pixel addition signal Psum. .

  The switching circuit 707 is connected to the subsequent stage of the 4-pixel addition signal Psum output from the first addition circuit 706, that is, whether or not to supply the 4-pixel addition signal Psum to the second addition circuit 708. Switching is performed based on the addition control signal CSW from the control circuit 13 applied to 710. When the addition control signal CSW is involuntary (first value, for example, “0”), a signal representing “0” is the output signal Psw of the switching circuit 707. When the addition control signal CSW is significant (second value, for example, “1”), the switching circuit 707 outputs a 4-pixel addition signal Psum.

  The second addition circuit 708 adds the signal of the target pixel P22 from the pixel extraction circuit 71 and the output signal Psw of the switching circuit 707. The output terminal 709 outputs the output signal PO of the second addition circuit 708. When the addition control signal CSW is unexpected, the signal of the target pixel P22 is output as it is as the output signal PO. When the addition control signal CSW is significant, a 5-pixel addition signal obtained by adding the signal of the target pixel P22 and the 4-pixel addition signal Psum is output as the output signal PO.

  The temporal and spatial positional relationship of the signal output from the pixel extraction circuit 71 will be described with reference to FIG. FIG. 3 is a pixel arrangement diagram of an interlaced scanning video signal having a vertical axis V in the vertical direction and a time axis T in the horizontal direction. A field (eg, odd field) of the first frame is 1A, B field (eg, even field) of the first frame is 1B, A field of the second frame is 2A, B field of the second frame is 2B, 3 frames The A field of the eye is denoted as 3A. The A field screen is indicated by a solid line, and the B field screen is indicated by a broken line. In the figure, the field period is 1/60 seconds and the frame period is 1/30 seconds.

  When the pixel of the current signal applied to the input terminal 701 is the position indicated by reference numeral P33 (the pixel position is expressed by the same reference numeral as the pixel), the one-line delay signal output from the one-line delay circuit 703 The pixel of the 263 line delay signal output from the 263 line delay circuit 702 is located at the position indicated by reference numeral P31, and the pixel of the 525 line delay signal output from the 525 line delay circuit 704 is indicated at the position indicated by reference numeral P22. The pixel of the 526 line delay signal output from the 526 line delay circuit 705 is at the position indicated by reference numeral P11 at the position indicated by reference numeral P13.

  The above-mentioned 263 line delay signal located at the pixel position P22 is set as the target pixel, and the peripheral pixels P11, P13, P31, and P33 positioned closest to the target pixel are set as reference pixels to be added to the target pixel. The reference pixel P11 is positioned directly above the screen one field before the target pixel P22, the reference pixel P13 is positioned right below the screen one field before the target pixel P22, and the reference pixel 31 is the target pixel P22. The reference pixel P33 is located directly below the screen one field after the target pixel P22.

  With reference to FIG. 4, the spatial positional relationship of the signals added by the pixel addition circuit 7 will be further described. FIG. 4 is a pixel arrangement diagram of an interlaced scanning video signal having a vertical axis V in the vertical direction and a horizontal axis H in the horizontal direction. The line 1 to the middle of the line 263 corresponds to the A field (odd field) scan line, and the line 263 to the line 525 corresponds to the B field (even field) scan line. A solid line represents the A field scanning line, and a broken line represents the B field scanning line. When the pixel of the current signal applied to the input terminal 701 is set to the position indicated by reference numeral P33, the pixel of the one-line delay signal output from the one-line delay circuit 703 is set to the position indicated by reference numeral P31. The pixel of the 263 line delay signal output from the 525 line delay circuit 705 is output from the 526 line delay circuit 705 to the position indicated by reference numeral P22 and the pixel of the 525 line delay signal output from the 525 line delay circuit 704 is output to the position indicated by reference numeral P13. The pixel of the 526 line delayed signal is at the position indicated by reference numeral P11.

The output signal PO of the pixel addition circuit 7 is obtained when the addition control signal CSW is not
PO = P22
When the addition control signal CSW is significant,
PO = P11 + P13 + P22 + P31 + P33
It is. (Here, P11, P13, P22, P31, and P33 represent pixel values of the pixels P11, P13, P22, P31, and P33, respectively.)

  The above-described operation of the pixel addition circuit 7 includes the first addition result obtained by adding the pixel values P11, P13, P22, P31, and P33 at the addition ratio 0: 0: 1: 0: 0, and the pixel values P11, P13, and P22. , P31, P33 can be switched and output with the second addition result obtained by adding the addition ratios 1: 1: 1: 1: 1. By performing such switching, as described in detail below, sensitivity control by the pixel addition circuit can also be controlled as part of exposure control, so even if the illuminance environment changes, the subject can always be viewed under optimal conditions. is there. It can also be said that the pixel addition circuit 7 constitutes means for adjusting the signal amplitude by changing the number of pixels to be added.

  As shown in the spatial pixel arrangement of FIGS. 3 and 4, the peripheral pixels (P11, P13, P31, and P33) that are closest to the target pixel P22 are used, and the sensitivity is improved five times. For example, when two pixels are added, the signal component is doubled, the noise component is square root doubled, and a relatively pure signal component is increased. In addition, since the pixels located in the vicinity have a high correlation as a property of the image, highly effective sensitivity improvement is realized by adding five pixels closest to the target pixel.

  The effect of the present invention will be described in comparison with pixel addition using pixels in the same field. In the present invention, pixels adjacent in the horizontal direction in the same field are not added, and deterioration in horizontal resolution does not occur. The spatially adjacent pixels in the horizontal direction are not added, and the horizontal resolution is not deteriorated. In the present invention, pixels adjacent in the vertical direction in the same field are not added, but pixels at positions shifted spatially in the vertical direction are added. Spatial pixels shifted in the vertical direction are added, but only 2 pixels can be added between adjacent scanning lines for pixels in the same field, but 3 pixels with the same inter-pixel distance in the same frame. Can be added. If the inter-pixel distance used for the addition operation is the same, the resolution will be the same. When two pixels are added to adjacent scanning lines in the vertical direction in the same field, the vertical resolution is reduced to ½, but the sensitivity is improved only twice. However, in the present invention, in the same frame (2 fields), the vertical resolution is reduced to ½, but the sensitivity can be improved three times. Furthermore, the sensitivity can be improved by a factor of five by expanding the object of the addition operation to the field opposite to the target pixel.

  In addition, in order to improve the sensitivity by a factor of 5 by adding the pixels in the same field, it is necessary to add the pixels located above and below in the vertical direction and the pixels located on the left and right in the horizontal direction around the target pixel. That is, in FIG. 4, it is necessary to add the signals of the pixels indicated by the symbols T22, L22, R22, and B22 to the signal of the pixel P22, respectively. As described above, when the sensitivity is increased 5 times by pixel addition in the same field, the vertical resolution deteriorates to 1/4 and the horizontal resolution also deteriorates to 1/2. On the other hand, in the present invention, the vertical resolution is reduced to ½, but the horizontal resolution is not deteriorated, and the sensitivity can be improved five times.

  The effect of the present invention will be described in comparison with long-time exposure. If the sensitivity is improved by a factor of 5 with long exposure, the 1/60 second dynamic resolution deteriorates to 5/60 second dynamic resolution, and at the same time, the field image becomes a vertical resolution. In the present invention, when the sensitivity is increased 5 times, the dynamic resolution of 1/60 seconds deteriorates to the dynamic resolution of 3/60 seconds, and the vertical resolution only deteriorates to 1/2.

  When using an image sensor that supports interlaced scanning to improve sensitivity by long exposure, the vertical resolution is always degraded by half because only the number of transfer stages corresponding to the number of pixels in the vertical direction of the field image is provided. Was.

  If the vertical resolution ½ degradation in the sensitivity enhancement mode at low illuminance is common, when the sensitivity is increased 5 times, the long-time exposure degrades the 1/60 second dynamic resolution to the 5/60 second dynamic resolution. However, in the present invention, the dynamic resolution of 1/60 seconds is limited to the deterioration of the dynamic resolution of 3/60 seconds.

  The present invention performs pixel addition using a highly correlated pixel closest to the pixel of interest based on the spatial arrangement of the pixels used for the addition operation of FIGS. 3 and 4, thus realizing improved sensitivity while minimizing image resolution degradation. can do.

  The control circuit 13 performs automatic exposure control so that the detection value ASA of the average level of the signal amplitude obtained from the digital signal processing circuit 6 is constant. When the signal amplitude is large in imaging in a bright environment, the control circuit 13 performs control to reduce the aperture of the lens 1 to reduce the amount of light incident on the solid-state image sensor 2 or to the photoelectric conversion element of the solid-state image sensor 2. The exposure time is reduced by controlling to forcibly discharge the accumulated charge.

  When the signal amplitude becomes smaller due to imaging in a dark environment, the control circuit 13 controls the programmable gain amplifier circuit 4 to increase the amplification gain and amplifies the imaging signal. However, when the amplification gain is too large, noise becomes conspicuous and an image with poor visibility is obtained. As another method, the control circuit 13 can extend the exposure time by controlling the charge readout from the photoelectric conversion element of the solid-state imaging device 2 to be thinned out in units of vertical scanning periods. However, if the exposure time is too long, the moving subject becomes an afterimage, resulting in an image with poor visibility. Further, an interpolation circuit for missing images in units of vertical scanning periods is required.

The control circuit 13 of the present embodiment controls the output control signal CSW to the pixel addition circuit 7 to be set significantly and to output a signal obtained by adding five pixels.
As shown in FIG. 3, by adding the five pixels located closest to the target pixel, it is possible to realize a five-fold improvement in sensitivity and to greatly improve the visibility even in an extremely dark environment. Further, there is no deterioration in horizontal resolution, and deterioration in vertical resolution and dynamic resolution can be minimized.

  When the control circuit 13 switches the addition control signal CSW from involuntary to significant and controls the pixel addition circuit 7 to add 5 pixels, the brightness of the output signal output from the output terminal 14 changes suddenly, and the screen is changed. In order to prevent the viewer from feeling uncomfortable or difficult to see, other signal amplitude adjusting means is used to control the overall sensitivity so as not to change significantly.

Hereinafter, an example of a procedure for adjusting sensitivity when the ambient illuminance changes will be described.
When the ambient illuminance gradually decreases and the detection value ASA of the average level of the signal amplitude decreases, the aperture of the lens 1 is controlled in the open direction to maintain the average level of the signal amplitude. Here, “maintaining the average level of the signal amplitude” means maintaining the average level of the signal amplitude of the output of the digital signal processing circuit 6 or the average level of the signal amplitude of the output of the pixel addition circuit 7. . As long as the number of pixels added in the pixel addition circuit 7 does not change, if the average level of the signal amplitude output from the digital signal processing circuit 6 is maintained at a constant value, the average level of the signal amplitude output from the pixel addition circuit 7 is also increased. It is maintained at a constant value.

  After the aperture of the lens 1 is opened (fully opened), control is performed so as to increase the amplification gain of the programmable gain amplifier circuit 4, and the average level of the signal amplitude is maintained. After the amplification gain of the programmable gain amplifier circuit 4 is greater than five times and greater than a predetermined upper limit value UGL of the amplification gain, the pixel addition circuit 7 is controlled to add five pixels, and at the same time, programmable gain amplification Control is performed so that the amplification gain of the circuit 4 is reduced to 1/5 of the immediately preceding set gain to maintain the average level of the signal amplitude (the average level of the signal amplitude of the output PO of the pixel addition circuit 7). When the ambient illuminance further decreases, control is performed so as to increase the amplification gain of the programmable gain amplifier circuit 4, and the average level of the signal amplitude is maintained.

  When the ambient illuminance gradually increases and the detected value ASA of the average level of the signal amplitude increases, control is performed so as to reduce the amplification gain of the programmable gain amplifier circuit 4, and the average level of the signal amplitude is maintained. After the amplification gain of the programmable gain amplification circuit 4 decreases and becomes smaller than the predetermined lower limit value LGL, the pixel addition circuit 7 is controlled so as not to add five pixels, and at the same time, the amplification gain of the programmable gain amplification circuit 4 Is controlled to increase to 5 times the set gain just before, and the average level of the signal amplitude (the average level of the signal amplitude of the output PO of the pixel addition circuit 7) is maintained. When the ambient illuminance further increases, control is performed so as to reduce the amplification gain of the programmable gain amplifier circuit 4, and the average level of the signal amplitude is maintained. When the ambient illuminance further increases, the aperture of the lens 1 is controlled in the light shielding direction to maintain the average level of signal amplitude.

  The predetermined upper limit value UGL of the amplification gain is determined based on a noise level detection value ANL supplied from the digital signal processing circuit 6 to the control circuit 13. (Considering that it is necessary to increase the amplification gain when the ambient illuminance decreases and the S / N of the output of the image pickup device 2 decreases accordingly) The noise level detection value ANL is the average level of the signal amplitude. The amplification gain of the programmable gain amplifier circuit 4 when the predetermined noise ratio (first predetermined noise ratio) NPR1 exceeds the detection value ASA is set to the predetermined upper limit value UGL. The first predetermined noise ratio NPR1 is set to 1/50, for example.

  Since the allowable noise level for visual recognition of the subject varies depending on the application, the first predetermined noise ratio NPR1 varies depending on the application of the imaging apparatus, such as whether S / N is important or image resolution is important. The control circuit 13 dynamically observes the gain set in the programmable gain amplifying circuit 4 and the detected value ANL of the noise level supplied from the digital signal processing circuit 6 to the control circuit 13, and dynamically increases a predetermined upper limit of the amplification gain. The programmable gain amplifier circuit 4 and the pixel addition circuit 7 are controlled by determining the value UGL. Alternatively, before the imaging apparatus is shipped from the factory, an amplification gain in which the detection value ANL of the noise level exceeds the first predetermined noise ratio with respect to the detection value ASA of the average level of the signal amplitude is measured. The upper limit value UGL is written to a storage element 16 (nonvolatile memory, volatile memory backed up by a battery, etc.) that can retain the stored contents even when the power of the imaging apparatus is turned off, and the control circuit 13 determines the predetermined amplification gain. The programmable gain amplifier circuit 4 and the pixel addition circuit 7 may be controlled with reference to the upper limit value UGL.

  The predetermined lower limit value LGL of the amplification gain is determined based on a noise level detection value ANL supplied from the digital signal processing circuit 6 to the control circuit 13. The amplification gain of the programmable gain amplifying circuit 4 when the detection value ANL of the noise level falls below a predetermined noise ratio (second predetermined noise ratio) NPR2 with respect to the detection value ASA of the average level of the signal amplitude is the predetermined gain. The lower limit is LGL. The second predetermined noise ratio is determined based on the first predetermined noise ratio NPR1 and the number of added pixels in the pixel adding circuit 7. For example, the second predetermined noise ratio NPR2 is defined as 1/250 (= {(1/50) × (1/5)}).

  Since the allowable noise level for visual recognition of the subject differs depending on the application, the second predetermined noise ratio NPR2 varies depending on the application of the imaging device, such as whether S / N is important or image resolution is important. The control circuit 13 dynamically observes the gain set in the programmable gain amplifier circuit 4 and the detected value ANL of the noise level supplied from the digital signal processing circuit 6 to the control circuit 13, and dynamically lowers the predetermined lower limit of the amplification gain. The programmable gain amplification circuit 4 and the pixel addition circuit 7 are controlled by determining the value LGL. Alternatively, before the imaging apparatus is shipped from the factory, an amplification gain in which the noise level detection value ANL exceeds the second predetermined noise ratio NPR2 with respect to the detection level ASA of the average level of the signal amplitude is measured, and the predetermined lower limit The value LGL is written in the storage element 16 that can retain the stored contents even when the power of the imaging apparatus is turned off. The control circuit 13 refers to the predetermined lower limit value LGL of the amplification gain, and sets the programmable gain amplification circuit 4 and the pixel addition circuit 7 You may make it control.

  The control circuit 13 controls the signal amplitude adjustment function of each of the aperture of the lens 1, the exposure time of the solid-state imaging device 2, the amplification gain of the programmable gain amplification circuit 4, and the pixel addition in the pixel addition circuit 7 to control the average level of the signal amplitude. (The average level of the signal amplitude of the output PO of the pixel addition circuit 7) is maintained. When applying a signal amplitude adjustment function with a large change in signal amplitude, such as pixel addition in the pixel addition circuit 7, other signal amplitude adjustment means are set to cancel each other so that the amplitude does not change suddenly before and after application. By setting the overall gain of all signal amplitude adjustment means to be the same before and after application, the brightness of the output signal will not change suddenly, and the person watching the screen will feel uncomfortable or difficult to see There is no longer to do.

  With reference to FIG. 5, the phase relationship of each signal is demonstrated. The synchronization signal generation circuit 12 supplies the internally generated horizontal synchronization signal HD and vertical synchronization signal VD to the timing generation circuit 11 and the digital signal processing circuit 6. In FIG. 5, the horizontal synchronization signal HD and the vertical synchronization signal VD are collectively referred to as a synchronization signal VDHD.

  The timing generation circuit 11 drives the solid-state imaging device 2 based on the horizontal synchronization signal HD and the vertical synchronization signal VD. The imaging signal output from the solid-state imaging device 2 is synchronized with the horizontal synchronizing signal HD and the vertical synchronizing signal VD, and the luminance signal Y, RY color difference signal Cr, BY color difference output from the digital signal processing circuit 6 is obtained. The signal Cb is also synchronized with the horizontal synchronization signal HD and the vertical synchronization signal VD.

  As the input luminance signal Y of the pixel addition circuit 7, the input synchronization signal VDHD is superimposed with the image information of the Y1 field at the timing of the A field 1A of the first frame, and the Y2 field at the timing of the B field 1B of the first frame. The image information of the Y4 field is superimposed at the timing of the A field 2A of the second frame, the image information of the Y4 field is superimposed at the timing of the B field 2B of the second frame, and the third frame. The image information of the Y5 field is superimposed at the timing of the A field 3A, and the image information of the Y6 field is superimposed at the timing of the B field 3B of the third frame. Note that “first frame”, “second frame”, and the like referred to here represent relative frame relationships for convenience of explanation. In the A field, the phase of the horizontal synchronizing signal HD with respect to the vertical synchronizing signal VD is the same, but in the B field, the phase of the horizontal synchronizing signal HD with respect to the vertical synchronizing signal VD is shifted by 1/2 horizontal scanning cycle. This distinguishes the A field and the B field.

  In the pixel addition circuit 7, the input field luminance signal Y (P33, P31 in FIG. 2) of the current field, the luminance signal of one field before, that is, the one field delayed luminance signal Y1DL (P22 of FIG. 2), and the luminance of two fields before The signal, that is, the two-field delayed luminance signal Y2DL (P13 and P11 in FIG. 2) is added to output an added luminance signal YADD (PO in FIG. 2). The added luminance signal YADD needs to be synchronized in phase with the target pixel P22 located at the center of the added pixel. Therefore, the synchronization signal generation circuit 12 generates a 1-field delay synchronization signal VDHD1DL obtained by delaying the input synchronization signal VDHD by 263 lines and supplies it to the composite video signal generation circuit 8.

  The synchronization signal generation circuit 12 supplies a synchronization signal VDHD1DL delayed by 263 lines from the horizontal synchronization timing and the vertical synchronization timing serving as a reference for the imaging operation to the composite video signal generation circuit 8, so that the synchronization signal generation circuit 12 is positioned at the center of each pixel to be added. When the control circuit 13 switches the addition control signal CSW to the pixel addition circuit 7 from involuntary to significant, or from significant to insignificant, The angle can be prevented from fluctuating, and the sensitivity can be controlled to be five times larger with the same composition of the subject.

  Note that the “field angle fluctuation” here means a shift of 1/2 of the horizontal scanning line interval due to the display of the A field image at the scanning line position of the B field. In FIG. 5, the added luminance signal YADD is generated by adding Y, Y1DL, and Y2DL, and therefore must be displayed as a field signal in which the center field Y1DL is located. By generating the 1-field delay synchronization signal VDH1DL instead of the input synchronization signal VDHD as the synchronization signal corresponding to the added luminance signal YADD, it is possible to prevent the display from being shifted by a half of the horizontal scanning line interval.

  In the above example, whether or not the sum of the signals of the four reference pixels is to be added is selected. However, by adding a weight to the sum of the signals of the four reference pixels, the sum is added at a predetermined rate. It's also good.

Embodiment 2. FIG.
A block configuration showing an imaging apparatus according to the second embodiment of the present invention is shown in FIG. 1 as in the first embodiment. The operation of each circuit excluding the pixel adder circuit 7 and the control circuit 13 is the same as that described in the first embodiment and provides the same effect, so the description thereof is omitted.

  As the pixel addition circuit 7, the one shown in FIG. 6 is used instead of the one shown in FIG. The pixel addition circuit 7 shown in FIG. 6 is generally the same as the pixel addition circuit shown in FIG. 2, but differs in the following points. That is, a selective addition circuit 712 and a rank determination circuit 711 are provided instead of the addition circuit 706 and the switching circuit 707 in FIG.

  The luminance signal Y applied from the digital signal processing circuit 6 to the input terminal 701 of the pixel addition circuit 7 is 263 line delay circuit 702 of the pixel extraction circuit 71, 1 line delay circuit 703, 525 line delay circuit 704, and 526 line delay. Each is input to the circuit 705. Delay circuits 702, 703, 704, 705 operate in the same manner as described with respect to FIG.

  The order determination circuit 711 includes the luminance signal P33 applied to the input terminal 701, the one-line delay signal P31 output from the one-line delay circuit 703, and the 525-line delay signal output from the 525-line delay circuit 704. Pixels of four pixels P33, P31, P13, and P11 are received by P13, the 526 line delay signal P11 output from the 526 line delay circuit 705, and the 263 line delay signal P22 output from the 263 line delay circuit 702. Each value is compared with the pixel value of the pixel P22 and ranked in the order of magnitude, and information indicating the rank is supplied to the selection and addition circuit 712.

An example of order determination by the order determination circuit 711 will be described. First, an absolute value of a difference value of each pixel value of other pixels with respect to the pixel value of the pixel P22 is obtained. The absolute value is represented by the following formula.
dP33 = | P22−P33 |
dP31 = | P22−P31 |
dP13 = | P22−P13 |
dP11 = | P22−P11 |
Next, the magnitudes of the difference values between the pixels and the pixel P22 are compared with each other and arranged in order of increasing difference values. The order determination circuit 711 assigns an order to the pixels P33, P31, P13, and P11 in ascending order of the obtained difference values, and notifies the selection / addition circuit 712 of the order (priority order).

  The selective addition circuit 712 includes the luminance signal P33 applied to the input terminal 701, the one-line delay signal P31 output from the one-line delay circuit 703, and the 525-line delay signal output from the 525-line delay circuit 704. P13 and the 526 line delay signal P11 output from the 526 line delay circuit 705 are added control for designating information indicating the priority order notified from the order determining circuit 711 and the number of added pixels applied to the control terminal 710. The pixel values are added while being selected based on the signal CSW and supplied to the adding circuit 708.

Based on the detected value ASA of the average level of the signal amplitude supplied from the digital signal processing circuit 6, the control circuit 13 controls the amplification gain of the amplification circuit 4 and the diaphragm of the lens 1 as will be described later. The number of added pixels is determined, and an addition control signal CSW that specifies the number of added pixels is generated.
When the addition control signal CSW from the control circuit 13 applied to the control terminal 710 instructs to add one pixel, the selective addition circuit 712 outputs “0”.

When the addition control signal CSW indicates the addition of two pixels, the selective addition circuit 712 outputs the pixel value of the first priority pixel determined by the priority determination circuit 711.
When the addition control signal CSW indicates the addition of three pixels, the selective addition circuit 712 determines the pixel value of the first priority pixel and the pixel value of the second priority pixel determined by the priority determination circuit 711. 2 pixel addition value obtained by adding is output.

When the addition control signal CSW indicates 4-pixel addition, the selective addition circuit 712 determines the pixel value of the first priority pixel and the pixel value of the second priority pixel determined by the priority determination circuit 711. A three-pixel addition value obtained by adding the pixel value of the pixel having the third priority is output.
When the addition control signal CSW indicates the addition of five pixels, the selective addition circuit 712 determines the pixel value of the first priority pixel and the pixel value of the second priority pixel determined by the priority determination circuit 711. The pixel value of the pixel with the priority number 3 and the pixel value of the pixel with the priority number 4 are added, that is, all four input pixel values are added to output a 4-pixel added value.

  As described above, the selective addition circuit 712 adds the pixel values of the number (n−1) of pixels obtained by subtracting 1 from the number of pixels to be added (n) indicated by the addition control signal CSW in accordance with the priority order. Which pixel is used for addition depends on the priority order. That is, pixels with a priority order of 1 to a priority order of (n-1) are used for addition.

  The 263 line delay circuit 702 outputs a 263 line delay signal P22 obtained by delaying the luminance signal P33 by 263 lines. The adder circuit 708 adds the 263 line delay signal P22 output from the 263 line delay circuit 702 and the output signal of the selective adder circuit 712. The output terminal 709 outputs the output signal PO of the adder circuit 708.

  As a result of the above processing, when the addition control signal CSW indicates “one pixel addition”, the 263 line delay signal P22 is output as it is. When the addition control signal CSW indicates “two-pixel addition”, a two-pixel addition signal including the target pixel P22 is output. When the addition control signal CSW indicates “3-pixel addition”, a 3-pixel addition signal including the target pixel P22 is output. When the addition control signal CSW indicates “4-pixel addition”, a 4-pixel addition signal including the target pixel P22 is output. When the addition control signal CSW indicates “5-pixel addition”, a 5-pixel addition signal including the target pixel P22 is output.

  The operations of the second adder circuit 708, the order determining circuit 711, and the selective adder circuit 712 in FIG. 6 may be realized by another configuration (an integrally configured circuit). In this case, the pixel value having the smallest difference value among the difference values dP33, dP31, dP13, and dP11 of the respective pixel values with respect to the pixel value of the target pixel P22 obtained by the same process as described with respect to the rank determination circuit 711. PN1, the pixel value of the second smallest difference value is PN2, the pixel value of the third smallest difference value is PN3, and the pixel value of the fourth smallest difference value is PN4.

The output signal PO of the pixel addition circuit 7 is obtained when the addition control signal CSW indicates “one pixel addition”.
PO = P22
And when the addition control signal CSW indicates “two pixel addition”,
PO = P22 + PN1
And when the addition control signal CSW indicates “3 pixel addition”,
PO = P22 + PN1 + PN2
And when the addition control signal CSW indicates “4 pixel addition”,
PO = P22 + PN1 + PN2 + PN3
When the addition control signal CSW indicates “5 pixel addition”,
PO = P22 + PN1 + PN2 + PN3 + PN4
It is.

  Depending on the amount of change in the vertical direction of the subject, the change position, the amount of change in the time direction of the subject, and the change timing, the degree of correlation of the surrounding four pixels with respect to the pixel of interest P22 changes. In the case of an image in which the ratio of the noise component to the signal component is small, a pixel having a pixel value close to the target pixel P22 can be determined as a highly correlated pixel. In the present embodiment, by utilizing this feature, peripheral pixels having a higher correlation with the target pixel are selected and added, and thereby, an improvement in sensitivity with little reduction in resolution can be realized.

  When peripheral pixels with higher correlation are extracted by performing motion detection or horizontal / vertical correlation determination, there is a risk that erroneous detection due to noise occurs and the image is uncomfortable. If correlation determination with high accuracy that does not give a sense of incongruity to an image is performed, there is a problem that the circuit scale increases and the product price increases and the power consumption increases. In the present embodiment, the four pixels located above and below the target pixel in the preceding and following fields are preferentially added, so that such a problem can be solved. .

  The control circuit 13 performs automatic exposure control so that the average level ASA of the signal amplitude obtained from the digital signal processing circuit 6 is constant. When the signal amplitude is large in imaging in a bright environment, the control circuit 13 performs control to reduce the aperture of the lens 1 to reduce the amount of light incident on the solid-state image sensor 2 or to the photoelectric conversion element of the solid-state image sensor 2. The exposure time is reduced by controlling to forcibly discharge the accumulated charge.

  When the signal amplitude becomes smaller due to imaging in a dark environment, the control circuit 13 controls the programmable gain amplifier circuit 4 to increase the amplification gain and amplifies the imaging signal. However, when the amplification gain is too large, noise becomes conspicuous and an image with poor visibility is obtained. As another method, the control circuit 13 extends the exposure time by controlling the charge readout from the photoelectric conversion element of the solid-state imaging device 2 to be thinned out in units of vertical scanning periods. However, if the exposure time is too long, the moving subject becomes an afterimage, resulting in an image with poor visibility. Furthermore, there is a problem that an interpolation circuit for missing images is required in units of vertical scanning periods.

The control circuit 13 of the present embodiment designates the number of added pixels represented by the addition control signal CSW to the pixel adder circuit 7 and controls to output a signal obtained by adding the designated number of pixels.
As shown in FIG. 3, by selectively adding the five pixels located closest to the target pixel, the sensitivity can be improved up to 5 times, and the visibility can be greatly improved even in imaging in an extremely dark environment. Further, there is no deterioration in horizontal resolution, and deterioration in vertical resolution and dynamic resolution can be minimized.

  When the control circuit 13 switches the number of added pixels specified by the addition control signal CSW in the range of 1 to 5 and controls the pixel adding circuit 7 to change the number of added pixels, it is output from the output terminal 14. Control is performed so that the overall sensitivity does not change drastically by using other signal amplitude adjusting means so that the brightness of the output signal does not change suddenly and the person watching the screen feels uncomfortable or difficult to see.

Hereinafter, an example of a procedure for adjusting sensitivity when the ambient illuminance changes will be described.
When the ambient illuminance gradually decreases and the detection value ASA of the average level of the signal amplitude decreases, the aperture of the lens 1 is controlled in the open direction to maintain the average level of the signal amplitude.
After the aperture of the lens 1 is opened (fully opened), control is performed to increase the amplification gain of the programmable gain amplifier circuit 4, and the average level of the signal amplitude is maintained. After the amplification gain of the programmable gain amplifier circuit 4 reaches a predetermined upper limit value UGL, the number of added pixels of the pixel adder circuit 7 is controlled to increase from one pixel to two pixels, and at the same time, the amplification of the programmable gain amplifier circuit 4 The gain is controlled to be reduced to ½ of the immediately preceding set gain to maintain the average level of the signal amplitude (the average level of the signal amplitude of the output PO of the pixel addition circuit 7).

  Further, when the ambient illuminance gradually decreases and the detection value ASA of the average level of the signal amplitude decreases, control is performed to increase the amplification gain of the programmable gain amplifier circuit 4, and the average level of the signal amplitude is maintained. After the amplification gain of the programmable gain amplifier circuit 4 reaches the predetermined upper limit value UGL, the number of added pixels of the pixel adder circuit 7 is controlled to increase from two pixels to three pixels, and at the same time, the amplification of the programmable gain amplifier circuit 4 The gain is controlled to be reduced to 2/3 of the previous set gain to maintain the average level of the signal amplitude (the average level of the signal amplitude of the output PO of the pixel addition circuit 7).

  Further, when the ambient illuminance gradually decreases and the detection value ASA of the average level of the signal amplitude decreases, control is performed to increase the amplification gain of the programmable gain amplifier circuit 4, and the average level of the signal amplitude is maintained. After the amplification gain of the programmable gain amplifier circuit 4 reaches the predetermined upper limit value UGL, the number of added pixels of the pixel adder circuit 7 is controlled to be increased from 3 pixels to 4 pixels, and simultaneously the amplification of the programmable gain amplifier circuit 4 is performed. The gain is controlled to be reduced to 3/4 of the immediately preceding set gain to maintain the average level of the signal amplitude (the average level of the signal amplitude of the output PO of the pixel addition circuit 7).

  Further, when the ambient illuminance gradually decreases and the detection value ASA of the average level of the signal amplitude decreases, control is performed to increase the amplification gain of the programmable gain amplifier circuit 4, and the average level of the signal amplitude is maintained. After the amplification gain of the programmable gain amplifier circuit 4 reaches the predetermined upper limit value UGL, the number of added pixels of the pixel adder circuit 7 is controlled to be increased from 4 pixels to 5 pixels, and simultaneously the amplification of the programmable gain amplifier circuit 4 is performed. The gain is controlled to be reduced to 4/5 of the previous set gain to maintain the average level of the signal amplitude (the average level of the signal amplitude of the output PO of the pixel addition circuit 7).

  Further, when the ambient illuminance gradually decreases and the detection value ASA of the average level of the signal amplitude decreases, control is performed to increase the amplification gain of the programmable gain amplifier circuit 4, and the average level of the signal amplitude is maintained.

  When the control circuit 13 switches the number of added pixels in the pixel adding circuit 7 in a stepwise manner, the vertical resolution and dynamic resolution of the output signal output from the output terminal 14 do not change suddenly, and a person watching the screen You don't feel uncomfortable or feel uncomfortable.

  The control circuit 13 switches the number of pixels to be added in the pixel addition circuit 7 in a stepwise manner, whereby the amount of change in the amplification gain in the control of the programmable gain amplifier circuit 4 can be reduced, and the output signal output from the output terminal 14 The S / N does not change abruptly, and the person watching the screen does not feel uncomfortable or feel uncomfortable.

The predetermined upper limit value UGL of the amplification gain is determined based on a noise level detection value ANL supplied from the digital signal processing circuit 6 to the control circuit 13.
The amplification gain of the programmable gain amplifier circuit 4 when the detection value ANL of the noise level exceeds a predetermined noise ratio (first predetermined noise ratio) NPR1 with respect to the detection value ASA of the average level of the signal amplitude is the predetermined upper limit. Let it be the value UGL. The first predetermined noise ratio NPR1 is set to 1/50, for example.

  Since the allowable noise level for visual recognition of the subject varies depending on the application, the first predetermined noise ratio NPR1 varies depending on the application of the imaging apparatus, such as whether S / N is important or image resolution is important. The control circuit 13 dynamically observes the gain set in the programmable gain amplifying circuit 4 and the detected value ANL of the noise level supplied from the digital signal processing circuit 6 to the control circuit 13, and dynamically increases a predetermined upper limit of the amplification gain. The programmable gain amplifier circuit 4 and the pixel addition circuit 7 are controlled by determining the value UGL. Alternatively, before the image pickup apparatus is shipped from the factory, an amplification gain in which the noise level detection value ANL exceeds the first predetermined noise ratio NPR1 with respect to the detection value ASA of the average level of the signal amplitude is measured. The predetermined upper limit value UGL is written in the storage element 16 that can retain the stored contents even when the power of the imaging apparatus is turned off. The control circuit 13 refers to the predetermined upper limit value UGL of the amplification gain and adds the pixel to the programmable gain amplifier circuit 4 The circuit 7 may be controlled.

  When the ambient illuminance gradually increases and the detected value ASA of the average level of the signal amplitude increases, control is performed so as to reduce the amplification gain of the programmable gain amplifier circuit 4, and the average level of the signal amplitude is maintained. After the amplification gain of the programmable gain amplifier circuit 4 decreases and becomes smaller than the predetermined lower limit value LGL, the pixel addition circuit 7 is controlled to reduce the number of added pixels from 5 pixels to 4 pixels, and at the same time programmable gain amplification Control is performed to increase the amplification gain of the circuit 4 to 5/4 times the set gain just before, and the average level of the signal amplitude (the average level of the signal amplitude of the output PO of the pixel addition circuit 7) is maintained.

  Further, when the ambient illuminance gradually increases and the detection value ASA of the average level of the signal amplitude increases, control is performed so as to reduce the amplification gain of the programmable gain amplifier circuit 4, and the average level of the signal amplitude is maintained. After the amplification gain of the programmable gain amplifier circuit 4 decreases and becomes smaller than the predetermined lower limit value LGL, the pixel addition circuit 7 is controlled to reduce the number of added pixels from 4 pixels to 3 pixels, and at the same time programmable gain amplification Control is performed to increase the amplification gain of the circuit 4 to 4/3 times the set gain just before, and the average level of the signal amplitude (the average level of the signal amplitude of the output PO of the pixel addition circuit 7) is maintained.

  Further, when the ambient illuminance gradually increases and the detection value ASA of the average level of the signal amplitude increases, control is performed so as to reduce the amplification gain of the programmable gain amplifier circuit 4, and the average level of the signal amplitude is maintained. After the amplification gain of the programmable gain amplifier circuit 4 decreases and becomes smaller than the predetermined lower limit value LGL, the pixel addition circuit 7 is controlled to reduce the number of added pixels from 3 pixels to 2 pixels, and at the same time programmable gain amplification Control is performed to increase the amplification gain of the circuit 4 to 3/2 times the previous set gain, and the average level of the signal amplitude (the average level of the signal amplitude of the output PO of the pixel addition circuit 7) is maintained.

  Further, when the ambient illuminance gradually increases and the detection value ASA of the average level of the signal amplitude increases, control is performed so as to reduce the amplification gain of the programmable gain amplifier circuit 4, and the average level of the signal amplitude is maintained. After the amplification gain of the programmable gain amplifier circuit 4 decreases and becomes smaller than the predetermined lower limit value LGL, the pixel addition circuit 7 is controlled to reduce the number of added pixels from 2 pixels to 1 pixel, and at the same time, the programmable gain amplification Control is performed to increase the amplification gain of the circuit 4 to twice the previous set gain to maintain the average level of the signal amplitude (the average level of the signal amplitude of the output PO of the pixel addition circuit 7).

  When the ambient illuminance further increases, control is performed to reduce the amplification gain of the programmable gain amplifier circuit 4, and the average level of the signal amplitude is maintained. When the ambient illuminance further increases, the lens aperture is controlled in the light shielding direction to maintain the average level of signal amplitude.

  As described above, when the number of added pixels changes from M (M is a positive integer) to N (N is a positive integer), the control circuit 13 simultaneously switches the amplification gain of the amplifier circuit to M / N times. Thus, the signal amplitude is prevented from changing abruptly.

The predetermined lower limit value LGL of the amplification gain is determined based on a noise level detection value ANL supplied from the digital signal processing circuit 6 to the control circuit 13.
The amplification gain of the programmable gain amplifying circuit 4 when the detection value ANL of the noise level falls below a predetermined noise ratio (second predetermined noise ratio) NPR2 with respect to the detection value ASA of the average level of the signal amplitude is the predetermined gain. The lower limit is LGL. The second predetermined noise ratio NPR2 is determined based on the first predetermined noise ratio NPR1 and a change in the number of added pixels in the pixel adding circuit 7. For example, when the pixel addition circuit 7 has 5 pixels, the second predetermined noise ratio NPR2 is set to 4/250 (= {(1/50) × (4/5)}), and the noise level is set. Is a predetermined lower limit value LGL when the gain is less than 4/250 (= ((1/50) × (4/5))) of the average level of the signal amplitude. For example, when the pixel addition circuit 7 has 4 pixels, the second predetermined noise ratio NPR2 is set to 3/200 (= {(1/50) × (3/4)}), and the noise level is set. Is set to the predetermined lower limit value LGL when the gain is less than 3/200 (= {(1/50) × (3/4)}) of the average level of the signal amplitude. For example, when the number of added pixels in the pixel adding circuit 7 is 3, The predetermined noise ratio NPR2 of 2 is 2/150 (= {(1/50) × (2/3)}), and the noise level is 2/150 of the average level of the signal amplitude (= {(1/50) × The amplification gain of the programmable gain amplifier circuit 4 when the ratio is less than (2/3)}) is set to the predetermined lower limit value LGL, for example, when the number of added pixels of the pixel adder circuit 7 is 2, The second predetermined noise ratio NPR2 is 1/100 (= {(1/50) × (1/2)}), and the noise level is 1/100 (= {(1/50)) of the average level of the signal amplitude. The amplification gain of the programmable gain amplifier circuit 4 when the ratio is less than (× (1/2)}) is set to the predetermined lower limit value LGL.

  Since the allowable noise level for visual recognition of the subject differs depending on the application, the second predetermined noise ratio NPR2 varies depending on the application of the imaging device, such as whether S / N is important or image resolution is important. The control circuit 13 dynamically observes the gain set in the programmable gain amplifier circuit 4 and the detected value ANL of the noise level supplied from the digital signal processing circuit 6 to the control circuit 13, and dynamically lowers the predetermined lower limit of the amplification gain. The programmable gain amplification circuit 4 and the pixel addition circuit 7 are controlled by determining the value LGL. Alternatively, before the image pickup apparatus is shipped from the factory, an amplification gain in which the noise level detection value ANL exceeds the second predetermined noise ratio NPR2 with respect to the detection value ASA of the average level of the signal amplitude is measured. The predetermined lower limit value LGL is written in the storage element 16 that can retain the stored contents even when the power of the imaging apparatus is turned off, and the control circuit 13 refers to the predetermined lower limit value LGL of the amplification gain and adds the pixel to the programmable gain amplifier circuit 4 The circuit 7 may be controlled.

  The control circuit 13 controls the signal amplitude adjustment function of each of the aperture of the lens 1, the exposure time of the solid-state imaging device 2, the amplification gain of the programmable gain amplification circuit 4, and the pixel addition in the pixel addition circuit 7 to control the average level of the signal amplitude. (The average level of the signal amplitude of the output PO of the pixel addition circuit 7) is maintained.

  When applying a signal amplitude adjustment function with a large change in signal amplitude, such as pixel addition in the pixel addition circuit 7, other signal amplitude adjustment means are set to cancel each other so that the amplitude does not change suddenly before and after application. By setting the overall gain of all signal amplitude adjustment means to be the same before and after application, the brightness of the output signal will not change suddenly, and the person watching the screen will feel uncomfortable or difficult to see. Disappear.

  In the above example, priority is given to the four reference pixels, and only the higher priority ones are selected and added, but by weighting each of the selected reference pixel signals, It is good also as adding at a predetermined ratio.

Embodiment 3 FIG.
FIG. 7 is a block diagram showing an imaging apparatus according to Embodiment 3 of the present invention. The configuration and operation of each circuit excluding the synchronization signal generation circuit 17 are the same as those described in the first embodiment or the second embodiment, and the effects by these are also the same.

  An external synchronization signal composed of a horizontal synchronization signal and a vertical synchronization signal is applied to the external synchronization signal input terminal 15 from the outside, and is supplied to the synchronization signal generation circuit 17. The synchronization signal generation circuit 17 generates an internal vertical synchronization signal, an internal horizontal synchronization signal, and a clock signal synchronized with the external vertical synchronization signal and the external horizontal synchronization signal applied to the external synchronization signal input terminal 15 to generate a composite video signal generation circuit. 8 is supplied. Further, a vertical synchronization signal and a horizontal synchronization signal at a timing advanced by one field from the external vertical synchronization signal and the external horizontal synchronization signal are generated and supplied to the digital signal processing circuit 6 and the timing generation circuit 11.

  With reference to FIG. 8, the phase relationship of each signal is demonstrated. The external input synchronization signal VDHEX applied to the external synchronization signal input terminal 15 generates a synchronization signal VDHD0 having a timing advanced by one field from the external input synchronization signal VDHDEX by the synchronization signal generation circuit 17 to generate the timing generation circuit 11 and the digital signal. The signal is supplied to the signal processing circuit 6.

  As described above, the synchronization signals of the A field and the B field are alternately arranged for each field, and the phase of the horizontal synchronization signal with respect to the vertical synchronization signal is aligned in the A field. The phase of the horizontal synchronizing signal with respect to the signal is shifted by 1/2 horizontal scanning period, and the synchronizing signal advanced by one field is generated from the synchronizing signal of the current field. For example, by changing the initial value (initial phase) of the vertical counter and the horizontal counter for generating the vertical synchronizing signal and the horizontal synchronizing signal, the phase of the vertical synchronizing signal and the horizontal synchronizing signal with the same phase are also halved. It is also possible to generate a vertical synchronizing signal and a horizontal synchronizing signal that are shifted in the horizontal scanning period.

  The timing generation circuit 11 drives the solid-state imaging device 2 based on a one-field preceding synchronization signal VDHD0 at a timing advanced by one field. The imaging signal output from the solid-state imaging device 2 is synchronized with the one-field preceding synchronization signal VDHD0, and the luminance signal Y, RY color difference signal Cr, and BY color difference signal output from the digital signal processing circuit 6 are also 1. It is synchronized with the field preceding synchronization signal VDHD0.

  As the input luminance signal Y of the pixel addition circuit 7, the 1-field preceding synchronization signal VDHD0 is superimposed on the image information of the Y2 field at the timing of the B field 1B of the first frame, and at the timing of the A field 2A of the second frame, The image information of the Y3 field is superimposed, the image information of the Y4 field is superimposed at the timing of the B field 2B of the second frame, and the image information of the Y5 field is superimposed at the timing of the A field 3A of the third frame. The image information of the Y6 field is superimposed at the timing of the B field 3B of the frame, and the image information of the Y7 field is superimposed at the timing of the A field 4A of the fourth frame.

  In the pixel addition circuit 7, the input field luminance signal Y (P33, P31 in FIG. 2) of the current field, the luminance signal of one field before, that is, the one field delayed luminance signal Y1DL (P22 of FIG. 2), and the luminance of two fields before The signal, that is, the two-field delayed luminance signal Y2DL (P13 and P11 in FIG. 2) is added to output an added luminance signal YADD (PO in FIG. 2).

  The added luminance signal YADD needs to be synchronized in phase with the target pixel P22 located at the center of the added pixel. Further, it is necessary to output the added luminance signal YADD in synchronization with a synchronization signal input from the outside. The synchronization signal generation circuit 17 generates a one-field preceding synchronization signal VDHD0 in which the external input synchronization signal VHDEX is preceded by 263 lines so that the synchronization signal phases of the external input synchronization signal VDHDEX and the one-field delayed luminance signal Y1DL coincide with each other. This is supplied to the generation circuit 11 and the digital signal processing circuit 6.

  The synchronization signal generation circuit 17 outputs a synchronization signal that is 263 lines ahead of the external input synchronization signal VDHDEX that is the reference of the output signal for the horizontal synchronization timing and the vertical synchronization timing that are the reference of the imaging operation, and the digital signal processing circuit 6. By supplying to, a signal that matches the phase of the target pixel located at the center of each pixel to be subjected to pixel addition can be output in synchronization with the external input synchronization signal VDHDEX. When the control circuit 13 switches the number of added pixels of the addition control signal CSW to the pixel adding circuit 7, it is possible to prevent the angle of view from fluctuating. Sensitivity can be controlled from 1 to 5 times with the same composition of the subject.

  In each of the above-described embodiments, only the delay circuit for matching the phase between the calculation target pixels that arises in principle from the spatial pixel arrangement has been described explicitly. Actually, it is necessary to consider the processing delay of each circuit, but the delay amount depends on the mounting means and is not clearly shown in the configuration diagram.

  In each of the above embodiments, the description has been made based on one configuration example of the solid-state imaging device. However, any two-dimensional image sensor capable of capturing a moving image may actually be a CCD or a CMOS image sensor. . Further, not limited to the interline transfer CCD, a frame transfer CCD or a frame interline transfer CCD may be used.

  In each of the above embodiments, for convenience of explanation, the system in which the input signal of the pixel addition circuit 7 is the color signal of the luminance signal Y, the RY color difference signal Cr, and the BY color difference signal Cb has been described as an example. The input signal of the adder circuit 7 may be a monochrome signal with only a luminance signal, and operates in the same manner as in the case of a color signal, and an equivalent effect is obtained.

  In each of the above embodiments, for convenience of explanation, the system in which the input signal of the pixel addition circuit 7 is a luminance signal, an RY color difference signal, and a BY color difference signal has been described as an example. May be an R signal, a G signal, or a B signal, and operates in the same manner as in the case of a luminance signal, an RY color difference signal, or a BY color difference signal, and an equivalent effect is obtained.

  In each of the above embodiments, for convenience of explanation, the system in which the output of the imaging apparatus is a composite video signal has been described as an example. However, the luminance signal, the RY color difference signal, the BY color difference signal, the horizontal synchronization signal, and the vertical synchronization are described. Even when the signal is output in parallel, the luminance signal, the RY color difference signal, the BY color difference signal, and the composite synchronization signal are output in parallel, and the R signal, G signal, B The signal, horizontal sync signal, and vertical sync signal may be output in parallel, or the R signal, G signal, B signal, and composite sync signal may be output in parallel. The same operation can be obtained with the same effect.

  In each of the above embodiments, for convenience of explanation, the imaging apparatus corresponding to the NTSC system television has been described as an example. However, the imaging apparatus corresponding to the PAL system television may be used, and the 1: 2 interlaced scanning system is supported. It is only necessary to operate in the same manner as in the case of NTSC television, and the same effect can be obtained. In the case of the PAL system, one field delay is 313 line delay and two field delay is 625 line delay. With such a configuration, the sensitivity can be improved by pixel addition using the peripheral pixels of the pixel of interest in the imaging apparatus compatible with the PAL television, and the subject can be visually recognized in an extremely dark low-light environment.

  In each of the above embodiments, the A field and the B field are expressed for convenience of explanation, but in practice, the interlaced scanning field determined by the configuration of the solid-state imaging device, the synchronization signal, the drive pattern, the television signal format, and the like. It follows the definition.

  In each of the above embodiments, the analog signal output imaging device has been described as an example for convenience of explanation. However, a digital interface circuit may be arranged after the pixel addition circuit to output a digital signal. It operates in the same way as the case, and an equivalent effect is obtained.

  DESCRIPTION OF SYMBOLS 1 Lens, 2 Solid-state image sensor, 3 Correlated double sampling processing circuit, 4 Programmable gain amplifier circuit, 5 A / D conversion circuit, 6 Digital signal processing circuit, 7 Pixel addition circuit, 8 Composite video signal generation circuit, 9 D / A conversion circuit, 10 drive circuit, 11 timing generation circuit, 12 synchronization signal generation circuit, 13 control circuit, 14 output terminal, 15 external synchronization signal input terminal, 16 storage element, 17 synchronization signal generation circuit, 71 pixel extraction circuit, 701 Input terminal, 702 263 line delay circuit, 703 1 line delay circuit, 704 525 line delay circuit, 705 526 line delay circuit, 706 first adder circuit, 707 switching circuit, 708 second adder circuit, 709 output terminal, 710 Control terminal, 711 rank determination circuit 712 selection adder circuit.

Claims (14)

Imaging means;
A signal processing means for outputting an interlaced scanning video signal based on the imaging signal read from the imaging means;
Pixel extraction means for delaying the imaging signal in field units and line units to simultaneously extract each pixel value of a target pixel and a plurality of reference pixels around it;
In the pixel of interest
A first reference pixel located directly above the screen one field before the target pixel;
A second reference pixel located in the direction directly below the screen one field before the target pixel;
The pixel values of the third reference pixel located in the direction directly above the screen one field after the target pixel and the fourth reference pixel located in the direction directly below the screen one field after the target pixel are added at a predetermined ratio. An image pickup apparatus comprising: a pixel addition unit that performs the above operation. The pixel extracting means includes
The video signal is used as a current signal representing a pixel value of a reference pixel located directly below the screen one field after the target pixel,
First delay means for extracting the pixel value of the pixel of interest by delaying the current signal by one field;
Second delay means for delaying the current signal by one line and extracting a pixel value of a reference pixel located immediately above the screen one field after the target pixel;
Third delay means for delaying the current signal by two fields and extracting a pixel value of a reference pixel located immediately below the screen one field before the target pixel;
The fourth delay means for extracting a pixel value of a reference pixel that is positioned immediately above the screen one field before the target pixel by delaying the current signal by two lines and one line. The imaging apparatus according to 1.   3. The imaging apparatus according to claim 1, further comprising a control unit that sets an exposure time and an amplification gain of an amplification unit that amplifies the imaging signal based on the magnitude of the imaging signal output from the imaging unit. .   The pixel addition means uses only the pixel value of the target pixel as a first addition result based on an instruction from the control means, and sets the pixel value of the first to fourth reference pixels as the pixel value of the target pixel. 4. The imaging apparatus according to claim 1, wherein a value obtained by adding is used as a second addition result, and the first addition result or the second addition result is switched and output. 5.   The control means outputs the first addition result when the imaging signal is higher than a predetermined level, and outputs the second addition result when the imaging signal is lower than the predetermined level. The imaging apparatus according to claim 4, wherein the adding means is controlled. The control means outputs a signal designating the number of pixels to be added based on the level of the imaging signal,
The pixel addition means, when the number of pixels to be added designated by the control means is n,
The value obtained by adding the pixel values of (n-1) reference pixels selected in descending order of priority among the reference pixels is output as an added pixel value. Imaging device.   The imaging apparatus according to claim 6, wherein the priority of the reference pixel is higher as the absolute value of the difference between the pixel value of the target pixel and the pixel value of each of the reference pixels is smaller.   8. The image pickup apparatus according to claim 6, wherein the control means specifies the number of pixels to be added by increasing the level of the image pickup signal. A further amplifying means for amplifying the imaging signal;
The control means switches the number of added pixels, and when the number of added pixels changes from M (M is a positive integer) to N (N is a positive integer), the amplification gain of the amplifying means is simultaneously increased (M / N 9. The image pickup apparatus according to claim 5, wherein control is performed so as to switch to double.   10. The imaging apparatus according to claim 1, further comprising composite video signal generation means for generating a composite video signal by superimposing a synchronization signal on an output signal of the pixel addition means.   11. The imaging apparatus according to claim 10, wherein the composite video signal generation unit generates the composite video signal based on a timing obtained by delaying a horizontal synchronization timing and a vertical synchronization timing of the current signal by one field. The composite video signal generating means generates a composite video signal based on a horizontal synchronization timing and a vertical synchronization timing synchronized with a reference signal input from the outside,
The imaging apparatus according to claim 10, wherein the imaging unit is driven based on a timing advanced by one field from the synchronization signal.   The imaging apparatus according to claim 2, wherein the one-field delay is a 263 line delay, and the two-field delay is a 525 line delay.   The imaging apparatus according to claim 2, wherein the one-field delay is a 313 line delay, and the two-field delay is a 625 line delay.

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