JPH1141066A - Digital filter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of multiplying means and to reduce to a half the circuit scale of a multi-input adding circuit which adds the output of the multiplying means by calculating the difference between the outputs of a 1st storage means stored with input data and a 2nd storage means stored with intermediate data. SOLUTION: The registers 1001 and 1002 of the 1st storage means 2001 and the registers 1003 to 1005 of the 2nd storage means 2002 are connected in series. The inputted data is stored in the registers 1001 and 1002 and 1003 to 1005. Then subtracting means 1201 to 1203 subtract the output data of the 2nd storage means 2002 from the output of the 1st storage means 2001 or the input data. The outputs of the subtracting means 1201 to 1203 are inputted to the multiplying means 1501 to 1503 and are multiplied by coefficients 1401 to 1403 respectively. The outputs of the multiplying means 1501 to 1503 are inputted to the multi- input adding means 1901 and added together, and the result is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital filter circuit used in digital signal processing.

[0002]

2. Description of the Related Art In recent years, with the progress of digital communication technology and semiconductor integrated technology, digitalization of television broadcasting has been promoted. Among them, VSB (vestigial sideban) is one of the modulation methods used for digital broadcasting by terrestrial broadcasting.
d: vestigial sideband) modulation. In the VSB modulation, a phase detection process is required when performing a waveform equalization process on the receiving side. This phase detection is performed by generating Q channel data from the received I channel data using Hilbert transform. Although the Hilbert transform is constituted by a digital filter circuit, it is important to reduce the size and cost of the digital filter circuit for practical use.

As an example of a digital filter circuit, Hatori and Mochida: "Digital Signal Processing", Maruzen, pp.37-38,
ISBN 4-621-03923-7 C3355 (1994). The digital filter circuit described above includes a register of (number of taps-1), multipliers having the same number as the number of taps, and a multi-input adder that receives all outputs of the multipliers as inputs.

[0004]

However, in the above configuration, multiplication must be performed for each input data and each output of the register, so that the same number of multiplication means as the number of taps is required, and the circuit scale is reduced. There has been a problem that the power consumption has increased due to the increase.

When the Hilbert transform is constituted by a digital filter, the number of taps of the digital filter circuit is N (N is an integer of 2 or more), and when N = even, the filter coefficient is Ci (i = 0 to (N -2) / 2), and when N = odd, if the filter coefficient is Ci (i = 0 to (N-3) / 2), there is a relationship of Ci = -C (Ni-1).

Therefore, the present invention newly focuses on the fact that tap pairs having the same absolute value of the filter coefficient can be subtracted before multiplication in the digital filter circuit, and a new subtraction means is added. Instead, it is obtained by reducing the number of multiplication means. In addition, instead of the subtraction means, it is obtained by using an addition means and one sign inversion means whose circuit scale is smaller than that of the subtraction means.

Further, the present invention is obtained by using, instead of the subtraction means, an addition means and one bit inversion means whose circuit scale is smaller than that of the subtraction means.

Accordingly, the present invention has been made in view of the above problems, and has as its object to provide a small-sized digital filter circuit.

[0009]

In order to solve the above-mentioned problems, a digital filter circuit according to the present invention comprises: first storage means for storing input data; and input data stored in the first storage means. Second storage means for performing subtraction of input data or data stored in the first storage means and data stored in the second storage means, and multiplication for multiplying an output of the subtraction means by a coefficient. And a multi-input adding means for adding the outputs of the multiplying means, and the output of the multi-input adding means is used as output data.

Further, in the digital filter circuit according to the first aspect, the subtraction function is realized by configuring the subtraction means with a sign inversion means and an addition means.

Further, in the digital filter circuit according to the present invention, the subtraction function is realized by configuring the subtraction means by bit inversion means and add-in means with carry-in.

The present invention reduces the number of multiplication means by subtracting the output from the first storage means storing the input data and the output from the second storage means storing the intermediate data. This is to reduce the circuit scale of the multi-input adding means for adding the outputs of the multiplying means. Conventionally, data for each tap was multiplied first, and then the result of the multiplication was subtracted.Therefore, the same number of multiplication means as the number of taps was required. That is, since the number of data to be multiplied can be reduced by performing subtraction first and multiplying the subtraction result, the number of multiplication means can be reduced and the overall circuit scale can be reduced.

Further, according to the present invention, the subtracting means of the present invention comprises one sign inverting means and an adding means, and the sign inverting means is provided between the first storage means and the second storage means. By arranging, the number of sign inversion means is reduced and the circuit scale is reduced as compared with the case where the sign inversion means is provided for each addition means.

Further, according to the present invention,
The subtraction means according to claim 1 is constituted by a bit inversion means and an addition means with carry-in, and the bit inversion means is arranged between the first storage means and the second storage means. The circuit scale is reduced by reducing the number of bit inversion means as compared with the case of providing.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital filter circuit according to an embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a configuration diagram of a digital filter circuit that performs Hilbert transform according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 2001 denotes first storage means for storing input data, and 2002 denotes first storage means 2001.
And 1201 to 1203 are subtraction means for subtracting the output of the second storage means 2002 from the input data or the output of the first storage means 2001. First storage means 20
Components of 01 are registers 1001 and 1002, each of which is connected in series. The components of the second storage means 2002 are registers 1003 to 1005, each of which is connected in series. 1501 to 1503 are multiplication means for multiplying the outputs of the subtraction means 1201 to 1203 by the coefficients 1401 to 1403,
The outputs 1501 to 1503 are all added by the multi-input adding means 1901 to be output.

The operation of the digital filter circuit configured as described above will be described below with reference to FIG. The input data is stored in registers 1001 and 1002 constituting the first storage means 2001 and registers 1003 to 1005 constituting the second storage means 2002. Next, from the output or input data of the first storage means 2001, the second storage means 2002
Is subtracted by subtraction means 1201 to 1203. Outputs of the subtraction means 1201 to 1203 are respectively multiplied by the multiplication means 1501 to 15
03 is input and multiplied by coefficients 1401 to 1403, respectively.
The outputs of the multiplication means 1501 to 1503 are input to the multi-input addition means 1901 and are all added up to become output data.

As described above, according to the present embodiment, the subtraction means 1201 to 1203 are provided, and the output data of the second storage means 2002 is subtracted from the output or input data of the first storage means 2001. Multiplying means by subtracting
The number of 1501 to 1503 can be halved, and the circuit scale of the multi-input adding means 1901 for adding the outputs of the multiplying means can be halved.

Here, the data input is x (0), the register
Assuming that the data outputs of 1001 to 1005 are x (1) to x (5), the data output Y is (Equation 3).

[0020]

(Equation 3)

This is nothing but Hilbert transform when the number of taps is six. As described above, the digital filter according to the first embodiment can perform the Hilbert transform when the number of taps is six.

(Embodiment 2) Hereinafter, Embodiment 2 of the present invention will be described with reference to the drawings.

FIG. 2 is a configuration diagram of a digital filter circuit according to the second embodiment of the present invention. The difference from FIG. 1 is that one sign inversion means 1601 and addition means 11
This is the point where 01 to 1103 are provided. 2, components having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The operation of the digital filter circuit configured as described above will be described below with reference to FIG. The input data is stored in registers 1001 and 1002 constituting the first storage unit 2001. First storage means 20
The output of 01 is inverted in sign of the value of the output data by the sign inversion means 1601 and stored in the registers 1003 to 1005 constituting the second storage means 2002. Next, the first storage means 2001
And the output data of the second storage means 2002 and the output data of the second storage means 2002 are added by the addition means 1101-1103. Addition means
Outputs of 1101 to 1103 are input to multiplication means 1501 to 1503, respectively, and multiplied by coefficients 1401 to 1403, respectively. The outputs of the multiplication means 1501 to 1503 are input to the multi-input addition means 1901 and are all added up to become output data.

As described above, according to this embodiment, the sign inverting means 1601 and the adding means 1101 to 1103 are provided, and the sign is inverted by the output or input data of the first storage means 2001 and the sign inverting means 1601. By adding the output data of the second storage means 2002 in which the data is stored by the adding means 1101-1103, the subtracting means used in the first embodiment is added.
Instead of 1201 to 1203, the circuit scale can be reduced by using the addition units 1101 to 1103 and one sign inversion unit 1601 whose circuit scale is smaller than that of the subtraction units 1201 to 1203. Further, since the number of the sign inverting means 1601 may be one without depending on the number of taps of the filter, the effect of reducing the circuit scale increases as the number of taps increases.

(Embodiment 3) Embodiment 3 of the present invention will be described below with reference to the drawings.

FIG. 3 is a configuration diagram of a digital filter circuit according to the third embodiment of the present invention. The difference from FIG. 1 is that one bit inversion means 1701, addition means with carry-in 2101 to 2103, and constants 11031 to 1303 are provided as subtraction means. 3, components having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The operation of the digital filter circuit configured as described above will be described below with reference to FIG. The input data is stored in registers 1001 and 1002 constituting the first storage unit 2001. First storage means 20
In the output of 01, all bits of the output data are inverted by the bit inversion means 1701 and stored in the registers 1003 to 1005 constituting the second storage means 2002. Next, the output or input data of the first storage means, the output data of the second storage means, and the constants 11031 to 1303 are added to the addition means with carry-in 2101 to 2110.
Add by 03. Addition means with carry-in 2101-
Outputs of 2103 are input to multiplication means 1501 to 1503, respectively, and are multiplied by coefficients 1401 to 1403, respectively. Multiplication means 1501
The outputs 1503 to 1503 are input to the multi-input adding means 1901 and are all added up to become output data. As described above, according to the present embodiment, the bit inversion means 1701, the addition means with carry-in 2101 to 2103, and the constants 11031 to 1303 are provided.
Output or input data of the storage means and bit inversion means 17
By adding the output data of the second storage unit storing the data in which all the bits are inverted by 01 and the constants 11031 to 1303 by the adding units with carry-in 2101 to 2103, the sign inversion used in the second embodiment is performed. The circuit scale can be reduced by using the bit inversion means 1601 having a smaller circuit scale than the sign inversion means 1601 instead of the means 1601. Also, since the number of bit inversion means 1701 can be one without depending on the number of taps of the filter, the effect of reducing the circuit scale increases as the number of taps increases.

In the first, second, third, and fourth embodiments, each storage means has a shift register configuration, but may be configured using one or a plurality of RAMs.

In the first, second, third, and fourth embodiments, the number of registers is five, but any number may be used as long as it is one or more. In that case, the number of registers is n,
The input data is x (0), the first to n-th output data of the register is x (1) to x (n), and the combination of the data to be subtracted is x (J) -x (K) (J + K = n, where n is an even number, x (n / 2) is not input to the subtraction means), so that when the number of registers is odd (Equation 1) and when the number of registers is even (Equation 2) The operation of the Hilbert transform can be performed.

[0031]

(Equation 4)

[0032]

(Equation 5)

In the first embodiment, a plurality of subtracting means and a plurality of multiplying means are used. However, by performing time division multiplexing, a structure using one subtracting means and one multiplying means is provided. You may.

In the second, third and fourth embodiments, a plurality of adding means and a plurality of multiplying means are used. However, by performing time division multiplexing, one adding means and one multiplying means are used. May be configured.

In the first, second, third, and fourth embodiments, the multiplication means and the multi-input addition means for adding the outputs of the multiplication means are used. You may comprise using a sum operation means.

[0036]

As described above, the present invention reduces the number of multiplication means by half by subtracting the output from the first storage means storing the input data and the output from the second storage means storing the intermediate data. However, the circuit scale of the multi-input adding means for adding the outputs of the multiplying means can be reduced by half.

Further, according to the present invention, a plurality of subtracting means according to claim 1 are replaced by one sign inverting means and a plurality of adding means, and the sign inverting means is replaced by a first storage means and a second storage means. By arranging between the means, a plurality of sign inversion means, which are components of the plurality of subtraction means, can be constituted by one sign inversion means, and the circuit scale can be reduced. Further, according to the present invention, the subtracting means of the first aspect is replaced with the bit inverting means and the add-in means with carry-in, and the bit inverting means is replaced by the first
By disposing between the storage means and the second storage means, a plurality of bit inversion means, which are components of the plurality of subtraction means, can be constituted by one bit inversion means, and the circuit scale can be reduced. Can be.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a digital filter circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a digital filter circuit according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a digital filter circuit according to a third embodiment of the present invention.

[Explanation of symbols]

1001,1002,1003,1004,1005
Registers 1101, 1102, 1103 Addition means 2101, 1022, 2103 Addition means with carry-in 1201, 1202, 1203 Subtraction means 1301, 1302, 1303 Constant 1 1401 Coefficient C1 1402 Coefficient C2 1403 Coefficient C3 1501, 1502, 1503 Multiplication means 1601 Code Inversion means 1701 Bit inversion means 1901 Multi-input addition means 2001 First storage means 2002 Second storage means

Claims (5)

[Claims] A first storage unit for storing input data; a second storage unit for inputting data stored in the first storage unit; and a storage unit for storing the input data or the first storage unit. Subtraction means for subtracting the stored data from the data stored in the second storage means; multiplication means for multiplying the output of the subtraction means by a coefficient; and multi-input addition for adding the outputs of the multiplication means. Means for outputting digital data from an output of said multi-input adding means. 2. The digital filter circuit according to claim 1, wherein said subtracting means comprises a subtractor. 3. The digital filter circuit according to claim 1, wherein said subtracting means comprises a sign inverting means and an adding means, and data stored in said first storage means is inputted to said sign inverting means, and said sign inversion is performed. A digital filter circuit, wherein the output of the means is stored in a second storage means, and the output of the first storage means and the output of the second storage means are input to the addition means. 4. The digital filter circuit according to claim 1, wherein said subtracting means comprises bit inverting means and add-in means with carry-in, and inputs data stored in said first storage means to said bit inverting means; The output of the bit inversion means is stored in a second storage means, and the output of the first storage means, the output of the second storage means, and a constant 1 are input to the addition means with carry-in. Digital filter circuit. 5. The digital filter circuit according to claim 1, wherein the number of taps of the digital filter circuit is N (N is an integer of 2 or more) and the input data is x.
(i) (i = 0 to (N-1) integer), the coefficient is Ci, and the input data or the data stored in the first storage means and the intermediate data stored in the second storage means. From the data ｛x (i)
-x (N-1-i)}, and {x (i) -x (N-1-i)} * Ci is calculated by the multiplication means from the calculation result and the coefficient, and the output of the multiplication means is calculated. When N = even number by the multi-input adding means, (Equation 1)
Sigma, and when N = odd, (Equation 2)
A digital filter circuit characterized in that the addition is performed in a combination indicated by sigma. (Equation 1) (Equation 2)