JP3865469B2 - Butterfly calculator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a butterfly computing unit constituting a butterfly computing device used in fast Fourier transform or the like.
[0002]
[Prior art]
  In recent years, with the progress of digital communication technology and semiconductor integration technology, digitization of television and radio broadcasting has been promoted. In digital broadcasting using terrestrial waves, OFDM (Orthogonal Frequency Division Multiplex) is often used as a modulation / demodulation method. OFDM is a method for efficiently transmitting a number of information within a limited frequency band, and has a feature for terrestrial broadcasting that is resistant to multipath interference. However, in OFDM, it is necessary to perform a large-scale fast Fourier transform of several thousand samples, and the cost reduction of the fast Fourier transform device is an important issue for practical use.
[0003]
  In the fast Fourier transform, a calculation is performed by performing a basic calculation called a butterfly calculation and a rotor multiplication that multiplies the calculation data by the rotor data a plurality of times. Therefore, the fast Fourier transform device includes a butterfly computation device that performs butterfly computation and rotator multiplication, and performs fast Fourier transform by repeatedly using the butterfly computation device. The most common butterfly operation is a radix-2 butterfly operation. When performing a fast Fourier transform of the number of samples N = 2 ^ n (n represents a positive integer, ^ represents a power) using a radix-2 butterfly operation, the radix-2 butterfly operation is performed by n · 2 ^ (n -1) Repeat.
[0004]
  On the other hand, a large-scale fast Fourier transform often uses a high radix butterfly computation such as radix 4 in order to reduce a huge amount of computation. An example of a conventional fast Fourier transform device using a high radix butterfly operation is one that performs a fast Fourier transform using a radix 4 butterfly operation. A. Delaruelle et al. (In IEEE Custom Integrated Circuit Conference, May 1994).
[0005]
[Problems to be solved by the invention]
  However, conventionally, when the radix-4 butterfly operation is used for the fast Fourier transform, there is a problem that the circuit scale of the fast Fourier transform device increases.
[0006]
  First, since the radix-4 butterfly operation is more complicated than the radix-2 butterfly operation, the circuit scale of the butterfly calculator increases accordingly.
[0007]
  Further, when performing fast Fourier transform of the number of samples N = 2 ^ n using the radix-4 butterfly operation, depending on the value of n, it is necessary to perform the radix-2 butterfly operation together. That is, when n is an even number, radix-4 butterfly operations may be performed n · 2 ^ (n−3) times, but when n is an odd number, (n−1) · 2 ^ (n−3) times. Radix-4 butterfly computation and 2 ^ (n-1) radix-2 butterfly computations. In order to realize such an operation, the butterfly computing unit needs to have a function of performing both radix-4 and radix-2 butterfly computations. This leads to an increase in the circuit scale of the butterfly computing unit, which in turn leads to an increase in the circuit scale of the fast Fourier transform device.
[0008]
  In addition, since the number of calculations and the number of calculation result data are different in the radix-4 and radix-2 butterfly calculations, the radix-4 and radix-2 butterflies are used in the repetitive calculation for the fast Fourier transform only by providing both the calculation functions. The timing at which the calculation result is obtained in the calculation is different, which causes a problem that the control of the fast Fourier transform becomes complicated.
[0009]
  In view of the above problems, an object of the present invention is to provide a butterfly calculator with a small circuit scale that performs radix-4 butterfly calculations. It is another object of the present invention to provide a butterfly calculator that can execute radix-4 and radix-2 butterfly calculations at the same timing and has a small circuit scale.
[0010]
[Means for Solving the Problems]
  In order to solve the above-described problem, the present invention performs radix-4 butterfly computation in a time-sharing manner by pipeline processing to reduce the circuit scale of the computation unit. Further, by recursively using intermediate data in the pipeline processing for calculation, the number of butterfly inputs that need to be held is reduced, and the number of data buffer registers is reduced. Furthermore, the present invention is configured such that one radix-4 butterfly computation and two radix-2 butterfly computations are obtained at the same timing using a common computing unit.
[0011]
  Specifically, the means taken by the invention of claim 1 is that the radix-4 butterfly operation is expressed by the following equation:
  X0 = (x0 + x2) + (x1 + x3)
  X1 = (x0−x2) + j (x1−x3)
  X2 = (x0 + x2)-(x1 + x3)
  X3 = (x0−x2) −j (x1−x3)
(However, x0, x1, x2, and x3 are butterfly inputs, and X0, X1, X2, and X3 are operation result data)
As a butterfly calculator that performs pipeline processing according toIn orderBased on the first data buffer to be stored and at least the butterfly input stored in the first data buffer, x0 + x2, x1 + x3, x0-x2, j (x1-x3) are calculated for each cycle as intermediate data. The first calculation unit and the intermediate data calculated by the first calculation unitIn orderA second data buffer for storing, and a second calculation unit for calculating calculation result data for each cycle based on at least the intermediate data stored in the second data buffer.The first operation unit performs an operation using the intermediate data stored in the second data buffer.Is a thing.
[0012]
  According to the first aspect of the present invention, the first calculation unit calculates intermediate data for each cycle based on at least the butterfly input stored in the first data buffer, and the second calculation unit includes at least the second calculation unit. On the basis of the intermediate data stored in the data buffer, calculation result data is calculated for each cycle. That is, since the butterfly operation is performed in a time-sharing manner for each cycle, the circuit scale of the operation unit is reduced.In addition, since the first calculation unit performs calculation using the intermediate data stored in the second data buffer, the intermediate calculation already calculated based on the butterfly input is performed. The data is recursively used to calculate new intermediate data. For this reason, the number of butterfly inputs that need to be held in the first data buffer is reduced, whereby the circuit scale of the first data buffer can be reduced.
[0013]
  AndClaim 2In the invention ofClaim 1In the butterfly computing unit, the first data buffer includes two registers connected in series that sequentially shift the butterfly input every cycle, and the second data buffer shifts the intermediate data sequentially every cycle. , Two registers connected in series, wherein the first arithmetic unit is one of the butterfly input inputted to the butterfly computing unit and the intermediate data stored in the second stage register of the second data buffer. A first selection circuit that selectively outputs one of the above, a butterfly input stored in the second stage register of the first data buffer, and a fourth that multiplies this butterfly input by 2 A first circuit that adds or subtracts the output data of the fourth selection circuit to the output data of the selection circuit and the first selection circuit; A second selection circuit that selectively outputs, as intermediate data, one of the subtractor and the output data of the first adder / subtractor and the output data multiplied by an imaginary number j; A third selection circuit that selectively outputs one of the intermediate data output from the first calculation unit and the intermediate data stored in the second stage register of the second data buffer; The second selection circuit adds or subtracts the butterfly input stored in the first stage register of the second data buffer to the output data of the third selection circuit, and outputs the addition or subtraction result as operation result data. And an adder / subtractor.
[0014]
  Claim 2The invention ofClaim 1In the configuration of the invention, the first calculation unit selects and outputs either the butterfly input stored in the second stage register of the first data buffer or the butterfly input multiplied by 2 In addition to providing a circuit, instead of the butterfly input stored in the fourth stage register of the first data buffer, the intermediate data stored in the second stage register of the second data buffer is selected by the first selection circuit. It is data.
[0015]
  That is,Claim 2According to the invention, when the butterfly inputs are input in the order of x0, x1, x2, and x3, the first calculation unit performs the calculation over four cycles with a delay of two cycles from the input of the butterfly input. In the first two cycles, the first selection circuit selects the butterfly input input to the butterfly computing unit, and the fourth selection circuit receives the butterfly input stored in the second stage register of the first data buffer. The first adder / subtracter performs addition, and in the latter two cycles, the first selection circuit selects the intermediate data stored in the second stage register of the second data buffer, and the fourth The selection circuit selects the one obtained by multiplying the butterfly input stored in the second stage register of the first data buffer by 2, and the first adder / subtracter performs subtraction. The second selection circuit selectively outputs the output data of the first adder / subtracter in the first to third cycles, while the output data of the first adder / subtracter is multiplied by the imaginary number j in the final cycle. Select and output things. With this operation, intermediate data is output from the first arithmetic unit in the order of x0 + x2, x1 + x3, x0-x2, j (x1-x3), as in the second aspect of the invention. Therefore, the number of registers required for configuring the first data buffer can be reduced to 2.
[0016]
  Also,The solution provided by the invention of claim 3 is that when performing a radix-4 butterfly operation,
    X0 = (x0 + x2) + (x1 + x3)
    X1 = (x0−x2) + j (x1−x3)
    X2 = (x0 + x2)-(x1 + x3)
    X3 = (x0−x2) −j (x1−x3)
(However, x0, x1, x2, and x3 are butterfly inputs, and X0, X1, X2, and X3 are operation results. Fruit data)
As a butterfly computing unit to be executed by pipeline processing according to the above, based on the first data buffer for storing the input butterfly input and at least the butterfly input stored in the first data buffer, intermediate data x0 + x2, x1 + x3 , X0−x2, j (x1−x3) for each cycle, a second data buffer for storing intermediate data calculated by the first calculation unit, and at least the second A second computing unit that computes computation result data for each cycle based on the intermediate data stored in the data buffer, and when performing radix-2 butterfly computation,The first calculation unit can calculate x0 + x2, x1 + x3, x0-x2, x1-x3 as intermediate data for each cycle, and the second calculation unitBy adding 0,Intermediate data enteredSame value asOutput as operation result dataByThe butterfly computing unit performs two radix-2 butterfly computations using the following formula:
    X0 = x0 + x2
    X1 = x1 + x3
    X2 = x0-x2
    X3 = x1-x3
Run according toTo do.
[0017]
  Claim 3According to the invention, one radix-4 butterfly computation and two radix-2 butterfly computations can be performed using the first and second computing units, and the computation timing of the radix-4 and radix-2 butterfly computations. And the number of operation result data can be matched. In the radix-2 butterfly calculation, the first calculation unit only needs to calculate x1-x3 instead of j (x1-x3), and the second calculation unit only needs to output the input data as it is. There is very little change in the configuration of the first and second calculation units to enable execution of the radix-2 butterfly calculation.
[0018]
  AndClaim 4In the invention ofClaim 3In the butterfly computing unit, the first data buffer includes four registers connected in series for sequentially shifting the butterfly input every cycle, and the second data buffer shifts the intermediate data sequentially for each cycle. , Two registers connected in series, and the first arithmetic unit is one of the butterfly input inputted to the butterfly computing unit and the butterfly input stored in the fourth stage register of the first data buffer. A first selection circuit that selectively outputs one of them, and a butterfly input that is stored in the second stage register of the first data buffer is added to or subtracted from the output data of the first selection circuit. 1 of the first adder / subtracter, the output data of the first adder / subtractor, and the output data multiplied by the imaginary number j, A second selection circuit that selectively outputs the intermediate data output from the first calculation unit and the second stage register of the second data buffer. A third selection circuit that selectively outputs any one of the intermediate data and the logical value “0”, and the first stage of the second data buffer for the output data of the third selection circuit A second adder / subtracter that adds or subtracts the butterfly input stored in the register and outputs the addition or subtraction result as operation result data is provided.
[0019]
  Also,Claim 5In the invention ofClaim 3In the butterfly computing unit, the first data buffer includes two registers connected in series that sequentially shift the butterfly input every cycle, and the second data buffer shifts the intermediate data sequentially every cycle. , Two registers connected in series, wherein the first arithmetic unit is one of the butterfly input inputted to the butterfly computing unit and the intermediate data stored in the second stage register of the second data buffer. A first selection circuit that selectively outputs one of the above, a butterfly input stored in the second stage register of the first data buffer, and a fourth that multiplies this butterfly input by 2 A first circuit that adds or subtracts the output data of the fourth selection circuit to the output data of the selection circuit and the first selection circuit; A second selection circuit that selectively outputs, as intermediate data, one of the subtractor and the output data of the first adder / subtractor and the output data multiplied by an imaginary number j; The arithmetic unit selectively outputs any one of the intermediate data output from the first arithmetic unit, the intermediate data stored in the second stage register of the second data buffer, and the logical value “0”. The addition or subtraction of the butterfly input stored in the first stage register of the second data buffer is performed on the output data of the third selection circuit and the third selection circuit, and the addition or subtraction result is obtained. It is assumed that a second adder / subtracter that outputs the calculation result data is provided.
[0020]
  Claims 4 and 5According to the invention, in the radix-2 butterfly calculation, the third selection circuit selects the logical value “0”, so that the intermediate data input from the second calculation unit can be directly output as calculation result data. it can. In addition, by causing the second selection circuit to select the output data of the first adder / subtracter, x1-x3 can be output instead of j (x1-x3) from the first arithmetic unit.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0022]
(First embodiment)
  FIG. 1 is a configuration diagram of a butterfly computing device including a butterfly computing unit according to the first embodiment of the present invention. The butterfly computing device shown in FIG. 1 performs rotor multiplication and radix-4 butterfly computation as shown in FIG. That is, as shown in FIG. 10A, data D0 to D3 and rotator data are subjected to rotator multiplication, data x0 to x3 is calculated, and data x0 to x3 is used as a butterfly input. Based on the above, a butterfly operation is performed to calculate data X0 to X3.
  X0 = (x0 + x2) + (x1 + x3)
  X1 = (x0−x2) + j (x1−x3)
  X2 = (x0 + x2)-(x1 + x3)
  X3 = (x0−x2) −j (x1−x3)
[0023]
  In FIG. 1, 1 performs a butterfly operation using data x0 to x3 as butterfly inputs, outputs a computation result data X0 to X3, 5 performs a multiplication of the input data D0 to D3 and the rotor data Wi, A rotator multiplier for outputting data x0 to x3, and a register 7 for storing output data x0 to x3 of the rotator multiplier 5. As constituent elements of the butterfly calculator 1, 10 is a first data buffer for sequentially storing butterfly inputs x0 to x3, 20 is a butterfly input input to the butterfly calculator 1 and a butterfly stored in the first data buffer 10. Based on the input, a first calculation unit that calculates intermediate data, 30 is a second data buffer that sequentially stores the intermediate data output from the first calculation unit 20, and 40 is the first calculation unit 20. 2 is a second arithmetic unit that performs arithmetic operations on the operation result data X0 to X3 based on the intermediate data output from the intermediate data and the intermediate data stored in the second data buffer 30.
[0024]
  The first arithmetic unit 20 includes, as components, a first adder / subtractor 21 that performs addition or subtraction according to the control signal SA0, an imaginary number j (j²= -1) and a first selection circuit 23 and a second selection circuit 24 controlled by control signals SA0 and SS0, respectively. The second arithmetic unit 40 includes, as components, a second adder / subtractor 41 that performs addition or subtraction according to the control signal SA1 and a third selection circuit 42 that is controlled by the control signal SA1. Reference numerals 11 to 14, 31 and 32 are registers for updating values every cycle in the pipeline processing. The first data buffer 10 includes registers 11 to 14 connected in series. Consists of registers 31, 32 connected in series.
[0025]
  FIG. 2 is a diagram showing the output of each selection circuit according to the value of the selection signal. In the figure, (a) shows the output of the first selection circuit 23 according to the value of the selection signal SA0, (b) shows the output of the second selection circuit 24 according to the value of the selection signal SS0, (c ) Shows the output of the third selection circuit 42 in accordance with the value of the selection signal SA1. As shown in FIG. 2A, the first selection circuit 23 selects the selection signal SA0 from the butterfly input input to the butterfly calculator 1 and the butterfly input stored in the register 14 of the first data buffer 10. When “0” is “0”, the butterfly input input to the butterfly computing unit 1 is selected and when the selection signal SA0 is “1”, the butterfly input stored in the register 14 is selectively output. As shown in FIG. 2B, the second selection circuit 24 multiplies the output data of the first adder / subtractor 21 and the output data of the multiplier 22 (the output data of the first adder / subtractor 21 by an imaginary number j). Among them, when the selection signal SS0 is "0", the output data of the first adder / subtractor 21 is selected and when the selection signal SS0 is "1", the output data of the multiplier 22 is selectively output. As shown in FIG. 2C, the third selection circuit 42 is configured to output data from the second selection circuit 24 (intermediate data output from the first arithmetic unit 20) and a register of the second data buffer 30. Among the intermediate data stored in 32, when the selection signal SA1 is “0”, the output data of the second selection circuit 24 is displayed, and when the selection signal SA1 is “1”, the intermediate data stored in the register 32 is stored. Select output.
[0026]
  The first adder / subtracter 21 operates in accordance with the selection signal SA0, and performs addition when the selection signal SA0 is “0”, while performing subtraction when the selection signal SA0 is “1”. The second adder / subtractor 41 operates in accordance with the selection signal SA1, and performs addition when the selection signal SA1 is “0”, while performing subtraction when the selection signal SA1 is “1”.
[0027]
  Here, the input data D0 to D3, the butterfly inputs x0 to x3, the calculation result data X0 to X3, and the intermediate data output by the first calculation unit 20 are complex data.
[0028]
  FIG. 3 is a diagram showing the processing timing of the butterfly arithmetic apparatus shown in FIG. As shown in FIG. 3, the butterfly operation apparatus shown in FIG. 1 inputs input data D0 to D3 every cycle, and outputs operation result data X0 to X3 from the cycle following the input cycle of input data D3. To do. Each process in the butterfly arithmetic apparatus shown in FIG. 1 is a pipeline process, and it is possible to process the output of the operation result data X0 to X3 and the input of the next input data D0 to D3 overlapping each other. In FIG. 3, “register output” indicates data stored in each register.
[0029]
  The input data D0 to D3 are multiplied by the rotor data Wi by the rotor multiplier 5 and stored in the register 7 as data x0 to x3. The output data x0 to x3 of the register 7 are sequentially stored in the registers 11 to 14 of the first data buffer 10 as butterfly inputs.
[0030]
  The calculation of the intermediate data by the first calculation unit 20 is started with a delay of two cycles from the start of the butterfly inputs x0 to x3. The first calculation unit 20 receives the output data of the register 7 (butterfly input input to the butterfly calculator 1) and the output data of the second stage register 12 and the fourth stage register 14 of the first data buffer 10 as inputs. The first adder / subtractor 21 and multiplier 22 calculate intermediate data. The first adder / subtractor 21 outputs the first data for the output data of the register 7 and the output data of the fourth stage register 14 of the first data buffer 10 selected by the first selection circuit 23. The output data of the second stage register 12 of the buffer 10 is added or subtracted. The multiplier 22 multiplies the output data of the first adder / subtractor 21 by an imaginary number j, and the second selection circuit 24 selects either the output data of the first adder / subtractor 21 or the output data of the multiplier 22, Output as intermediate data.
[0031]
  In the calculation of the intermediate data by the first calculation unit 20, the selection signal SA0 is “0” in the first two cycles and “1” in the second two cycles. Accordingly, in the first two cycles, the first selection circuit 23 selects and outputs the butterfly input inputted to the butterfly computing unit 1, and the first adder / subtractor 21 performs addition, while in the second half two cycles, The selection circuit 23 selects and outputs the butterfly input stored in the fourth stage register 14 of the first data buffer 10, and the first adder / subtractor 21 performs subtraction. As a result, the output data of each cycle of the first adder / subtractor 21 is (x0 + x2), (x1 + x3), (x0−x2), and (x1−x3).
[0032]
  Further, the selection signal SS0 becomes “0” in the first three cycles and becomes “1” only in the last cycle. Accordingly, the second selection circuit 24 selects and outputs the output data of the first adder / subtractor 21 in the first three cycles, while the output data of the multiplier 22 (into the output data of the first adder / subtractor 21 in the last cycle). (Multiplied by an imaginary number j) is selected and output. As a result, (x0 + x2), (x1 + x3), (x0−x2), and j (x1−x3) are sequentially output from the first arithmetic unit 20 as intermediate data. The intermediate data output from the first arithmetic unit 20 is sequentially stored in the registers 31 and 32 in the second data buffer 30.
[0033]
  The calculation of the calculation result data by the second calculation unit 40 is delayed by one cycle from the calculation of the intermediate data by the first calculation unit 20, that is, by three cycles after the start of the butterfly inputs x0 to x3. The second arithmetic unit 40 receives the intermediate data output from the first arithmetic unit 20 and the intermediate data stored in the first stage register 31 and the second stage register 32 of the second data buffer 30 as inputs. The calculation result data is calculated by the 2 adder / subtractor 41. The second adder / subtractor 41 selects the output data of the second selection circuit 24 and the output data of the second stage register 32 of the second data buffer 30 selected by the third selection circuit 42. The output data of the first stage register 31 of the second data buffer 30 is added or subtracted.
[0034]
  In the calculation of the calculation result data by the second calculation unit 40, the selection signal SA1 is “0” in the first and third cycles and “1” in the second and final cycles. Therefore, in the first and third cycles, the third selection circuit 42 selects and outputs the output data of the second selection circuit 24, and the second adder / subtractor 41 performs addition, while in the second and final cycles. The third selection circuit 42 selectively outputs the output data of the second stage register 32 of the second data buffer 30, and the second adder / subtractor 41 performs subtraction. As a result, (x0 + x2) + (x1 + x3) (= X0), (x0 + x2) − (x1 + x3) (= X1), (x0−x2) + j (x1−x3) is obtained as calculation result data from the second calculation unit 40. (= X2), (x0-x2) -j (x1-x3) (= X3) are output.
[0035]
  That is, the input data is input in the order of D0, D1, D2, and D3, while the operation result data is output in the order of X0, X2, X1, and X3. When the output order of the operation result data is X0, X1, X2, and X3 so as to match the data input order, the order of the addresses for storing the operation result data may be changed.
[0036]
  Through the processing as described above, the butterfly operation device shown in FIG. 1 performs rotator multiplication and radix-4 butterfly operation on the input data D0 to D3, and calculates operation result data X0 to X3.
[0037]
  As described above, according to this embodiment, the first data buffer 10 that stores the butterfly input and the second data buffer 20 that stores the intermediate data are provided, and the first arithmetic unit 20 and the second arithmetic unit are provided. By using 40 in a time-sharing manner for each cycle by pipeline processing, the circuit scale of the computing unit of the butterfly computing unit that performs the radix-4 butterfly computation can be reduced.
[0038]
(Second Embodiment)
  Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
[0039]
  FIG. 4 is a block diagram of a butterfly computing device including a butterfly computing unit according to the second embodiment of the present invention. The butterfly operation apparatus shown in FIG. 4 performs the rotor multiplication and the radix-4 butterfly operation as shown in FIG. 10A, as in the first embodiment.
[0040]
  In FIG. 4, reference numeral 2 denotes a butterfly computing unit that performs butterfly computation based on butterfly inputs x0 to x3 and outputs computation result data X0 to X3. As constituent elements of the butterfly computing unit 2, 10A is a first data buffer for sequentially storing butterfly inputs x0 to x3, 20A is a butterfly input inputted to the butterfly computing unit 2, and a butterfly stored in the first data buffer 10A. Based on the input, a first calculation unit that calculates intermediate data, 30 is a second data buffer that sequentially stores the intermediate data output from the first calculation unit 20A, and 40 is the first calculation unit 20A. 2 is a second arithmetic unit that performs arithmetic operations on the operation result data X0 to X3 based on the intermediate data output from the intermediate data and the intermediate data stored in the second data buffer 30. 4, components having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted in the present embodiment.
[0041]
  The butterfly calculator 2 shown in FIG. 4 is different from the butterfly calculator 1 shown in FIG. 1 in that the first data buffer 10 of the butterfly calculator 1 shown in FIG. 1 is composed of four stages of registers. The first data buffer 10A of the butterfly computing unit 2 shown in FIG. 4 is composed of two-stage registers.
[0042]
  The first computing unit 20A of the butterfly computing unit 2 shown in FIG. 4 includes a multiplier 25 that multiplies input data by 2 and a control in addition to the components of the first computing unit 20 of the butterfly computing unit 1 shown in FIG. A fourth selection circuit 26 controlled by the signal SB0 is provided. That is, since the first data buffer 10A is composed of two stages of registers, the butterfly input input to the butterfly calculator 2 and the intermediate data stored in the second stage register 32 of the second data buffer 30 are the first. 1 is selected and output by the selection circuit 23, butterfly input stored in the second stage register 12 of the first data buffer 10A, and output data of the multiplier 25 (2 is input to the butterfly input stored in the register 12). The product selected by the fourth selection circuit 26 is used as the input to the first adder / subtractor 21.
[0043]
  FIG. 5 is a diagram showing the output of each selection circuit according to the value of the selection signal. In the figure, (a) shows the output of the first selection circuit 23 according to the value of the selection signal SA0, and (b) shows the output of the fourth selection circuit 26 according to the value of the selection signal SB0. ing. As shown in FIG. 5A, the first selection circuit 23 selects the selection signal SA0 from among the butterfly input inputted to the butterfly computing unit 2 and the intermediate data stored in the register 32 of the second data buffer 30. When “0” is “0”, the butterfly input inputted to the butterfly computing unit 2 is selected and when the selection signal SA0 is “1”, the intermediate data stored in the register 32 is selectively outputted. As shown in FIG. 5B, the fourth selection circuit 26 receives the selection signal SB0 out of the butterfly input stored in the second stage register 12 of the first data buffer 10A and the output data of the multiplier 25. When “0”, the butterfly input stored in the register 12 is selected, and when the selection signal SB0 is “1”, the output data of the multiplier 25 is selected and output.
[0044]
  FIG. 6 is a diagram showing the processing timing of the butterfly arithmetic apparatus shown in FIG. As in the first embodiment, the input data D0 to D3 are input for each cycle, and the operation result data X0 to X3 are output for each cycle from the cycle following the input cycle of the input data D3. Each process is a pipeline process, and it is possible to overlap the output of the operation result data X0 to X3 and the input of the next input data D0 to D3. Similarly to the first embodiment, the calculation of the intermediate data by the first calculation unit 20A starts two cycles after the start of the butterfly inputs x0 to x3, and the calculation result by the second calculation unit 40 The data calculation is started one cycle after the intermediate data calculation by the first calculation unit 20A, that is, three cycles after the start of the butterfly inputs x0 to x3.
[0045]
  The butterfly inputs x0 to x3 are sequentially stored in the registers 11 and 12 of the first data buffer 10A. The first arithmetic unit 20A includes a butterfly input input to the butterfly calculator 2, a butterfly input stored in the second stage register 12 of the first data buffer 10A, and a second stage register 32 of the second data buffer 30. The intermediate data stored in is input to the first adder / subtractor 21 and the multipliers 22 and 25. The first adder / subtractor 21 performs the butterfly stored in the register 12 for the butterfly input input to the butterfly calculator 2 and the intermediate data selected by the first selection circuit 23 among the intermediate data stored in the register 32. Of the input data and the output data of the multiplier 25, the data selected by the fourth selection circuit 26 is added or subtracted. The operations of the multiplier 22 and the second selection circuit 24 are the same as those in the first embodiment.
[0046]
  In the intermediate data calculation by the first calculation unit 20A, the selection signal SA0 is “0” in the first two cycles and “1” in the second two cycles. Therefore, in the first two cycles, the first selection circuit 23 selects and outputs the butterfly input inputted to the butterfly calculator 2, and the first adder / subtractor 21 performs addition, while in the second two cycles, the first selection circuit 23 performs first addition. The selection circuit 23 selects and outputs the intermediate data stored in the register 32, and the first adder / subtractor 21 performs subtraction. The selection signal SB0 is “0” in the first two cycles and “1” in the second two cycles. Accordingly, the fourth selection circuit 26 selects and outputs the butterfly input stored in the register 12 in the first two cycles, and selectively outputs the output data of the multiplier 25 in the second two cycles.
[0047]
  As a result, the first adder / subtractor 21 receives x2, x3, (x0 + x2), (x1 + x3) as input A and x0, x1, x2, 2, x3, 2 as input B in each cycle. . Therefore, the output data of the first adder / subtractor 21 is (x0 + x2), (x1 + x3), (x0−x2), (x1−x3).
[0048]
  The processes of the second data buffer 30 and the second arithmetic unit 40 are the same as in the first embodiment. As a result, (x0 + x2) + (x1 + x3) (= X0), (x0 + x2) − (x1 + x3) (= X2), (x0−x2) + j (x1−x3) is obtained as calculation result data from the second calculation unit 40. (= X1), (x0-x2) -j (x1-x3) (= X3) are output.
[0049]
  Here, paying attention to the first adder / subtractor 21, as shown in FIGS. 3 and 6, the same data is output in the present embodiment and the first embodiment. In the first embodiment, the first adder / subtractor 21 outputs the output data (x0−x2) and (x1−x3) in the latter two cycles to the second and fourth stage registers 12 of the first data buffer 10. , 14 from the butterfly input. For this reason, the first data buffer 10 requires a register having the number of stages equal to twice the data interval used in the first stage addition / subtraction of the butterfly operation shown in FIG. For example, (x0−x2) is an operation using 0th and 2nd data, and the data interval is 2. (X1-x3) is an operation using the first and third data, and the data interval is 2. Therefore, in the first embodiment, the first data buffer 10 requires four stages of registers.
[0050]
  On the other hand, in the present embodiment, the first adder / subtractor 21 stores the output data (x0−x2) and (x1−x3) in the latter two cycles in the second stage register 12 of the first data buffer 10A. It is calculated from the butterfly input and the intermediate data stored in the second stage register 32 of the second data buffer 30. That is, using the fact that the intermediate data (x0 + x2) and (x1 + x3) already calculated in the first two cycles are stored in the registers 31 and 32 of the second data buffer 30, values obtained by multiplying x2 and x3 by 2 respectively. Is subtracted to calculate output data (x0-x2) and (x1-x3) in the latter two cycles. As a result, the butterfly inputs x0 and x1 are not required for the calculation of the intermediate data in the latter two cycles, so that the first data buffer 10A can be configured with only two stages of registers.
[0051]
  As described above, according to the present embodiment, the multiplier 25 for multiplying the first arithmetic unit 20A by 2 is provided, and the first arithmetic unit 20A uses the intermediate data stored in the second data buffer 30. As a result, the number of register stages of the first data buffer 10A can be reduced.
[0052]
(Third embodiment)
  Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.
[0053]
  FIG. 7 is a block diagram of a butterfly computing device including a butterfly computing unit according to the third embodiment of the present invention. The butterfly computing device shown in FIG. 7 performs the rotor multiplication and radix-4 butterfly computation as shown in FIG. 10 (a), and the rotor multiplication and radix-2 butterfly computation as shown in FIG. 10 (b). is there.
[0054]
  When performing radix-2 butterfly computation, two butterfly computations are performed. That is, as shown in FIG. 10 (b), rotator multiplication of data D0 to D3 and rotator data is performed to calculate data x0 to x3, and data x0 to x3 is used as a butterfly input. Based on the above, a butterfly operation is performed to calculate data X0 to X3.
<First Radix-2 Butterfly Calculation>
  X0 = x0 + x2, X2 = x0-x2
<Second Radix-2 Butterfly Calculation>
  X1 = x1 + x3, X3 = x1-x3
[0055]
  In FIG. 7, reference numeral 3 denotes a butterfly calculator that performs radix-4 or radix-2 butterfly calculations based on butterfly inputs x0 to x3 and outputs calculation result data X0 to X3. As constituent elements of the butterfly computing unit 3, 10A is a first data buffer for sequentially storing butterfly inputs x0 to x3, 20A is a butterfly input inputted to the butterfly computing unit 3, and a butterfly stored in the first data buffer 10A. A first arithmetic unit that calculates intermediate data based on the input, 30 is a second data buffer that sequentially stores the intermediate data output from the first arithmetic unit 20A, and 40A is the first arithmetic unit 20A. 2 is a second arithmetic unit that performs arithmetic operations on the operation result data X0 to X3 based on the intermediate data output from the intermediate data and the intermediate data stored in the second data buffer 30. 7, components having the same functions as those in FIG. 4 are denoted by the same reference numerals, and detailed description thereof is omitted in the present embodiment.
[0056]
  The butterfly computing unit 3 shown in FIG. 7 is different from the butterfly computing unit 2 shown in FIG. 4 in that the second computing unit 40A performs the radix-2 butterfly computation in the second of the butterfly computing unit 2 shown in FIG. Instead of the third selection circuit 42 in the arithmetic unit 40, a third selection circuit 43 that operates according to the selection signal SC0 is provided.
[0057]
  In the third selection circuit 43, a logical value “0” is added as data to be selected. As shown in FIG. 8, the output data of the second selection circuit 24 (output from the first arithmetic unit 20A). Intermediate data), intermediate data stored in the register 32 of the second data buffer 30, and logical value “0”, when the selection signal SC0 is “0”, the output data of the second selection circuit 24 is When the selection signal SC0 is “1”, the intermediate data stored in the register 32 is selected, and when the selection signal SC0 is “2”, the logical value “0” is selected and output. The second adder / subtractor 41 performs addition when the selection signal SC0 is “0” or “2”, and performs subtraction when the selection signal SC0 is “1”.
[0058]
  When the butterfly calculator 3 performs the radix-4 butterfly calculation, the third selection circuit 43 of the second calculation unit 40A does not select the logical value “0”, and the second and second embodiments according to the first and second embodiments. The same operation as the third selection circuit 42 of the arithmetic unit 40 is performed. On the other hand, when performing radix-2 butterfly computation, the third selection circuit 43 of the second computation unit 40A always selects and outputs the logical value “0”.
[0059]
  FIG. 9 is a diagram showing processing timing when the butterfly computing device shown in FIG. 7 performs radix-2 butterfly computation. As in the first and second embodiments, the input data D0 to D3 are input every cycle, and the operation result data X0 to X3 are output every cycle from the cycle following the input cycle of the input data D3. Each process is a pipeline process, and it is possible to overlap the output of the operation result data X0 to X3 and the input of the next input data D0 to D3. Similarly to the first and second embodiments, the calculation of intermediate data by the first calculation unit 20A is started with a delay of two cycles from the start of the butterfly inputs x0 to x3, and the second calculation unit 40A. The calculation of the calculation result data is started one cycle after the intermediate data calculation by the first calculation unit 20A, that is, three cycles after the start of the butterfly inputs x0 to x3.
[0060]
  The first data buffer 10A, the first arithmetic unit 20A, and the second data buffer 30 operate in the same manner as in the second embodiment. However, the selection signal SS0 is always set to “0” in the radix-2 butterfly computation, and as a result, the output data of the first adder / subtractor 21 is multiplied by the imaginary number j as intermediate data from the first computing unit 20A. Is not output, and the first arithmetic unit 20A outputs (x1-x3) as intermediate data in the final cycle.
[0061]
  In the calculation of the calculation result data by the second calculation unit 40A, the selection signal SC0 is always “2” in the radix-2 butterfly calculation, so that the third selection circuit 43 selectively outputs the logical value “0”. The second adder / subtractor 41 performs addition. As a result, the same value as the intermediate data stored in the first stage register 31 of the second data buffer 30 is output as the operation result data from the second operation unit 40A. That is, x0 + x2 (= X0), x1 + x3 (= X1), x0-x2 (= X2), and x1-x3 (= X3) are output from the second calculation unit 40A as calculation result data.
[0062]
  When performing radix-4 butterfly computation, the third selection circuit 43 of the second computation unit 40A is the same as the third selection circuit 42 of the second computation unit 40 according to the first and second embodiments. Therefore, the processing timing is the same as in FIG.
[0063]
  As shown in FIG. 9, the input data is input in the order of D0, D1, D2, and D3, while the operation result data is output in the order of X0, X1, X2, and X3. On the other hand, in the radix-4 butterfly operation, as shown in FIG. 6, the operation result data is output in the order of X0, X2, X1, and X3. When matching the output order of the operation result data between the radix-4 butterfly operation and the radix-2 butterfly operation, the order of the addresses storing the operation result data may be switched.
[0064]
  Through the processing as described above, the butterfly operation device shown in FIG. 7 performs a rotator multiplication and one radix-4 butterfly operation or a rotator multiplication and two radix-2 butterfly operations on the input data D0 to D3. Result data X0 to X3 are calculated.
[0065]
  As described above, according to the present embodiment, one radix-4 butterfly operation or two radixes are provided by providing the third selection circuit 43 in the second arithmetic unit 40A with a function of selecting a logical value 0. Two butterfly calculations can be performed in accordance with the data output timing. That is, a butterfly calculator capable of executing both radix-4 butterfly computation and radix-2 butterfly computation at the same timing can be realized with a simple configuration, and the switching can be performed by simple control.
[0066]
  In the first, second, and third embodiments, each register is a register that stores complex data, and each arithmetic unit is an arithmetic unit for complex data. However, each register is a real part register. It is possible to divide and connect to the imaginary part register and perform the real part operation and the imaginary part operation in a time division manner in each arithmetic unit. In this case, the number of register stages in the first data buffer 10, 10A and the second data buffer 30 is double the number of stages in the above-described embodiment, and each arithmetic unit is half the circuit scale in the above-described embodiment. Circuit scale.
[0067]
  In the second and third embodiments, the multiplier 25 for multiplying by 2 is provided in the first arithmetic unit 20A. Instead of this multiplier 25, a 1-bit shifter for shifting input data by 1 bit to the upper side. May be provided.
[0068]
【The invention's effect】
  As described above, according to the present invention, since the radix-4 butterfly operation is performed by pipeline processing and the arithmetic unit is used in a time-sharing manner, the circuit scale of the arithmetic unit is reduced. In addition, since new intermediate data is calculated using the already calculated intermediate data, the number of register stages of the first data buffer holding the butterfly input is reduced. Furthermore, since the radix-4 and radix-2 butterfly computations can be executed by a common computing unit, an increase in the circuit scale of the computing unit is suppressed. Therefore, a butterfly computing unit with a small circuit scale can be realized.
[0069]
  In addition, since the output timing of the operation result data of one radix-4 butterfly operation and two radix-2 butterfly operations can be matched, the butterfly operation unit according to the present invention can be used to repeat the butterfly operation in the fast Fourier transform device. Control of calculation becomes easy.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a butterfly computing device including a butterfly computing unit according to a first embodiment of the present invention.
FIGS. 2A to 2C are diagrams illustrating the operation of a selection circuit according to the first embodiment of the present invention.
FIG. 3 is a diagram illustrating processing timing of the butterfly arithmetic device according to the first embodiment of the present invention.
FIG. 4 is a configuration diagram of a butterfly computing device including a butterfly computing unit according to a second embodiment of the present invention.
FIGS. 5A and 5B are diagrams illustrating an operation of a selection circuit according to a second embodiment of the present invention.
FIG. 6 is a diagram showing processing timing of a butterfly arithmetic device according to a second embodiment of the present invention.
FIG. 7 is a configuration diagram of a butterfly computing device including a butterfly computing unit according to a third embodiment of the present invention.
FIG. 8 is a diagram illustrating an operation of a selection circuit according to a third embodiment of the present invention.
FIG. 9 is a diagram illustrating processing timing of the butterfly arithmetic device according to the third embodiment of the present invention.
FIGS. 10A and 10B are diagrams illustrating butterfly computation executed by the butterfly computation device;
[Explanation of symbols]
1,2,3 Butterfly calculator
10, 10A first data buffer
11, 12, 13, 14 registers
20, 20A first calculation unit
21 First adder / subtracter
23 First selection circuit
24 Second selection circuit
26 Fourth selection circuit
30 Second data buffer
31, 32 registers
40, 40A second arithmetic unit
41 Second adder / subtracter
42, 43 Third selection circuit

Claims (5)

The radix-4 butterfly operation is
X0 = (x0 + x2) + (x1 + x3)
X1 = (x0−x2) + j (x1−x3)
X2 = (x0 + x2)-(x1 + x3)
X3 = (x0−x2) −j (x1−x3)
(However, x0, x1, x2, and x3 are butterfly inputs, and X0, X1, X2, and X3 are operation result data)
A butterfly calculator that performs pipeline processing according to
A first data buffer for sequentially storing input butterfly inputs;
A first calculation unit that calculates x0 + x2, x1 + x3, x0-x2, j (x1-x3) for each cycle based on at least a butterfly input stored in the first data buffer;
A second data buffer for sequentially storing the intermediate data calculated by the first calculation unit;
A second calculation unit that calculates calculation result data for each cycle based on at least the intermediate data stored in the second data buffer;
The butterfly computing unit, wherein the first computing unit performs computation using intermediate data stored in the second data buffer. The butterfly computing unit according to claim 1 .
The first data buffer includes two registers connected in series for sequentially shifting the butterfly input every cycle,
The second data buffer includes two registers connected in series for sequentially shifting the intermediate data every cycle.
The first calculation unit includes:
A first selection circuit that selectively outputs one of the butterfly input input to the butterfly calculator and the intermediate data stored in the second stage register of the second data buffer;
A fourth selection circuit that selectively outputs one of the butterfly input stored in the second stage register of the first data buffer and the butterfly input multiplied by 2;
A first adder / subtractor for adding or subtracting the output data of the fourth selection circuit to the output data of the first selection circuit;
A second selection circuit that selectively outputs one of the output data of the first adder / subtractor and the output data multiplied by an imaginary number j as intermediate data;
The second calculation unit includes:
A third selection circuit that selectively outputs any one of the intermediate data output from the first arithmetic unit and the intermediate data stored in the second stage register of the second data buffer;
The second selection circuit adds or subtracts the butterfly input stored in the first stage register of the second data buffer to the output data of the third selection circuit, and outputs the addition or subtraction result as operation result data. A butterfly arithmetic unit comprising: an adder / subtractor. When performing radix-4 butterfly computation,
X0 = (x0 + x2) + (x1 + x3)
X1 = (x0−x2) + j (x1−x3)
X2 = (x0 + x2)-(x1 + x3)
X3 = (x0−x2) −j (x1−x3)
(However, x0, x1, x2, x3 butterfly input, X0, X1, X2, X3 are the operation result data)
A butterfly calculator that performs pipeline processing according to
A first data buffer for storing the input butterfly input;
A first calculation unit that calculates x0 + x2, x1 + x3, x0-x2, j (x1-x3) for each cycle based on at least a butterfly input stored in the first data buffer;
A second data buffer for storing intermediate data calculated by the first calculation unit;
A second calculation unit that calculates calculation result data for each cycle based on at least the intermediate data stored in the second data buffer;
When performing radix-2 butterfly computation, the first computation unit can compute x0 + x2, x1 + x3, x0-x2, and x1-x3 for each cycle as intermediate data.
The second calculation unit adds 0 and outputs the same value as the input intermediate data as calculation result data.
The butterfly computing unit performs two radix-2 butterfly computations using the following formula: X0 = x0 + x2
X1 = x1 + x3
X2 = x0-x2
X3 = x1-x3
Butterfly operation unit, wherein the <br/> be performed according. The butterfly calculator according to claim 3 ,
The first data buffer comprises four registers connected in series for sequentially shifting the butterfly input every cycle;
The second data buffer includes two registers connected in series for sequentially shifting the intermediate data every cycle.
The first calculation unit includes:
A first selection circuit that selectively outputs one of the butterfly input input to the butterfly computing unit and the butterfly input stored in the fourth stage register of the first data buffer;
A first adder / subtracter for adding or subtracting a butterfly input stored in a second stage register of the first data buffer to the output data of the first selection circuit;
A second selection circuit that selectively outputs one of the output data of the first adder / subtractor and the output data multiplied by an imaginary number j as intermediate data;
The second calculation unit includes:
Third selection for selectively outputting any one of the intermediate data output from the first arithmetic unit, the intermediate data stored in the second stage register of the second data buffer, and the logical value “0” Circuit,
The second selection circuit adds or subtracts the butterfly input stored in the first stage register of the second data buffer to the output data of the third selection circuit, and outputs the addition or subtraction result as operation result data. A butterfly arithmetic unit comprising: an adder / subtractor. The butterfly calculator according to claim 3 ,
The first data buffer includes two registers connected in series for sequentially shifting the butterfly input every cycle,
The second data buffer includes two registers connected in series for sequentially shifting the intermediate data every cycle.
The first calculation unit includes:
A first selection circuit that selectively outputs one of the butterfly input input to the butterfly calculator and the intermediate data stored in the second stage register of the second data buffer;
A fourth selection circuit that selectively outputs one of the butterfly input stored in the second stage register of the first data buffer and the butterfly input multiplied by 2;
A first adder / subtractor for adding or subtracting the output data of the fourth selection circuit to the output data of the first selection circuit;
A second selection circuit that selectively outputs one of the output data of the first adder / subtractor and the output data multiplied by an imaginary number j as intermediate data;
The second calculation unit includes:
Third selection for selectively outputting any one of the intermediate data output from the first arithmetic unit, the intermediate data stored in the second stage register of the second data buffer, and the logical value “0” Circuit,
The second selection circuit adds or subtracts the butterfly input stored in the first stage register of the second data buffer to the output data of the third selection circuit, and outputs the addition or subtraction result as operation result data. A butterfly arithmetic unit comprising: an adder / subtractor.

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