JPH113997A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a very fine and high speed semiconductor device with high yield. SOLUTION: A sidewall spacer is formed on a polycrystalline Si layer 43 and a SiO2 film 44 by a SiN film 47. The SiO2 film 44 is removed, and a groove 48 is formed. High-melting point metal silicide layers 53b are formed on the surfaces of the polycrystalline Si layer 43 and a Si substrate 41. The groove 48 is filled which a SiO2 film 56, and an interlayer insulating film is formed of a SiN film 57 and a SiO2 system film 54. Then, a contact hole 55 is formed. Although the high-melting point metallic silicide layers 53b and the contact hole 55 are formed in a self-aligned manner, the polycrystalline Si layer 43 and the like are not exposed, even if the position of the contact hole 55 shifts. Then, the Si substrate 41 and the polycrystalline Si layer 43 are not shorted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device utilizing a self-alignment technique.

[0002]

2. Description of the Related Art A self-alignment technique that does not require a sufficient mask alignment margin is one of the important techniques for miniaturization and high-speed semiconductor devices. FIG. 3 shows a first conventional example of a method of manufacturing a semiconductor device utilizing such a self-alignment technique. In this first conventional example, as shown in FIG. 3A, SiO _{2 is} formed on the surface of a Si substrate 11 as a gate insulating film.
Forming a film 12, a polycrystalline S on such the SiO ₂ film 12
An i-layer 13 is formed.

After that, the polycrystalline Si layer 13 and the SiO ₂ film 12 are processed into a gate electrode pattern.
LDD by impurity ion implantation using the layer 13 etc. as a mask
The low concentration diffusion layer 14 for the source / drain of
Formed on the substrate 11. Then, an SiO ₂ film 15 is deposited on the entire surface, and the entire surface of the SiO ₂ film 15 is etched back.
The side wall spacer made of this SiO ₂ film 15 is made of polycrystalline Si.
It is formed on the side surface of the layer 13.

Thereafter, a high concentration diffusion layer 16 for source / drain having an LDD structure is formed on the Si substrate 11 by ion implantation of impurities using the polycrystalline Si layer 13 and the SiO ₂ film 15 as a mask. Next, as shown in FIG. 3B, a refractory metal layer 17 is deposited on the entire surface, and the Si substrate 11 and the polycrystalline Si layer 13 are reacted with the refractory metal layer 17 by low-temperature annealing to form a Si substrate. A refractory metal silicide layer 18a is formed on the surface of the polycrystalline Si layer 13 and the surface of the polycrystalline Si layer 13.

Next, as shown in FIG. 3C, the refractory metal layer 17 remaining unreacted on the SiO ₂ film
Is removed, high-temperature annealing causes a phase transition in the high-melting-point metal silicide layer 18a to turn the high-melting-point metal silicide layer 18a into a low-resistance high-melting-point metal silicide layer 18b. In the first conventional example described above, the refractory metal silicide layer 18b can be formed on the surface of the Si substrate 11 and the surface of the polycrystalline Si layer 13 in a self-aligned manner.

FIG. 4 shows a second conventional example of a method of manufacturing a semiconductor device utilizing a self-alignment technique. In the second conventional example, as shown in FIG. 4A, an SiO ₂ film 22 is formed on a surface of a Si substrate 21 as a gate insulating film. Then, a polycrystalline Si layer 23 and an offset SiO ₂ film 24 are sequentially formed on the SiO ₂ film 22 and the like, and the SiO ₂ film 24, the polycrystalline Si layer 23, and the SiO ₂ film 22 are patterned as gate electrodes. Process into

Next, as shown in FIG. 4B, a low concentration diffusion layer 25 for source / drain of LDD structure is formed on the Si substrate 21 by ion implantation of impurities using the SiO ₂ film 24 or the like as a mask. Form. Then, an SiO ₂ film 26 is deposited on the entire surface, the entire surface of the SiO ₂ film 26 is etched back, and side wall spacers made of the SiO ₂ film 26 are formed on the side surfaces of the polycrystalline Si layer 23 and the SiO ₂ film 24.

Thereafter, a high concentration diffusion layer 27 for source / drain of LDD structure is formed on the Si substrate 21 by ion implantation of impurities using the SiO ₂ films 24 and 26 as a mask. Next, as shown in FIG.
An O ₂ -based film 31 is sequentially deposited on the entire surface to form an interlayer insulating film, and the Si substrate 21 is used as a stopper with the SiN film 28 as a stopper.
SiO ₂ based film 3 with contact hole 32 pattern
1 is etched.

Although not shown, S
SiN using the SiO ₂ film 26 and the Si substrate 21 as stoppers
The contact hole 32 is completed by etching the film 28. In the above second conventional example, as shown in FIG.
Position of the contact hole 32 is deviated, even if the contact hole 32 is spread to on the SiO ₂ film 26, since the SiO ₂ film 26 is not etched, forms a self-aligned manner the contact holes 32 with respect to polycrystalline Si layer 23 can do.

FIG. 5 shows a third conventional example of a method of manufacturing a semiconductor device utilizing a self-alignment technique, in which a refractory metal silicide layer is formed in a self-aligning manner on the surface of a semiconductor substrate and the surface of a gate electrode. A technique proposed by the inventor of the present application in Japanese Patent Application Laid-Open No. 7-16581 to form a contact hole in a self-aligned manner with respect to a gate electrode is shown.

In the third conventional example, as shown in FIG. 5A, a 6-nm thick gate insulating film is formed on the surface of an Si substrate 41.
An m ₂ SiO ₂ film 42 is formed. And the SiO ₂ film 4
2 and the like, a polycrystalline Si layer 43 having a thickness of 150 nm and a SiO ₂ film 44 having a thickness of 150 nm for offset are sequentially formed, and the SiO ₂ film 44, the polycrystalline Si layer 43, and the SiO ₂ film
The film 42 is processed into a gate electrode pattern.

Thereafter, the surface of the Si substrate 41 and the polycrystalline S
An SiO ₂ film 45 is formed on the side surface of the i-layer 43 by thermal oxidation.
By ion implantation of impurities using the iO ₂ film 44 etc. as a mask,
Lightly doped diffusion layer 46 for source / drain of LDD structure
Is formed on the Si substrate 41. Next, as shown in FIG. 5B, an SiN film 47 having a thickness of 300 nm is deposited on the entire surface by the CVD method, and the entire surface of the SiN film 47 is etched back, so that a large number of side wall spacers made of the SiN film 47 are formed. Crystal Si layer 4
3 and the side surfaces of the SiO ₂ film 44.

Next, as shown in FIG. 5C, the SiO ₂ film 44 and the SiO ₂ film 4 exposed on the surface of the Si substrate 41 are formed.
5 and the like are removed with diluted hydrofluoric acid or the like to form a groove 48 on the polycrystalline Si layer 43 and expose the surface of the Si substrate 41.

[0014] At this time, it is SiN film 47 is not etched, because the element SiO ₂ film of the isolation region (not shown) or the like is etched, area to prevent etching by dilute hydrofluoric acid or the like is to be covered with a resist Is desirable.
Thereafter, a high concentration diffusion layer 51 for the source / drain of the LDD structure is formed on the Si substrate 41 by ion implantation of impurities using the polycrystalline Si layer 43 and the SiN film 47 as a mask.

Next, as shown in FIG. 5D, a refractory metal layer 52 such as a Ti layer is deposited on the entire surface by sputtering or the like.
Then, as shown in FIG. 5E, the Si substrate 41 and the polycrystalline Si layer 43 are reacted with the refractory metal layer 52 by low-temperature annealing at about 600 ° C., so that the surface of the Si substrate 41 and the polycrystalline Si layer A refractory metal silicide layer 53a is formed on the surface of the substrate 43.

Next, as shown in FIG.
After removing the refractory metal layer 52 remaining unreacted on the layer 7 and the like, a phase transition is caused in the refractory metal silicide layer 53a by high-temperature annealing at about 800 ° C. To a low-resistance refractory metal silicide layer 53b.

Next, as shown in FIG. 5 (g), an SiO ₂ -based film 54 is deposited on the entire surface to form an interlayer insulating film.
A contact hole 55 for the Si substrate 41 is formed in the SiO ₂ -based film 54 by etching using the film 47 as a stopper.

[0018]

However, in the third conventional example shown in FIG. 5, as shown in FIG. 6, the position of the contact hole 55 is shifted, and the polycrystalline Si layer 43 and the high melting point When the contact hole 55 spreads over the gate electrode formed of the silicide layer 53b, the contact hole 55
Through source / drain electrodes (not shown)
The source / drain diffusion layer 51 and the gate electrode are short-circuited.

For this reason, in the third conventional example shown in FIG.
It has been difficult to manufacture fine and high-speed semiconductor devices with high yield. On the other hand, if a sufficient margin for mask alignment is ensured, it is possible to prevent the contact hole 55 from spreading over the gate electrode even if the position of the contact hole 55 is displaced. Can not do. Accordingly, an object of the present invention is to provide a method capable of manufacturing a fine and high-speed semiconductor device with a high yield.

[0020]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: sequentially stacking a semiconductor layer and a first insulating film on a semiconductor substrate; A step of processing the semiconductor layer into a wiring pattern, and forming side wall spacers of at least a surface portion of a second insulating film having an etching characteristic different from that of the first insulating film on the side surfaces of the semiconductor layer and the first insulating film. Forming a groove on the semiconductor layer by removing the first insulating film after forming the sidewall spacer; and forming a groove on the semiconductor layer at the bottom of the groove and the semiconductor substrate. Forming a compound layer of a semiconductor and a metal on the surface; and filling the groove on the compound layer with a third insulating film having different etching characteristics from at least the surface portion of the second insulating film. , The groove After the filling, a step of sequentially laminating a fourth insulating film having an etching characteristic different from that of the third insulating film and a fifth insulating film having an etching characteristic different from that of the fourth insulating film as an interlayer insulating film. And forming a contact hole for the semiconductor substrate in the fifth and fourth insulating films.

As described above, in the method of manufacturing a semiconductor device according to the first aspect, the etching characteristics of the first insulating film on the semiconductor layer and at least the surface of the second insulating film as the side wall spacer are different from each other. Even if etching is performed without using a mask, the first insulating film can be removed in a self-aligned manner while suppressing etching of the sidewall spacer.

Further, since the compound layer of the semiconductor and the metal is formed after the first insulating film on the semiconductor layer is removed, the compound reaction between the semiconductor and the metal causes not only the surface of the semiconductor substrate but also the wiring pattern. A compound layer of a semiconductor and a metal can also be formed in a self-aligned manner on the surface of the semiconductor layer.

Also, since the etching characteristics of at least the surface of the second insulating film as the side wall spacer and the third insulating film filling the trench on the semiconductor layer are different from each other, after the third insulating film is deposited, Even if etching without using a mask is performed, the third insulating film can be left in a self-aligned manner in the groove on the semiconductor layer without etching the side wall spacer.

On the other hand, since the etching characteristics of the fourth and fifth insulating films, which are the interlayer insulating films, are different from each other, the fourth insulating film is formed at the time of etching the fifth insulating film when forming the contact hole with the semiconductor substrate. It can be a stopper. For this reason, even if the position of the contact hole is shifted and the contact hole spreads over the wiring composed of the semiconductor layer and the compound layer thereon, the etching of the third insulating film on the wiring can be prevented, Exposure of the wiring can be prevented.

Further, since the third insulating film filling the trench on the semiconductor layer and the fourth insulating film which is a part of the interlayer insulating film have different etching characteristics, the fourth insulating film for forming the contact hole is different. Even when the insulating film is etched, the third insulating film on the wiring can be prevented from being etched, and the wiring can be prevented from being exposed.

Further, since the fourth and fifth insulating films sequentially laminated are used as an interlayer insulating film, the thin fourth insulating film and the thick fifth insulating film have a required thickness. Can be formed. For this reason, even if the etching characteristics of at least the surface portion of the second insulating film serving as the side wall spacer and the fourth insulating film which is a part of the interlayer insulating film are not different from each other, the etching may be performed at the time of etching the fourth insulating film. A reduction in the thickness of the second insulating film can be suppressed, and a contact hole for the semiconductor substrate can be formed in a self-aligned manner with respect to the wiring.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming a sixth insulating film having a different material from at least the surface portion of the second insulating film between the semiconductor substrate and the side wall spacer. It is characterized by doing.

As described above, in the method of manufacturing a semiconductor device according to the second aspect, the sixth insulating film having a different material from at least the surface portion of the second insulating film serving as the side wall spacer is formed between the semiconductor substrate and the side wall spacer. Even when a large stress is generated between the semiconductor substrate and the side wall spacers, the sixth insulating film can absorb this stress,
Generation of crystal defects in the semiconductor substrate can be suppressed.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first and second aspects, wherein the seventh insulating film as the surface portion and the seventh insulating film are formed. Is at least 2 including an eighth insulating film made of a different material.
It is characterized in that the second insulating film is constituted by a layer of the insulating film.

As described above, in the method of manufacturing a semiconductor device according to the third and fourth aspects, the side wall spacer is formed by at least two layers of insulating films including the seventh and eighth insulating films of different materials. Even when a large stress is generated between the semiconductor layer of the pattern and the seventh insulating film, the stress can be absorbed by the eighth insulating film and the like, thereby suppressing generation of crystal defects in the semiconductor substrate. can do.

Further, the adhesiveness between the semiconductor layer of the wiring pattern and the seventh insulating film can be enhanced by the eighth insulating film or the like, and peeling of the side wall spacer due to thermal stress or the like in a subsequent step is prevented. be able to.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, first and second embodiments of the present invention applied to the manufacture of a MOS transistor will be described with reference to FIGS. FIG. 1 shows a first embodiment. As shown in FIGS. 1A to 1F, the first embodiment also has a low-resistance refractory metal silicide layer 53b.
Until the step is formed, substantially the same steps as those of the third conventional example shown in FIG. 5 are performed.

However, in the first embodiment,
The SiO ₂ film 56 is deposited on the entire surface by a CVD method, SiO ₂
The entire surface of the film 56 is etched back, and the SiO ₂ film 56 is etched.
To fill the groove 48. Next, as shown in FIG.
An N film 57 and a SiO ₂ film 54 are sequentially deposited on the entire surface to form an interlayer insulating film. Then, the SiO ₂ -based film 54 is etched with the pattern of the contact hole 55, and
The contact hole 55 is completed by etching the iN film 57.

[0034] In the etching of the SiO ₂ based layer 54, since the SiN film 57 is a stopper, SiO ₂ film 5
6 is not etched. In etching the SiN film 57, the SiO ₂ film 56 is not etched,
Since the SiN film 47 is considerably thicker than the SiN film 57,
The decrease in the thickness of the N film 47 is small. The polycrystalline Si layer 4
3 and a contact hole for the gate electrode composed of the refractory metal silicide layer 53b thereon
It is formed in a step different from that of the above.

In the first embodiment as described above, the Si substrate 4
1 and the surface of the polycrystalline Si layer 43, a refractory metal silicide layer 53b is formed in a self-aligning manner, and the polycrystalline S
The contact hole 5 is self-aligned with the gate electrode composed of the i-layer 43 and the refractory metal silicide layer 53b thereon.
5 are formed.

In spite of that, contact hole 5
Even if the contact hole 55 is displaced and the contact hole 55 spreads over the polycrystalline Si layer 43, the polycrystalline Si layer 43 and the refractory metal silicide layer 53b thereon are not exposed, and the contact hole 5
The source / drain diffusion layer 51 and the polycrystalline Si layer 43 do not short-circuit via the source / drain electrodes (not shown) filling the layer 5.

[0037] In the above first embodiment, the SiO ₂ film 45 is interposed between the SiN film 47 and the Si substrate 41 is a sidewall spacer, the Si substrate 41 and SiN
Although the generation of crystal defects in the Si substrate 41 is suppressed by absorbing the stress between itself and the film 47, the SiO ₂ film 45 is not always necessary. In the first embodiment, S
Although iO ₂ film 45 is formed by thermal oxidation, the SiO ₂
An insulating film other than the film 45 and the SiO ₂ film may be formed by the CVD method or both the thermal oxidation and the CVD method.

FIG. 2 shows a step in the middle of the second embodiment, which corresponds to FIG. 1B of the first embodiment. Also in the second embodiment, the SiO ₂ film 4
5 was not formed, and the SiO ₂ film 61 and the SiN film 62 were
Substantially the same steps as those of the first embodiment shown in FIG. Si
The O ₂ film 61 is formed by oxidation or CVD.

In the second embodiment, the stress between the polycrystalline Si layer 43 and the SiN film 62 is absorbed by the SiO ₂ film 61, thereby suppressing the generation of crystal defects in the Si substrate 41. And the deterioration of the SiO ₂ film 42 can be suppressed. Also, the polycrystalline Si layer 43 and the SiN film 62
Can be improved by the SiO ₂ film 61, and peeling of the SiN film 62 due to thermal stress or the like in a subsequent step can be prevented.

In the second embodiment, the polycrystalline S
A part of the SiO ₂ film 61 is removed at the same time by removing the SiO ₂ film 44 when forming the groove 48 on the i-layer 43, and then the removed portion is also removed by the SiO ₂ film 56 for filling the groove 48. There is no particular problem because it is buried at the same time.

In the above-described second embodiment, the side wall spacer is formed by the SiO ₂ film 61 and the SiN film 62 which are two layers of insulating materials different from each other, but the side wall spacer is formed by three or more insulating films. A spacer may be formed. Further, the SiO ₂ film 45 is not formed in the above-described second embodiment, but the SiO ₂ film 45 may be formed similarly to the first embodiment.

In the first and second embodiments,
SiO ₂ films 44, 56, 61 and SiO ₂ based film 54 and S
Two insulating film groups having different etching characteristics, iN films 47, 57, and 62, are used. However, as long as the insulating film groups have different etching characteristics, an insulating film made of a material different from the above-described film may be used. Good.

Further, the first and second embodiments described above have the MO
Although the invention of the present application is applied to the manufacture of an S transistor, the invention of the present application can be applied to the manufacture of a semiconductor device other than a MOS transistor.

[0044]

According to the method of manufacturing a semiconductor device of the present invention, a compound layer of a semiconductor and a metal can be formed in a self-alignment manner not only on the surface of a semiconductor substrate but also on the surface of a semiconductor layer of a wiring pattern. Since a contact hole with respect to the semiconductor substrate can be formed in a self-alignment manner with respect to the wiring, a fine and high-speed semiconductor device can be manufactured.

In spite of this, even if the position of the contact hole with respect to the semiconductor substrate is shifted and the contact hole is extended over the wiring, the exposure of the wiring can be prevented. A short circuit between the semiconductor substrate and the wiring can be prevented, and a semiconductor device can be manufactured with a high yield.

In the method of manufacturing a semiconductor device according to the second aspect, the occurrence of crystal defects in the semiconductor substrate can be suppressed, so that the occurrence of leak current through the crystal defects can be suppressed. A semiconductor device having excellent characteristics can be manufactured.

In the method for manufacturing a semiconductor device according to the third and fourth aspects, the occurrence of crystal defects and the like in the semiconductor substrate can be suppressed, so that the occurrence of leak current and the like via the crystal defects can be suppressed. Since peeling of the side wall spacer can be prevented, a semiconductor device having excellent characteristics can be manufactured with a high yield.

[Brief description of the drawings]

FIG. 1 is a side sectional view showing a first embodiment of the present invention in the order of steps.

FIG. 2 is a side sectional view showing a step in the middle of the second embodiment of the present invention and corresponding to FIG. 1 (b).

FIG. 3 is a side sectional view showing a first conventional example of the present invention in the order of steps.

FIG. 4 is a side sectional view showing a second conventional example of the present invention in the order of steps.

FIG. 5 is a side sectional view showing a third conventional example of the present invention in the order of steps.

FIG. 6 is a side sectional view for explaining a problem of a third conventional example.

[Explanation of symbols]

41: Si substrate (semiconductor substrate), 43: polycrystalline Si layer (semiconductor layer), 44: SiO ₂ film (first insulating film), 4
5: SiO ₂ film (sixth insulating film), 47: SiN film (second insulating film), 48: groove, 53b: refractory metal silicide layer (compound layer), 54: SiO ₂ based film (fifth 55, contact holes, 56, SiO ₂ film (third insulating film), 57, SiN film (fourth insulating film), 61, S
SiO ₂ film (eighth insulating film), 62... SiN film (seventh insulating film)

Claims (4)

[Claims] A step of sequentially laminating a semiconductor layer and a first insulating film on a semiconductor substrate; a step of processing the first insulating film and the semiconductor layer into a wiring pattern; Forming side wall spacers made of a second insulating film having different etching characteristics from the first insulating film on the side surfaces of the semiconductor layer and the first insulating film; and forming the first side wall after forming the side wall spacers. Forming a groove on the semiconductor layer by removing the insulating film, and forming a compound layer of a semiconductor and a metal on the surface of the semiconductor layer and the surface of the semiconductor substrate at the bottom of the groove, A step of filling the groove on the compound layer with a third insulating film having an etching characteristic different from at least the surface portion of the second insulating film; and, after filling the groove, the third insulating film Of etching characteristics A step of sequentially laminating a different fourth insulating film and a fifth insulating film having a different etching characteristic from the fourth insulating film as an interlayer insulating film; and forming contact holes for the semiconductor substrate with the fifth and fourth insulating films. Forming a semiconductor device on the insulating film. 2. The method according to claim 1, further comprising the step of forming a sixth insulating film having a different material from at least the surface portion of the second insulating film between the semiconductor substrate and the side wall spacer. Item 2. A method for manufacturing a semiconductor device according to Item 1. 3. The second insulating film is composed of at least two insulating films including a seventh insulating film serving as the surface portion and an eighth insulating film having a different material from the seventh insulating film. 2. The method for manufacturing a semiconductor device according to claim 1, wherein 4. The second insulating film is composed of at least two insulating films including a seventh insulating film as the surface portion and an eighth insulating film made of a different material from the seventh insulating film. 3. The method of manufacturing a semiconductor device according to claim 2, wherein: