JPH11354845A - Gan compound semiconductor light emitting element - Google Patents
Gan compound semiconductor light emitting elementInfo
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- JPH11354845A JPH11354845A JP16184898A JP16184898A JPH11354845A JP H11354845 A JPH11354845 A JP H11354845A JP 16184898 A JP16184898 A JP 16184898A JP 16184898 A JP16184898 A JP 16184898A JP H11354845 A JPH11354845 A JP H11354845A
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Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、たとえば青色発光
用のLEDに係り、特にn型層との格子整合を最適化し
て用途上で必要とされる発光輝度を小電力で得られるよ
うにしたGaN系化合物半導体発光素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, an LED for emitting blue light, and more particularly to optimizing lattice matching with an n-type layer so as to obtain light emission luminance required for an application with low power. The present invention relates to a GaN-based compound semiconductor light emitting device.
【0002】[0002]
【従来の技術】青色発光のLEDとして、GaN,Ga
AlN,InGaN及びInAlGaN等のGaN系化
合物半導体を利用したものが従来から知られている。こ
のGaN系化合物半導体によるLEDの開発過程では、
化合物半導体の結晶をその表面上に成長させるための基
板の材料が様々に探究されてきたが、主としてサファイ
アが多く採用されている。2. Description of the Related Art GaN, Ga
A device utilizing a GaN-based compound semiconductor such as AlN, InGaN, and InAlGaN has been conventionally known. In the development process of LED using GaN compound semiconductor,
Various materials have been sought for a substrate for growing a compound semiconductor crystal on its surface, and sapphire is mainly used in many cases.
【0003】図2は従来のGaN系化合物半導体発光素
子の一例であって、同図の(a)は外観斜視図、同図の
(b)は概略縦断面図である。FIG. 2 shows an example of a conventional GaN-based compound semiconductor light emitting device. FIG. 2A is an external perspective view, and FIG. 2B is a schematic longitudinal sectional view.
【0004】図において、サファイアを用いた基板51
の上にGaNのn型層52及びGaNのp型層53がそ
れぞれ積層形成され、図示の例ではp型層53の表面に
p側透光性電極54を形成している。そして、このp側
透光性電極54の表面にはp側電極パッド53aを設
け、p型層53の一部をエッチングしてn型層52を露
出させた部分にはn側電極パッド52aを形成してい
る。そして、周知のように、n型層52及びp型層53
は有機金属気相成長法によるエピタキシャル成長により
形成され、p側及びn側の電極パッド53a,52aは
AlやTi等の金属を蒸着法によって形成したものであ
る。In FIG. 1, a substrate 51 using sapphire is shown.
An n-type layer 52 of GaN and a p-type layer 53 of GaN are formed on each other, and a p-side translucent electrode 54 is formed on the surface of the p-type layer 53 in the illustrated example. A p-side electrode pad 53a is provided on the surface of the p-side translucent electrode 54, and an n-side electrode pad 52a is provided on a portion where a part of the p-type layer 53 is etched to expose the n-type layer 52. Has formed. Then, as is well known, the n-type layer 52 and the p-type layer 53
Are formed by epitaxial growth by metalorganic vapor phase epitaxy, and the p-side and n-side electrode pads 53a, 52a are formed by vapor deposition of a metal such as Al or Ti.
【0005】以上は構成の概略であるが、実際には基板
51とn型層52との間に、基板51のサファイアとn
型層52のn型GaNとの格子不整合の緩衝のためのバ
ッファ層を設けるほか、p型クラッド層やp型コンタク
ト層等が形成される。そして、n型層52とp型層53
との間には、たとえばInGaNによる活性層55が形
成され、この活性層55が発光域となる。[0005] The above is an outline of the structure. Actually, between the substrate 51 and the n-type layer 52, the sapphire and n
In addition to providing a buffer layer for buffering lattice mismatch between the mold layer 52 and the n-type GaN, a p-type clad layer, a p-type contact layer, and the like are formed. Then, the n-type layer 52 and the p-type layer 53
An active layer 55 of, for example, InGaN is formed between these layers, and this active layer 55 becomes a light emitting region.
【0006】[0006]
【発明が解決しようとする課題】ところが、基板51を
絶縁性のサファイアとするので、n側及びp側の電極パ
ッド52a,53aはいずれも基板51とは反対側の主
光取出し面側に設けるしかないという制約を受ける。こ
のため、基板51をLEDランプのリードフレームやデ
ィスプレイパネル等のプリント基板に搭載するアセンブ
リの場合では、これらのn側及びp側の電極パッド52
a,53aの両方にワイヤをボンディングすることが必
要となる。したがって、アセンブリの工程数が多くなる
ほか、ワイヤが発光素子の上側に大きく張り出すので、
樹脂封止した後のチップLED等の製品の薄型化にも限
界がある。However, since the substrate 51 is made of insulating sapphire, both the n-side and p-side electrode pads 52a and 53a are provided on the main light extraction surface side opposite to the substrate 51. There is a restriction that there is only. Therefore, in the case of an assembly in which the board 51 is mounted on a printed board such as a lead frame of an LED lamp or a display panel, these n-side and p-side electrode pads 52
It is necessary to bond wires to both a and 53a. Therefore, the number of assembly steps is increased, and the wire protrudes greatly above the light emitting element.
There is also a limit in thinning products such as chip LEDs after resin sealing.
【0007】また、基板51のサファイアとn型層52
のn型GaNとの間には、格子不整合や熱膨張率の差が
ある。そして、これらの要因を吸収して結晶度の高いエ
ピタキシャル層を成長させるためにバッファ層を設ける
ようにしているが、現在のところこのようなバッファ層
を備えていても高結晶度のエピタキシャル層の成長は得
られていない。したがって、主として格子不整合によ
り、活性層55による発光輝度に少なからず影響を及ぼ
すことになる。The sapphire of the substrate 51 and the n-type layer 52
There is a lattice mismatch and a difference in coefficient of thermal expansion between the n-type GaN and the n-type GaN. A buffer layer is provided to absorb these factors and grow an epitaxial layer having a high crystallinity. However, even if such a buffer layer is provided at present, a high crystallinity epitaxial layer cannot be formed. No growth has been obtained. Therefore, mainly due to the lattice mismatch, the luminance of light emitted by the active layer 55 is affected to some extent.
【0008】一方、LEDを利用した発光表示装置で
は、それぞれの用途に応じた発光輝度が得られることが
大前提であるが、たとえば携帯電話等のように消費電力
を小さくすることが要求される場合が多い。この消費電
力の削減は、発光素子を小さくして電流を絞り込むこと
で或る程度は対応可能である。On the other hand, in a light emitting display device using an LED, it is a major premise that a light emission luminance corresponding to each application can be obtained. However, it is required to reduce power consumption as in a mobile phone, for example. Often. This reduction in power consumption can be dealt with to some extent by reducing the size of the light emitting element and narrowing down the current.
【0009】ところが、図2に示したGaN系化合物半
導体を利用した発光素子でも、基板51をウエハー状態
としてこれにn型GaNやp型GaNを成長させた後
に、ダイサーによってチップ状にダイシングする工程を
踏む。このダイシングはダイヤモンドブレードの回転に
よる剪断を利用した機械的なものなので、ダイシングで
きるチップの大きさには下限がある。また、ダイシング
した後にチップをリードフレームに載せる工程において
も、チップが余りにも小さいとハンドリングがし難くな
り、製品の歩留りにも影響を及ぼす。したがって、発光
素子を小さくすることによって消費電力を削減しようと
しても、現段階では製造面での適切な対応ができない。However, even in the light emitting device using the GaN-based compound semiconductor shown in FIG. 2, the substrate 51 is formed into a wafer state, and n-type GaN or p-type GaN is grown thereon, and then dicing is performed by a dicer into chips. Step on. Since this dicing is mechanical using shearing due to the rotation of a diamond blade, there is a lower limit to the size of a chip that can be diced. Also, in the process of mounting the chip on the lead frame after dicing, if the chip is too small, it becomes difficult to handle and the product yield is affected. Therefore, even if an attempt is made to reduce the power consumption by reducing the size of the light emitting element, it is not possible at the present stage to take appropriate measures in terms of manufacturing.
【0010】以上のように、サファイアを基板51とし
て備えるGaN系化合物半導体の発光素子では、特に小
型で消費電力が小さいことが要求される発光表示装置に
ついて最適化しようとしても、発光輝度や消費電力及び
アセンブリのそれぞれの面において改善すべき問題が残
っている。As described above, in the GaN-based compound semiconductor light-emitting device having sapphire as the substrate 51, even if it is desired to optimize a light-emitting display device which is particularly required to be small in size and low in power consumption, the luminous luminance and power consumption cannot be improved. And problems remain to be improved in each aspect of the assembly.
【0011】本発明において解決すべき課題は、消費電
力が小さくて用途に応じた適正な発光輝度が得られしか
も薄型化が可能なGaN系化合物半導体発光素子を提供
することにある。It is an object of the present invention to provide a GaN-based compound semiconductor light-emitting device which consumes a small amount of power, has an appropriate emission luminance according to the intended use, and can be made thin.
【0012】[0012]
【課題を解決するための手段】本発明のGaN系化合物
半導体発光素子は、n型不純物をドープしたGaNを素
材とする基板と、この基板の一面側に形成したn電極
と、前記基板の他面側に順に積層したGaNのn型層,
活性層及びGaNのp型層と、このp型層の上に形成し
たp電極とを備え、前記p型層の表面から前記活性層を
貫いて前記n型層の上端の内部まで達する深さを持ち且
つ平面形状が閉じた環を形成する溝を設け、この溝に囲
まれた部分をメサとするとともにこのメサの表面に前記
p電極を導通配置してなることを特徴とする。A GaN-based compound semiconductor light-emitting device according to the present invention comprises a substrate made of GaN doped with an n-type impurity, an n-electrode formed on one surface of the substrate, An n-type GaN layer sequentially stacked on the surface side,
An active layer and a p-type layer of GaN, and a p-electrode formed on the p-type layer, and a depth reaching from the surface of the p-type layer to the inside of the upper end of the n-type layer through the active layer. And a groove that forms a ring having a closed planar shape is provided, a portion surrounded by the groove is used as a mesa, and the p-electrode is conductively arranged on the surface of the mesa.
【0013】[0013]
【発明の実施の形態】請求項1に記載の発明は、n型不
純物をドープしたGaNを素材とする基板と、この基板
の一面側に形成したn電極と、前記基板の他面側に順に
積層したGaNのn型層,活性層及びGaNのp型層
と、このp型層の上に形成したp電極とを備え、前記p
型層の表面から前記活性層を貫いて前記n型層の上端の
内部まで達する深さを持ち且つ平面形状が閉じた環を形
成する溝を設け、この溝に囲まれた部分をメサとすると
ともにこのメサの表面に前記p電極を導通配置してなる
ものであり、発光素子に形成される発光層の全体ではな
く一部を占めるメサ部分を発光領域として集約して電流
密度を上げるので、供給電流が少なくても輝度が高い発
光が得られる。また、溝の外の活性層からは光の放出が
ないので、発光素子の主光取出し面方向のみへの光の照
射が得られる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 is a method of forming a substrate made of GaN doped with an n-type impurity, an n-electrode formed on one surface of the substrate, and another surface of the substrate in this order. An n-type layer of GaN, an active layer, a p-type layer of GaN, and a p-electrode formed on the p-type layer;
A groove having a depth extending from the surface of the mold layer to the inside of the upper end of the n-type layer through the active layer and forming a closed ring having a closed planar shape is provided, and a portion surrounded by the groove is used as a mesa. In addition, the p-electrode is conductively arranged on the surface of the mesa, and the current density is increased by consolidating the mesa portion occupying a part, not the entire light emitting layer formed in the light emitting element, as a light emitting region, Light emission with high luminance can be obtained even with a small supply current. In addition, since no light is emitted from the active layer outside the groove, light can be emitted only in the main light extraction surface direction of the light emitting element.
【0014】請求項2に記載の発明は、前記p型層の平
面形状の大きさと前記p電極が占める平面積との大きさ
との間に、前記p電極の周りで前記溝の幅及び環の長さ
を変更可能とする関係を持たせてなる請求項1記載のG
aN系化合物半導体発光素子であり、メサの平面積を自
由に変えることができるので、発光素子の大きさは一様
であってもその発光面積だけを変えた仕様の製品が得ら
れる。According to a second aspect of the present invention, the width of the groove and the width of the ring around the p-electrode are between the size of the planar shape of the p-type layer and the size of the plane area occupied by the p-electrode. 2. The G according to claim 1, wherein the length is changeable.
Since it is an aN-based compound semiconductor light emitting device and the plane area of the mesa can be freely changed, a product having a specification in which only the light emitting area is changed even if the size of the light emitting device is uniform can be obtained.
【0015】以下に、本発明の実施の形態の具体例を図
面を参照しながら説明する。図1は本発明の一実施の形
態によるGaN系化合物半導体発光素子の概略であっ
て、同図の(a)は平面図、同図の(b)は縦断面図で
ある。Hereinafter, specific examples of the embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a schematic view of a GaN-based compound semiconductor light-emitting device according to an embodiment of the present invention. FIG. 1A is a plan view, and FIG. 1B is a longitudinal sectional view.
【0016】図において、本発明の発光素子は、n型の
GaNを用いた基板1を備え、この基板1の表面にバッ
ファ層等を介在させずにGaNのn型層2を形成し、こ
のn型層2の表面にInGaNの活性層3及びGaNの
p型層4を積層したものである。Referring to FIG. 1, the light emitting device of the present invention includes a substrate 1 using n-type GaN, and forms an GaN n-type layer 2 on the surface of the substrate 1 without interposing a buffer layer or the like. An active layer 3 of InGaN and a p-type layer 4 of GaN are laminated on the surface of an n-type layer 2.
【0017】n型層2,活性層3,p型層4は従来例と
同様に有機金属気相成長法によって結晶を成長させて成
膜されたものである。そして、この気相成長の過程で、
GaNをn型化してn型層2とするためにn型不純物と
してSiやGe等をドープし、GaNをp型化してp型
層4とするためにp型不純物としてMgやZnがドープ
される。なお、p型層4としては、p型クラッド層とp
型コンタクト層に別けて形成することもできる。The n-type layer 2, the active layer 3, and the p-type layer 4 are formed by growing crystals by a metal organic chemical vapor deposition method as in the conventional example. And in the course of this vapor phase growth,
Si or Ge is doped as an n-type impurity to make GaN n-type to form an n-type layer 2, and Mg or Zn is doped as a p-type impurity to make GaN p-type to form a p-type layer 4. You. The p-type layer 4 includes a p-type cladding layer and a p-type cladding layer.
It can also be formed separately for the mold contact layer.
【0018】n型GaNの基板1はGaNの結晶にn型
不純物としてSiやGe等をドープした導電材であり、
その下面にはたとえばAlまたはTi等を蒸着法によっ
て薄膜形成したn電極5を備えている。このn電極5は
基板1の底面のほぼ全体に形成され、たとえばLEDラ
ンプのリードフレームに搭載する場合では、Agペース
ト等の導電性の接着剤によって導通固定する。The n-type GaN substrate 1 is a conductive material in which GaN crystals are doped with n-type impurities such as Si and Ge.
The lower surface is provided with an n-electrode 5 formed of a thin film of, for example, Al or Ti by an evaporation method. The n-electrode 5 is formed on almost the entire bottom surface of the substrate 1 and, for example, when mounted on a lead frame of an LED lamp, is conductively fixed by a conductive adhesive such as Ag paste.
【0019】一方、p電極6はp型層4の表面であっ
て、額縁状の溝7によって包囲されたメサ8に含まれた
部分に形成する。このp電極6はAlやTi等を蒸着法
によってパッド状に形成されたもので、その上面に導通
用のAu等を利用したワイヤ(図示せず)がボンディン
グされる。すなわち、LEDランプのリードフレームの
搭載面側にn電極5が導通し、p電極6はワイヤによっ
て他方のリードに導通させることによって、p電極6か
らn電極5側へを順方向とする電流を印加することがで
きる。On the other hand, the p-electrode 6 is formed on the surface of the p-type layer 4 at a portion included in the mesa 8 surrounded by the frame-shaped groove 7. The p-electrode 6 is formed by depositing Al, Ti, or the like into a pad by an evaporation method, and a wire (not shown) using Au or the like for conduction is bonded to the upper surface thereof. That is, the n-electrode 5 is electrically connected to the mounting surface side of the lead frame of the LED lamp, and the p-electrode 6 is electrically connected to the other lead by a wire, so that a current flowing in the forward direction from the p-electrode 6 to the n-electrode 5 is provided. Can be applied.
【0020】溝7はp型層4の表面から活性層3を貫い
てn型層2の上端まで入り込む深さを持ち、この溝7に
よって包囲されたメサ8の活性層3は溝7の外の活性層
3とは分断されている。なお、溝7の形成にはドライエ
ッチング法やレーザ光を用いる加工及びダイサーによる
ダイシング加工等で対応できる。The groove 7 has a depth penetrating from the surface of the p-type layer 4 to the upper end of the n-type layer 2 through the active layer 3, and the active layer 3 of the mesa 8 surrounded by the groove 7 is outside the groove 7. From the active layer 3. The groove 7 can be formed by dry etching, processing using laser light, dicing with a dicer, or the like.
【0021】以上の構成において、発光素子をLEDラ
ンプやチップLEDとしてアセンブリするときには、リ
ードフレームや配線パターンの搭載面にn電極5を導電
性の接着剤等によって導通固定し、1本のワイヤをp電
極6にボンディングするだけで済む。このため、従来の
絶縁性のサファイアを基板としたp側及びn側のそれぞ
れにワイヤをボンディングするアセンブリに比べると、
工程数を減らすことができる。また、ワイヤを含めた高
さ寸法が抑えられるので、最終的に樹脂封止されて製品
化されるLEDランプやチップLEDの薄型化も可能と
なる。In the above configuration, when the light emitting element is assembled as an LED lamp or a chip LED, the n-electrode 5 is conductively fixed to the mounting surface of the lead frame or the wiring pattern with a conductive adhesive or the like, and one wire is connected. It only needs to be bonded to the p-electrode 6. For this reason, compared with the conventional assembly in which wires are respectively bonded to the p-side and the n-side using a substrate made of insulating sapphire,
The number of steps can be reduced. Further, since the height including the wires is suppressed, it is possible to reduce the thickness of LED lamps and chip LEDs that are finally resin-sealed and commercialized.
【0022】基板1はn型のGaNであるため、基板1
の上にバッファ層を介在させないままでも、n型GaN
のn型層2との格子整合性を高めることができるととも
に熱膨張の差も無視し得る程度に抑えられる。したがっ
て、基板1の上にはバッファ層を介さない結晶度の高い
n型層2のエピタキシャル層が得られるので、このn型
層2の上に形成される活性層3のエピタキシャル層も結
晶度の高い層となり、活性層3の発光輝度の向上が可能
となる。Since the substrate 1 is made of n-type GaN,
N-type GaN without a buffer layer
Can be improved in lattice matching with the n-type layer 2 and the difference in thermal expansion can be suppressed to a negligible level. Therefore, an epitaxial layer of n-type layer 2 having a high degree of crystallinity without interposing a buffer layer is obtained on substrate 1, and the epitaxial layer of active layer 3 formed on n-type layer 2 also has a high degree of crystallinity. It becomes a high layer, and the emission luminance of the active layer 3 can be improved.
【0023】また、p電極6はメサ8のほぼ中央に位置
しているので、n電極5側への電流はこのメサ8に含ま
れた部分に集中し、溝7の外側の活性層3には通過電流
が発生しない。したがって、溝7の外側の活性層3から
の発光成分はなく、メサ8の表面部分だけが発光域とな
る。すなわち、発光素子の全体の平面形状に対して中央
部の限られた狭いメサ8の領域を発光面とするだけの通
電量での発光が可能なので、消費電力を削減できる。こ
のため、消費電力を削減できるように発光素子の全体を
小さくしないままで済み、発光素子の製造過程において
ダイサーによるダイシングやその他のハンドリングに支
障をきたすことはなく、製品歩留りへの影響もない。Since the p-electrode 6 is located substantially at the center of the mesa 8, the current flowing to the n-electrode 5 is concentrated on the portion included in the mesa 8, and the current flows to the active layer 3 outside the groove 7. Does not generate a passing current. Therefore, there is no light emitting component from the active layer 3 outside the groove 7, and only the surface portion of the mesa 8 becomes a light emitting region. In other words, light emission can be performed with an amount of electricity sufficient to make the area of the narrow mesa 8 having a limited central portion as a light emitting surface with respect to the entire planar shape of the light emitting element, so that power consumption can be reduced. For this reason, the entire light-emitting element does not have to be small so that power consumption can be reduced. In the process of manufacturing the light-emitting element, dicing by a dicer or other handling is not hindered, and the product yield is not affected.
【0024】更に、p電極6からn電極5に向かう電流
は活性層3部分ではその電流密度が高いので、活性層3
のエネルギ励起が促され、発光輝度を上げることができ
る。したがって、メサ8部分だけが発光領域であってし
かも通電量を小さくしても、所定の輝度の発光を得るこ
とができ、たとえば消費電力を小さく抑えるとともに発
光輝度も或る程度のものが得られれば十分に使用できる
ようなタイプの表示装置に最適に利用できる。Further, the current flowing from the p electrode 6 to the n electrode 5 has a high current density in the active layer 3 portion.
Is excited, and the light emission luminance can be increased. Therefore, even if only the mesa 8 is a light emitting area and the amount of current is small, light emission of a predetermined luminance can be obtained. For example, power consumption can be suppressed and light emission luminance can be obtained to some extent. It can be optimally used for a type of display device that can be used sufficiently.
【0025】[0025]
【発明の効果】請求項1に記載の発明では、n型不純物
をドープしたGaNを基板とするので、これに積層する
n型GaNのn型層との格子整合が高くしかも熱膨張の
差も無視し得るので、活性層による発光輝度を向上させ
ることができ、バッファ層等も不要なので半導体薄膜の
積層工程数も削減される。また、発光層の全体ではなく
一部を占めるメサ部分を発光領域として集約して電流密
度を上げるので、供給電流が少なくても輝度が高い発光
が得られ、消費電力を低減できる。そして、この消費電
力の低減のために発光素子の全体を小型にする必要もな
く、従来の製造設備のままでのアセンブリで対応でき
る。更に、溝の外の活性層からの発光がないので、発光
素子の側方に抜ける光はなく、主光取出し面からだけの
発光とすることができる。According to the first aspect of the present invention, since GaN doped with an n-type impurity is used as the substrate, the lattice matching with the n-type GaN layer stacked thereon is high and the difference in thermal expansion is small. Since it can be neglected, the luminance of light emission by the active layer can be improved, and the number of semiconductor thin film laminating steps can be reduced since a buffer layer and the like are not required. Further, the mesa portion occupying a part of the light emitting layer, not the whole, is concentrated as a light emitting region to increase the current density, so that light emission with high luminance can be obtained even with a small supply current, and power consumption can be reduced. In addition, there is no need to reduce the size of the entire light emitting element in order to reduce the power consumption, and an assembly using conventional manufacturing equipment can be used. Furthermore, since there is no light emission from the active layer outside the groove, no light escapes to the side of the light emitting element, and light can be emitted only from the main light extraction surface.
【0026】請求項2に記載の発明では、メサの面積を
自由に変更できるので発光面積が異なる仕様の製品が得
られる。According to the second aspect of the present invention, the area of the mesa can be freely changed, so that a product having a different light emitting area can be obtained.
【図1】(a)は本発明の一実施の形態における化合物
半導体発光素子の平面図 (b)は上図(a)の縦断面図FIG. 1A is a plan view of a compound semiconductor light emitting device according to an embodiment of the present invention. FIG. 1B is a longitudinal sectional view of FIG.
【図2】(a)は従来の化合物半導体発光素子の概略斜
視図 (b)は上図(a)の縦断面図2A is a schematic perspective view of a conventional compound semiconductor light emitting device, and FIG. 2B is a longitudinal sectional view of FIG.
1 基板 2 n型層 3 活性層 4 p型層 5 n電極 6 p電極 7 溝 8 メサ Reference Signs List 1 substrate 2 n-type layer 3 active layer 4 p-type layer 5 n-electrode 6 p-electrode 7 groove 8 mesa
Claims (2)
する基板と、この基板の一面側に形成したn電極と、前
記基板の他面側に順に積層したGaNのn型層,活性層
及びGaNのp型層と、このp型層の上に形成したp電
極とを備え、前記p型層の表面から前記活性層を貫いて
前記n型層の上端の内部まで達する深さを持ち且つ平面
形状が閉じた環を形成する溝を設け、この溝に囲まれた
部分をメサとするとともにこのメサの表面に前記p電極
を導通配置してなるGaN系化合物半導体発光素子。1. A substrate made of GaN doped with an n-type impurity, an n-electrode formed on one surface of the substrate, and an n-type layer, an active layer, and a GaN layer sequentially stacked on the other surface of the substrate. A p-type layer of GaN and a p-electrode formed on the p-type layer, having a depth extending from the surface of the p-type layer to the inside of the upper end of the n-type layer through the active layer; A GaN-based compound semiconductor light-emitting device in which a groove that forms a closed ring in a planar shape is provided, a portion surrounded by the groove is used as a mesa, and the p-electrode is conductively arranged on the surface of the mesa.
電極が占める平面積との大きさとの間に、前記p電極の
周りで前記溝の幅及び環の長さを変更可能とする関係を
持たせてなる請求項1記載のGaN系化合物半導体発光
素子。2. The size of the planar shape of the p-type layer and the p-type layer
2. The GaN-based compound semiconductor light emitting device according to claim 1, wherein a relationship is provided between the plane area occupied by the electrode and the size of the groove and the length of the ring around the p electrode. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP16184898A JPH11354845A (en) | 1998-06-10 | 1998-06-10 | Gan compound semiconductor light emitting element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16184898A JPH11354845A (en) | 1998-06-10 | 1998-06-10 | Gan compound semiconductor light emitting element |
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Publication Number | Publication Date |
---|---|
JPH11354845A true JPH11354845A (en) | 1999-12-24 |
Family
ID=15743101
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JP16184898A Pending JPH11354845A (en) | 1998-06-10 | 1998-06-10 | Gan compound semiconductor light emitting element |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002094117A (en) * | 2000-09-06 | 2002-03-29 | Renyu Kagi Kofun Yugenkoshi | Light emitting diode device and its manufacturing method |
JP2004521498A (en) * | 2001-03-09 | 2004-07-15 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | Beam emitting semiconductor device and method of manufacturing the same |
CN103258933A (en) * | 2012-04-09 | 2013-08-21 | 东莞市久祥电子有限公司 | Method for preventing glue overflowing in packaging process of wafer-type light-emitting diode (LED) circuit board through copper plating |
US9911899B2 (en) | 2015-06-15 | 2018-03-06 | Alpad Corporation | Semiconductor light-emitting device |
WO2022202342A1 (en) * | 2021-03-23 | 2022-09-29 | 旭化成株式会社 | Ultraviolet light emitting element |
-
1998
- 1998-06-10 JP JP16184898A patent/JPH11354845A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002094117A (en) * | 2000-09-06 | 2002-03-29 | Renyu Kagi Kofun Yugenkoshi | Light emitting diode device and its manufacturing method |
JP2004521498A (en) * | 2001-03-09 | 2004-07-15 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング | Beam emitting semiconductor device and method of manufacturing the same |
US8138511B2 (en) | 2001-03-09 | 2012-03-20 | Osram Ag | Radiation-emitting semiconductor component and method for producing the semiconductor component |
CN103258933A (en) * | 2012-04-09 | 2013-08-21 | 东莞市久祥电子有限公司 | Method for preventing glue overflowing in packaging process of wafer-type light-emitting diode (LED) circuit board through copper plating |
US9911899B2 (en) | 2015-06-15 | 2018-03-06 | Alpad Corporation | Semiconductor light-emitting device |
US10128408B2 (en) | 2015-06-15 | 2018-11-13 | Alpad Corporation | Semiconductor light-emitting device |
US10403790B2 (en) | 2015-06-15 | 2019-09-03 | Alpad Corporation | Method for manufacturing semiconductor light-emitting device |
WO2022202342A1 (en) * | 2021-03-23 | 2022-09-29 | 旭化成株式会社 | Ultraviolet light emitting element |
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