JPH11354633A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize the plasma starting of a sputter etching device and to remove an organic matter or absorbed moisture without damaging a processed substrate, by sputtering/etching ion energy while it is increased stepwise. SOLUTION: In a cleaned processed substrate, an element isolation area 2 is formed on the surface of a semiconductor substrate 1, and a gate electrode 3 and an impurity diffusion layer 5 which are formed in an element area surrounded by the element isolation area 2, and connection holes 7 opened to an interlayer insulating film 6, are provided. The cleaning process of automatic oxide films 8 is executed on the processed substrate. In the cleaning process, the energy of sputtering ions is increased stepwise to a prescribed value with which the throughput of cleaning is not dropped, without causing damaged by the ions to the processed substrate, sputtering/etching are executed and sputtering/etching are continued in such a state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device characterized by a cleaning step as a step prior to forming a conductive layer such as a metal in a semiconductor device having a multilayer wiring structure. About the method.

[0002]

2. Description of the Related Art ULSI (Ultra Large Scale Integrat)
ed Circuits) are being integrated and the minimum design rules are shrinking to the sub-quarter micron level, while multi-layer interconnect structures are evolving. Achieving low contact resistance in the interlayer connection between the multi-layer wirings is particularly important for CPUs.
(Central Processing Unit) is extremely important in semiconductor devices requiring high-speed operation.

In order to reduce the contact resistance, as a pretreatment step for forming a conductive layer such as a contact plug in a connection hole formed in an interlayer insulating film, a natural oxide film or the like on the surface of a lower conductive layer exposed at the bottom of the connection hole is used. It is indispensable to form a conductive layer immediately after performing a cleaning step for removing and before forming a new native oxide film.

As a pre-treatment of a contact hole using a diffusion layer of a semiconductor substrate as a lower conductive layer, a wet treatment with diluted hydrofluoric acid has been conventionally used. However, when the contact hole diameter is reduced and the aspect ratio is increased, the cleaning effect of the fine hole bottom is reduced. In addition, there is a problem that the interlayer insulating film on the side surface of the contact hole is isotropically etched to cause undercut, thereby deteriorating the filling characteristics of the contact plug.

Therefore, as a cleaning method by dry processing, a parallel plate etching apparatus and RF reverse sputtering (sputter etching) using Ar have come to be used. However, on the other hand, the thickness of the gate insulating film and the diffusion layer is also 1
It is becoming smaller than 0 nm, and there is a concern about device damage such as dielectric breakdown due to charge accumulation of incident ions and junction leak. Further, even if sputter etching conditions with less risk of damage are set, the reproducibility of the process is reduced when the number of times of processing of the substrate to be processed is increased, that is, the yield is degraded due to the change or damage of the contact resistance.

That is, when the number of substrates to be processed is increased by the same etching apparatus, silicon compounds, metals or organic substances sputtered from the substrate to be processed are gradually accumulated on the inner walls of the plasma processing chamber. In particular, in the step of cleaning the bottom of the connection hole, the surface of the substrate to be processed is occupied mostly by an insulating film such as silicon oxide. For this reason, the plasma impedance fluctuates, and the plasma does not rise smoothly at the beginning of etching, or the etching rate is distributed between the substrates to be processed or in the substrates to be processed. Such a phenomenon may cause a decrease in the production yield and reliability of the semiconductor device, such as a decrease in reproducibility in a production line and a change in device characteristics.

[0007]

SUMMARY OF THE INVENTION The present invention is proposed in view of the above technical background. Even in a highly integrated semiconductor device of the sub-quarter micron generation, a stable and reproducible low-resistance interlayer connection is provided. It is an object of the present invention to provide a method of manufacturing a semiconductor device having a cleaning step capable of realizing the above.

[0008]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of: cleaning a surface of a substrate to be processed by sputter etching;
A method of manufacturing a semiconductor device, comprising: forming a conductive layer on the cleaned substrate to be processed, wherein the cleaning step includes a first step of performing sputter etching while stepwise increasing the energy of sputter ions to a predetermined value. It is characterized by including a cleaning step and a second cleaning step of continuing sputter etching with the energy of the predetermined value. The predetermined value of energy means energy that does not cause ion damage to the substrate to be processed and does not lower the throughput of cleaning, and depends on the surface condition of the substrate to be cleaned and the etching apparatus. These values are set individually.

In the first cleaning step, it is desirable that the discharge output of the sputter etching apparatus be stepwise increased, so that the energy of the sputter ions is stepwise increased to a predetermined value.

Alternatively, the first cleaning step includes:
When using a sputter etching apparatus capable of independently controlling the plasma generation power output and the substrate bias power output, at least one of the plasma generation power output and the substrate bias power output is increased stepwise to a predetermined value. Accordingly, it is desirable to increase the energy of the sputter ions stepwise to a predetermined value. When increasing in a stepwise manner, the height may be increased in small steps in a literal manner, or may be increased in a linear or curved manner.

Further, it is desirable that the sputter etching apparatus employed in the present invention has a high-density plasma generation source having an electron density of 1 × 10 ¹¹ cm ⁻³ or more and less than 1 × 10 ¹⁴ cm ⁻³ . At an electron density of less than 1 × 10 ¹¹ cm ⁻³ , there are some difficulties in terms of etching rate and in-plane uniformity of a large-diameter substrate to be processed. In order to clean the bottom of the connection hole having a high aspect ratio, it is desirable to increase the mean free path of ions by setting the gas pressure during etching to a high vacuum of the order of 10 ^-1 Pa. Density is limited to less than 1 × 10 ¹⁴ cm ⁻³ . An etching apparatus having such a high-density plasma generation source includes ECR (Electron Cyclotron Resonan).
ce) Plasma etching equipment, ICP (Inductively Co
upled Plasma) etching apparatus, helicon wave plasma etching apparatus, and the like.

Further, it is desirable to use an etching gas containing a reducing gas as an etching gas used in the cleaning step of the present invention. That is, in addition to Ar as a sputter etching gas, a reducing gas such as H ₂ , HF or HCl is used.

In a conventional sputter etching apparatus, a target substrate is irradiated with sputter ions of a predetermined energy set in an initial stage in one step. For this reason, when the number of substrates to be processed is increased and the impedance or the like in the etching chamber changes, time is required for impedance matching, and the plasma activation may become unstable or abnormal discharge may occur. In severe cases, the auto-tuning function of impedance matching may not work. According to the method for manufacturing a semiconductor device of the present invention, the output at the time of plasma activation is small,
Therefore, the load applied at the time of impedance matching on the power supply side is small, so that impedance matching can be easily achieved, and plasma is stably generated. Therefore, if you gradually increase the output of the power supply,
Cleaning can be performed on the surface of the substrate under stable sputter etching conditions.

After completion of the cleaning process, it is desirable to form the conductive layer continuously without exposing the cleaned substrate to the atmosphere. For this purpose, a continuous processing apparatus in which a film forming apparatus is connected to a sputter etching apparatus via a vacuum gate valve is suitable. The film forming device is a sputter deposition device, a vacuum evaporation device or a CVD device.
(Chemical Vapor Deposition) Any device may be used.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

First, an example of the configuration of a plasma processing apparatus used in the method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.

FIG. 2 is a schematic sectional view of a triode parallel plate type sputter etching apparatus. That is, in the plasma processing chamber 16, the substrate 10 to be processed is placed, and the substrate stage 11 serving as one of the electrodes, the counter electrode 13, and the grid electrode 15 at an intermediate position between these capacitance electrodes are provided.
Is arranged. The substrate stage 11 is provided with a substrate bias power supply 12 for applying a substrate bias potential.
Are connected to a plasma generation power supply 14, respectively.
The grid electrode 15 is at the ground potential. Each output of the substrate bias power supply 12 and the plasma generation power supply 14 can be increased stepwise or maintained at a constant value. This may be either computer control, control by a timer or the like, or manual control. In FIG. 2, details of the apparatus such as a gas introducing unit, a gas exhausting unit, a loading / unloading unit of the substrate to be processed 10, an output control unit of each power supply, and the like are omitted. Further, a film forming apparatus such as a sputtering apparatus that vacuum-transfers the substrate 10 to be processed in a later process and continuously forms an upper conductive layer is not illustrated.

According to the sputter etching apparatus shown in FIG.
Plasma 17 having an ion density of the order of 10 ⁹ cm ⁻³ is generated between the counter electrode 13 and the grid electrode 15, and the incident energy of ions can be controlled independently of the input level of the plasma generation power supply 14. That is, plasma 1
Cations such as Ar ^{+ in} 7 pass through the grid electrode 15,
Due to the weak substrate bias potential formed by the substrate bias power supply 12, the light enters the substrate 10 to be processed. If a magnet is arranged on the back side of the counter electrode 13 or around the plasma processing chamber 16 to constitute a magnetron parallel plate type plasma processing apparatus using the magnetron motion of electrons in the plasma 17, 10 ¹⁰ cm ⁻³ units Can be obtained.

FIG. 3 is a schematic sectional view of an inductively coupled plasma (ICP) processing apparatus. That is, the plasma processing chamber 1
6, a substrate stage 11 on which a substrate 10 to be processed is mounted is provided.
Are arranged. The substrate stage 11 is connected to a substrate bias power supply 12 for applying a substrate bias potential. An inductive coupling coil 18 is wound around the plasma processing chamber 16 in multiple layers, and an ICP power supply 19
Is connected. Each output of the ICP power supply 19 and the substrate bias power supply 12 can be increased in a stepwise manner or maintained at a constant value. This may be any of computer control, control by a timer, or manual control.
In FIG. 3, details of the apparatus such as a gas introduction unit, a gas exhaust unit, a loading / unloading unit for loading and unloading the substrate to be processed 10, and an output control unit for each power supply are omitted. Further, a film forming apparatus such as a sputtering apparatus that vacuum-transfers the substrate 10 to be processed in a later process and continuously forms an upper conductive layer is not illustrated.

According to the sputter etching apparatus shown in FIG.
Due to the alternating electric field formed by the inductive coupling coil 18, 10 ¹¹
High-density plasma 17 having an ion density of cm ^-3 or more can be generated. A large amount of cations such as Ar ⁺ in the plasma 17 enter the substrate 10 to be processed by a weak substrate bias potential generated by the substrate bias power supply 12.

FIG. 4 is a schematic sectional view of the substrate stage 11 of the sputter etching apparatus shown in FIGS. A heater 2 is provided in a substrate stage 11 on which the substrate 10 is placed.
1 and a refrigerant pipe 22 for circulating a refrigerant such as ethanol
Is provided, and the temperature of the substrate 10 to be processed can be controlled to a desired temperature by a temperature sensor and temperature control means (not shown). The surface of the substrate stage 11 is made of a ceramic such as quartz in which fine grooves such as a radial shape are formed, and an electrostatic chucking electrode 20 is embedded below the ceramic. Also, H penetrates through the center of the substrate stage 11 and
Heat conduction medium introduction hole 23 for introducing a heat conduction gas such as e gas
Are formed.

With the configuration of the substrate stage 11 shown in FIG. 4, the substrate 10 to be processed adheres to the surface of the substrate stage 11 and the heat conduction effect of the heat conductive gas is added.
The temperature can be controlled with high precision, and stable sputter etching can be performed.

According to the sputter etching apparatus illustrated in FIGS. 2 and 3, sputter etching can be performed on the substrate to be processed while increasing the incident energy of sputter ions in a stepwise manner or with a predetermined value of energy. Therefore, it is easy to perform impedance matching at the start of discharge, and stable low-damage cleaning can be performed.

[0024]

EXAMPLES Hereinafter, the present invention will be described in more detail with reference to specific examples. However, the present invention is not limited at all by the following examples.

[Embodiment 1] In this embodiment, an example in which a native oxide film on the surface of a conductive layer exposed at the bottom of a connection hole is removed by Ar ⁺ ion irradiation by a triode type parallel plate type plasma processing apparatus shown in FIG. This step will be described with reference to FIG.

The substrate to be processed employed in this embodiment is shown in FIG.
As shown in FIG. 1A, an element isolation region 2 formed on the surface of a semiconductor substrate 1 made of silicon or the like, a gate electrode 3 and an impurity diffusion layer 5 formed in an element region surrounded by the element isolation region 2, and It has a contact hole 7 (Contact Hole) opened in the interlayer insulating film 6 facing the impurity diffusion layer 5. A lower wiring 4 is formed on the element isolation region 2 and faces the lower wiring 4 to form a connection hole 7 (via Hole).
Is open. The lower wiring 4 extending from the gate electrode 3 is made of the same kind of conductive material as the gate electrode 3, that is, polycrystalline silicon or high melting point metal polycide. A natural oxide film 8 is formed on the surface of the impurity diffusion layer 5 and the lower wiring 4 exposed at the bottoms of the connection holes 7.
In FIG. 1A, the natural oxide film 8 is shown thicker than it actually is for explanation.

The substrate to be processed shown in FIG. 1A was set on the substrate stage 11 of the triode parallel plate type plasma processing apparatus shown in FIG. 2, and a natural oxide film 8 was cleaned. In this cleaning step, the energy of sputter ions was increased in two stages, and sputter etching was finally performed at a predetermined energy for 60 seconds.

[Cleaning Step 1] Ar 25 sccm pressure 0.7 Pa substrate stage temperature 50 ° C. plasma generation power 300 W (2 MHz) substrate bias voltage 0 V time 5 sec

[Cleaning Step 2] Ar 25 sccm pressure 0.7 Pa substrate stage temperature 50 ° C. plasma generation power 600 W (2 MHz) substrate bias voltage 0 V time 5 sec

[Cleaning Step 3] Ar 25 sccm pressure 0.7 Pa substrate stage temperature 50 ° C. plasma generation power 600 W (2 MHz) substrate bias voltage 250 V (13.56 MHz) time 60 sec

In the cleaning step 1 and the cleaning step 2, the plasma stably rises, and finally, in the cleaning step 3, the substrate to be processed was sputter-etched with a predetermined ion energy. As a result, the natural oxide film 8 at the bottom of the connection hole 7 is stably and effectively removed by sputtering due to the incidence of Ar ⁺ ions indicated by arrows in FIG. 1B. The irradiation energy of Ar ⁺ ions in this embodiment is relatively low, and the sputter removal rate of the native oxide film 8 is within the practical range but relatively small.

Thereafter, the substrate to be processed is vacuum-transferred into the sputtering apparatus via a gate valve, and immediately the conductive layer 9
To form In this embodiment, the conductive layer 9 has a thickness of 120 nm.
And a wiring layer 9a made of W and having a thickness of 600 nm was formed by sputtering. Among them, the barrier layer 9b had a three-layer structure of Ti / TiN / Ti, and each was formed with a thickness of 30/60/30 nm. FIG. 1C shows a state in which the conductive layer 9 is formed.

Thereafter, although not shown, the conductive layer 9 is patterned into a desired wiring shape by forming a resist mask and anisotropic etching. In the case where the conductive layer 9 is used as a contact plug, the entire surface is etched back,
The conductive layer 9 on the interlayer insulating film 6 may be removed by MP (Chemical mechanical polishing).

As described above, according to the present embodiment, the contact portion is stably cleaned and the contact resistance is reduced by performing the sputter etching while increasing the ion energy stepwise by using the triode parallel plate type plasma processing apparatus. The wiring resistance of the conductive layer itself can also be reduced. In addition, a highly reliable multilayer wiring structure, such as improved adhesion of the conductive layer, can be obtained.

[Embodiment 2] In the present embodiment, the I shown in FIG.
This is an example in which a native oxide film on the surface of the conductive layer exposed at the bottom of the connection hole is sputter-etched and removed using a reducing gas together with a CP processing apparatus. This step will be described with reference to FIG.

The substrate to be processed adopted in this embodiment is the same as that described in the first embodiment with reference to FIG. The substrate to be processed shown in FIG. 1A is mounted on a substrate stage 1 of the ICP processing apparatus shown in FIG.
1 was set. Next, HF is used as a reducing gas.
And a cleaning step of the natural oxide film 8 was performed.
In this cleaning step, the energy of the sputter ions is increased in two steps, and finally, the energy of the
Sputter etching was performed for 5 seconds.

[Cleaning Step 1] HF 5 sccm Ar 25 sccm pressure 0.3 Pa substrate stage temperature 50 ° C. ICP power supply 500 W (450 kHz) substrate bias voltage 0 V time 5 sec

[Cleaning Step 2] HF 5 sccm Ar 25 sccm pressure 0.3 Pa substrate stage temperature 50 ° C. ICP power supply 750 W (450 kHz) substrate bias voltage 50 V (13.56 MHz) time 5 sec

[Cleaning Step 3] HF 5 sccm Ar 25 sccm pressure 0.3 Pa substrate stage temperature 50 ° C. ICP power supply 1000 W (450 kHz) substrate bias voltage 100 V (13.56 MHz) time 45 sec

In the cleaning step 1 and the cleaning step 2, the plasma rises smoothly by increasing the ion energy stepwise, and stable cleaning can be performed. As a result, as shown in FIG. 1B, the natural oxide film 8 at the bottom of the connection hole 7 is irradiated by irradiation of hydrogen active species such as Ar ⁺ ions and H ⁺ ions indicated by arrows.
Is very effectively removed by a chemical reduction reaction and a physical sputtering effect. Ar ^{+ in} this example
The ion irradiation energy is relatively low, and the damage to the substrate to be processed is small. When the clean impurity diffusion layer 5 surface, that is, the silicon surface is exposed, dangling bonds of silicon atoms on the outermost surface are terminated by F atoms, and become chemically active.

Thereafter, the substrate to be processed is vacuum-transferred into the sputtering apparatus via a gate valve, and immediately the conductive layer 9
To form In this embodiment, the conductive layer 9 has a thickness of 120 nm.
And a wiring layer 9a made of Cu having a thickness of 600 nm. First of all, dozens of n
A seed layer was formed by sputtering to a thickness of about m, and the remaining layer was formed by electroplating using this as a current-carrying layer. The Cu layer may be formed by CVD. The barrier layer 9b is made of Ti
/ TiN / Ti three-layer structure, each having a thickness of 30
/ 60/30 nm. FIG. 1C shows a state in which the conductive layer 9 is formed.

Thereafter, although not shown, the conductive layer 9 is patterned into a desired wiring shape by forming a resist mask and anisotropic etching. In the case where the conductive layer 9 is used as a contact plug, the whole surface is etched back,
The conductive layer 9 on the interlayer insulating film 6 may be removed by the P method.

As described above, according to this embodiment, by using the ICP processing apparatus, the sputter ion energy is increased stepwise, and the relatively low energy Ar ⁺ ions and hydrogen active species are irradiated, whereby the cleanliness of the contact portion is improved. Is further increased, the contact resistance is reduced, and the wiring resistance of the conductive layer itself can be reduced. In addition, a highly reliable multilayer wiring structure, such as improved adhesion of the conductive layer, can be obtained.

Although the present invention has been described in detail with reference to two examples, the present invention is not limited to these examples.

For example, as a method of increasing the ion energy in a stepwise manner, the power supply output is increased in two steps, but may be increased in multiple steps or in a linear or curved manner.

As the plasma processing apparatus, an ECR plasma processing apparatus, a helicon wave plasma processing apparatus, or the like can be employed in addition to the triode parallel plate type apparatus and the ICP apparatus. From the viewpoint that soft etching with low ion energy is possible, a high-density plasma processing apparatus having an ion density of 1 × 10 ¹¹ cm ⁻³ or more is preferably used.

As a substrate to be processed, besides a substrate on which an impurity diffusion layer and a gate electrode / wiring formed on a silicon substrate are formed, a bipolar transistor, a CCD (Char
(Ge Coupled Device) or a semiconductor film of a thin film transistor. The semiconductor substrate may be a compound semiconductor such as SiGe, Ge, or GaAs in addition to silicon. In addition, it goes without saying that the configuration of the substrate to be processed and the like can be appropriately changed.

[0048]

As is apparent from the above description, according to the method for manufacturing a semiconductor device of the present invention, the plasma activation of the sputter etching apparatus is stabilized, and the spontaneous oxide film and the natural oxide film can be formed without damaging the substrate to be processed. Organic substances such as etching residues, adsorbed moisture, and the like can be removed. Therefore, a low-resistance and high-reliability interlayer connection structure using a connection hole having a small opening diameter and a high aspect ratio can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view illustrating steps of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a schematic sectional view showing a triode parallel plate type plasma processing apparatus of an embodiment.

FIG. 3 is a schematic sectional view showing an inductively coupled plasma processing apparatus according to another embodiment.

FIG. 4 is a schematic sectional view showing a substrate stage of the plasma processing apparatus used in the example.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 element isolation region 3 gate electrode
4 lower wiring, 5 impurity diffusion layer, 6 interlayer insulating film, 7
... connection hole, 8 ... natural oxide film, 9 ... conductive layer, 9a ... wiring layer, 9b ... barrier layer 10 ... substrate to be processed, 11 ... substrate stage, 12 ... substrate bias power supply, 13 ... counter electrode, 14 ... plasma generation Power supply, 15: grid electrode, 16: plasma processing chamber, 17: plasma, 18: inductive coupling coil, 19: ICP power supply, 2
0: Electrostatic adsorption electrode, 21: Heater, 22: Refrigerant pipe, 2
3 ... Heat conduction medium introduction hole

Claims (5)

[Claims] 1. A method for manufacturing a semiconductor device, comprising: a step of cleaning a surface of a substrate to be processed by sputter etching; and a step of forming a conductive layer on the cleaned substrate to be processed. A first cleaning step of performing sputter etching while stepwise increasing the energy of the semiconductor device to a predetermined value; and a second cleaning step of continuing sputter etching with the predetermined value of energy. . 2. The semiconductor according to claim 1, wherein in the first cleaning step, the energy of sputter ions is increased stepwise to a predetermined value by stepwise increasing a discharge output of a sputter etching apparatus. Device manufacturing method. 3. The first cleaning step uses a sputter etching apparatus that can independently control a plasma generation power supply output and a substrate bias power supply output, and uses any one of the plasma generation power supply output and the substrate bias power supply output. 2. The method according to claim 1, wherein the energy of the sputter ions is increased stepwise to a predetermined value by increasing at least one output stepwise to a predetermined value. 4. The semiconductor device according to claim 2, wherein said sputter etching apparatus has a plasma generation source having an electron density of 1 × 10 ¹¹ cm ⁻³ or more and less than 1 × 10 ¹⁴ cm ^−3. Manufacturing method. 5. The method according to claim 1, wherein said cleaning step uses an etching gas containing a reducing gas.