JP2000216249A - Method and device for manufacturing electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic device manufacturing method with which a highly reliable low-resistance interlayer connection can be achieved by using fine connecting holes having high aspect ratios. SOLUTION: Prior to the cleaning of a natural oxide film 8, etc., formed on the surface of an impurity diffusion layer 5 or gate electrode wiring 3' exposed on the bottoms of connecting holes 7 and 7' by using the discharge plasma of a rare gas or by performing reverse sputtering, adsorbed water is removed from the surface of a substrate, to be treated by irradiating the surface with the light of a lamp in a nonoxidative reduced-pressure atmosphere.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an electronic device and an apparatus therefor, and more particularly, to an upper conductive layer in an interconnection of a multilayer wiring structure of an electronic device such as a highly integrated semiconductor device. Formation (Meta
The present invention relates to a method of manufacturing an electronic device having a feature in a pretreatment process before entering a process, and an apparatus thereof.

[0002]

2. Description of the Related Art ULSI (Ultra Large Scale Integrat)
Semiconductor devices such as ed circuits) have been highly integrated, and their design design rules have become finer, and multilayer wiring structures have been used extensively. In a multilayer wiring structure, a lower conductive layer and an upper conductive layer are electrically connected via a connection hole formed in an interlayer insulating film. These connection holes are also in the direction of miniaturization, for example, the minimum design rule is 0.18 μm
In the semiconductor device described above, the opening diameter of the connection hole is 0.24 μm.
m. Since the thickness of the interlayer insulating film itself is about 1.0 μm from the viewpoint of the capacitance between wirings and the withstand voltage, the aspect ratio of the connection hole becomes 4.0 or more.

In order to realize a multi-layer wiring structure with low resistance and high reliability by using such fine and high aspect ratio connection holes, it is inevitable to form on the surface of the lower conductive layer exposed at the bottom of the connection holes. A pretreatment step for removing the removed natural oxide film, contaminants and the like (hereinafter abbreviated as a natural oxide film and the like), that is, a cleaning step is indispensable.

When an impurity diffusion layer of a semiconductor substrate such as silicon is used as a lower conductive layer, or when a metal wiring such as Al or an Al alloy is used as a lower conductive layer, connection holes, ie, contact holes or via holes, are formed. The impurity diffusion layer exposed at the bottom or the natural oxide film on the surface of the metal wiring is mainly composed of silicon oxide or aluminum oxide, and also contains etching residues, resist residues, adsorbed moisture and the like.

For the removal of the natural oxide film and the like, for example, silicon oxide, wet cleaning with a dilute hydrofluoric acid aqueous solution has been mainly used. However, the interlayer insulating film on the side wall of the connection hole is also isotropically etched to have an overhang shape, and thus, there is a problem that the embedded shape of the contact plug and the upper wiring is deteriorated. Further, in the case of a connection hole having a fine opening diameter and a high aspect ratio, the cleaning liquid does not sufficiently spread to the inside of the connection hole. As a result, there is also a problem that the effect of removing the natural oxide film at the bottom of the connection hole is reduced. .

In place of such wet cleaning, a dry pretreatment in which a parallel plate type plasma processing apparatus is used to perform dry cleaning by RF reverse sputtering using Ar ⁺ ions has been proposed, and a lower wiring such as an Al-based metal is used as a lower conductive layer. Practical for pre-processing of via holes. Since the direction of Ar ⁺ ions can be controlled by an electric field or the like, it is easy to remove a natural oxide film or the like at the bottom of a fine and high aspect ratio connection hole.

However, in the removal of the natural oxide film on the surface of the lower wiring extending from the gate electrode, the accumulation of charges due to incident Ar ⁺ ions or the like causes the gate insulating film to be destroyed (partial potential difference due to the charges is reduced). It has been pointed out that device damage such as leakage current is one of the causes of gate destruction.) In addition, when the diameter of the wafer is further increased, the processing performance by Ar ⁺ ions is reduced. There is also a concern that the degree of variation within the wafer surface will increase. In the case where the lower conductive layer is a shallow impurity diffusion layer formed on a semiconductor substrate, there is a possibility that a junction leak may be caused by damage due to the incidence of Ar ⁺ ions having high ion energy.
These were mainly caused by non-uniformity of RF plasma density when a large-diameter wafer was processed by a parallel plate type plasma apparatus.

Accordingly, the present inventor has proposed a soft etching method using a high-density plasma processing apparatus with a low substrate bias as a pre-processing method for forming an upper conductive layer in a contact hole or a via hole. -26045
No. 5 publication. For example, ICP (Inductively Coupled Plasma) is used for pre-processing when forming an upper metal layer in a via hole that makes contact with a lower metal wiring layer.
, TCP (Transfer Coupled Plasma), ECR (Elect
ron Cyclotron Resonance), by using a high-density plasma source such as helicon wave plasma, and by optimally controlling the substrate bias voltage, it is possible to handle large-diameter wafers and suppress device damage to ultra-fine semiconductor elements.
The next generation wafer processing technology was proposed.

According to this method, low energy Ar ⁺
It is possible to perform low-damage cleaning using ions, and a concern about a decrease in the etching rate is as follows.
This can be compensated for by improving the plasma density. That is, I
By the formation of high-density plasma by CP, etc., and precise control of substrate bias voltage independent of plasma generation,
Compared to the RF reverse sputtering using a conventional parallel plate type plasma apparatus, a dry pretreatment process having high uniformity in a wafer surface and low damage and sufficient removal capability for lower layer metal oxides and the like can be realized. . As a result, it is possible to realize a metal film forming pretreatment that can cope with the formation of via plugs and the like of a very miniaturized VLSI device.

[0010]

As described above, by adopting the pretreatment by soft etching using a high-density plasma processing apparatus with a low substrate bias, it is possible to clean a natural oxide film and the like at the bottom of a finely-divided connection hole. Has made significant progress.
However, it has not been possible to completely remove moisture firmly adsorbed on the surface of the substrate to be treated, causing outgassing during the formation of the upper conductive layer and causing unstable electrical characteristics at the contact interface in the long term. Had a risk of becoming a factor.

In the case of forming a wiring material such as W or Cu by a further miniaturized device or by CVD (chemical vapor deposition) or plating other than the conventional sputtering of Al or Al alloy, Stricter substrate cleanliness is required, and even if the above-mentioned dry pretreatment is performed, the moisture adsorbed on the wafer surface cannot always be sufficiently removed, and the interface of the metal joint such as a via plug (or contact plug) is not removed. In some cases, this may cause the electrical characteristics of the device to become unstable.

In a situation where the degree of integration of a semiconductor device is further advanced, for example, the thickness of a gate insulating film is reduced to 10 nm or less, and the depth of an impurity diffusion layer is also becoming thinner, further cleaning with less damage and more stable cleaning is performed. A method of conversion is desired. In addition to the formation of the upper conductive layer by sputtering an Al-based metal, a high-melting point metal such as W or a low-resistance Cu
When a metal such as is formed by a CVD method or an electrolytic plating method, a stricter degree of cleaning is required.

It is also desired to establish a highly reliable metal film forming pretreatment process for stably forming contact plugs and via plugs of ultra-fine devices of the sub-quarter micron generation. .

[0014] The present invention solves the above-described problems and provides a natural oxide film in a contact hole or a via hole on a substrate to be processed even in a semiconductor device to which a sub-quarter micron design rule is applied. In addition, it is an object of the present invention to provide an electronic device manufacturing method and an electronic device manufacturing method capable of removing and cleaning adsorbed water on a substrate to be processed and performing the cleaning without damaging the substrate to be processed. It is the purpose.

[0015]

That is, the present invention provides a method for forming an interlayer insulating film formed on a conductive layer formed on a substrate to be processed.
A step of opening a connection hole facing the conductive layer; a step of cleaning the surface of the conductive layer exposed at the bottom of the connection hole; and a step of continuously forming an upper conductive layer at least in the connection hole. In the method of manufacturing an electronic device, the cleaning step includes irradiating the substrate to be processed with lamp light in a non-oxidizing reduced-pressure atmosphere, and applying at least a rare gas to the substrate to be processed. A method of manufacturing an electronic device (hereinafter, referred to as a first method of the present invention).

In the present invention, the term “continuous” refers to
This means that the substrate to be processed is conveyed to a conductive layer forming apparatus by a vacuum gate valve or the like without being exposed to a polluted atmosphere such as the atmosphere, and is subjected to the next step of forming an upper conductive layer. The upper conductive layer can be formed while avoiding reoxidation of the converted substrate and re-adsorption of moisture and foreign matter (the same applies hereinafter). The electronic device to which the present invention is applied includes a memory, a logic, and a CCD (Charge C).
oupled Device), multi-layer coil type thin film magnetic head device, thin film inductor device, thin film coil device, micro machine device, etc.
A microelectronic device employing a multilayer wiring with connection holes called contact holes or via holes is exemplified (the same applies hereinafter).

Further, according to the present invention, a step of opening a connection hole facing the conductive layer in an interlayer insulating film formed on the conductive layer formed on the substrate to be processed; A method of manufacturing an electronic device, comprising: a step of cleaning a surface of a conductive layer; and a step of continuously forming an upper conductive layer at least in the connection hole. A method of manufacturing the electronic device (hereinafter referred to as the present invention), which comprises a step of irradiating a lamp light in a non-oxidizing reduced-pressure atmosphere and a step of subjecting the substrate to be processed to reverse sputtering. This is referred to as a second method.)

Further, the present invention provides a process for forming a connection hole as a via hole facing the lower conductive layer in an interlayer insulating film formed on the lower conductive layer formed on the substrate to be processed; A step of cleaning the surface of the lower conductive layer exposed at the bottom of the device, and a step of forming an upper conductive layer at least in the connection hole, wherein the cleaning step comprises at least A method for manufacturing an electronic device, characterized in that the substrate to be processed is subjected to light irradiation and plasma processing in a plasma processing chamber having a light irradiation device (hereinafter, referred to as a third method of the present invention). It is related to.

Further, the present invention provides a cleaning chamber for cleaning the surface of the conductive layer exposed on the bottom of the connection hole opened in the interlayer insulating film on the conductive layer formed on the substrate to be processed; An apparatus for manufacturing an electronic device, comprising: a film forming chamber for forming an upper conductive layer in a connection hole; wherein the cleaning chamber is a plasma processing chamber including at least a light irradiation device; The present invention also provides an apparatus for manufacturing an electronic device (hereinafter, referred to as an apparatus of the present invention), characterized in that the apparatus is configured to be able to perform plasma processing.

According to the first and second methods of the present invention, the moisture adsorbed on the surface of the substrate to be treated is rapidly desorbed and removed by irradiating the lamp light in a non-oxidizing reduced pressure atmosphere. You. Since the lamp light mainly raises the temperature of the surface of the substrate to be processed in a short period of time, the MOS (Meta
(l Oxide Semiconductor) Even if an element such as a transistor is formed, there is little possibility that inconvenience such as re-diffusion of the impurity diffusion layer occurs. Then, a natural oxide film or the like is removed by subjecting the substrate to be processed to at least a discharge plasma treatment of a rare gas or a reverse sputtering treatment.

Therefore, the surface of the substrate to be processed after cleaning is in a state where neither adsorbed moisture nor a natural oxide film is present. If the upper conductive layer is formed continuously, no outgas is generated, and no contact gas is generated at the contact interface. Contact resistance is reduced.

According to the third method of the present invention and the apparatus of the present invention, the surface of the substrate to be processed is irradiated by irradiating light such as lamp light in at least a plasma processing chamber provided with a light irradiation device. The adsorbed water is quickly desorbed and removed.
Since the lamp light mainly raises the temperature of the surface of the substrate to be processed in a short time, even if an element such as a MOS transistor is formed on the substrate to be processed, there is a possibility that inconvenience such as re-diffusion of the impurity diffusion layer may occur. small. Then, a natural oxide film or the like is removed by performing a plasma process on the substrate to be processed.

Therefore, the surface of the lower conductive layer (particularly, the metal wiring material layer) in the via hole is cleaned while effectively removing and removing the moisture adsorbed on the surface of the substrate to be processed after the formation of the via hole. After the cleaning, the surface of the substrate to be treated is in a state in which neither adsorbed moisture nor a natural oxide film is present, and therefore, an upper conductive layer such as a barrier metal or a wiring material layer is continuously formed. If a film is formed, outgas from the substrate to be processed is suppressed during the film formation, and the via plug can be formed of a highly pure conductive material without adversely affecting the process due to the impurity gas. As a result, the electrical characteristics of via plugs are improved, such as a reduction in contact resistance at the metal interface of fine via holes of the sub-quarter micron generation, and high-speed operation of ultra LSI devices can be stably manufactured at a high yield. .

As described above, the semiconductor device is designed based on a fine design rule, and is extremely effective for the manufacture of a semiconductor device which requires high integration, high performance and high reliability.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a first method of the present invention,
The cleaning step is performed in a plasma processing chamber equipped with a lamp light irradiation device, and the upper conductive layer forming step is performed in a film forming chamber connected to the plasma processing chamber via a gate valve. It is desirable.

In the second method of the present invention, in the cleaning step, the step of irradiating the lamp light may include:
The reverse sputtering process is performed in a preliminary vacuum chamber provided with a lamp light irradiation device, and the reverse sputtering process is performed in a film formation pretreatment chamber connected to the preliminary vacuum chamber via a gate valve to form the upper conductive layer. The step is desirably performed in a film forming chamber connected to the film forming pretreatment chamber via a gate valve.

In the third method of the present invention, the cleaning step includes irradiating the substrate to be treated with a lamp light in a non-oxidizing reduced-pressure atmosphere. Performing a sputtering process or at least a discharge plasma treatment of a rare gas.

In this case, the plasma treatment is preferably performed under the action of discharge plasma of a gas having a reducing effect on the lower conductive layer such as HCl.

The step of forming the upper conductive layer is desirably performed continuously in a film forming chamber connected to the plasma processing chamber, and the film is preferably formed by sputtering.

Further, in the apparatus of the present invention, the cleaning chamber includes a light source for irradiating the substrate to be processed with lamp light in a non-oxidizing reduced-pressure atmosphere;
It is preferable to include a plasma generating means for performing reverse sputtering processing or at least discharge plasma processing of a rare gas.

In this case, it is preferable that the light source is disposed outside the cleaning chamber having at least a part of the light transmitting portion, and the plasma generating means is configured to generate inductively coupled plasma. Preferably, the plasma treatment is performed under the action of discharge plasma of a gas having a reducing effect on the lower conductive layer, such as HCl.

It is preferable that the upper conductive layer is formed continuously in a film forming chamber connected to the plasma processing chamber, and the film is formed by sputtering.

Preferably, the connection holes are formed as contact holes or via holes.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

First, two examples of the processing apparatus employed in the cleaning step according to the present invention will be described with reference to FIGS.

The processing apparatus shown in FIG. 2 mainly includes a lamp light irradiation / plasma processing apparatus 10 and a film forming apparatus 20. Substrate to be processed 1 such as Si semiconductor wafer
The details of the apparatus such as a load chamber for loading 1, an unload chamber for unloading, and a transport device for the substrate 11 are not shown.

Among them, the lamp light irradiation and plasma processing apparatus 10 is an apparatus for performing lamp light irradiation and plasma processing. In the chamber 21, the substrate 11 to be processed is placed and via a coupling capacitor 28. A stage 12 to which a bias power supply 13 is applied is provided. The stage 12 has a built-in heater 56 of a resistance heating type or the like, and can control a heating temperature by lamp light irradiation. The upper part of the chamber is a bell jar made of a dielectric material such as quartz or alumina, and the side of the bell jar has an ICP
(Inductively Coupled Plasma) An ICP coil 14 connected to a power supply 15 is wound. Above the bell jar, a halogen lamp or Xe
A lamp 16 such as an arc lamp is provided, and the surface of the substrate 11 to be processed can be heated through the light-transmitting wall (light irradiation window) 18 of the bell jar.

The lamp light irradiation / plasma processing apparatus 10 shown in FIG. 2 preferably uses an ICP method which does not generate a magnetic field and has little damage to the substrate 11 to be processed and small plasma unevenness. Is also good. Further, since the lamp 16 is disposed outside the bell jar, plasma is efficiently generated and maintenance is easy.

As a plasma generation method preferably employed in the present invention, in addition to the ICP method, a TCP (Transformer
Coupled Plasma) method, Helicon wave plasma method or E
An example is a CR (Electron Cyclotron Resonance) plasma method. These devices are high-density plasma sources of 1 × 10 ¹¹ cm ⁻³ or more. Although a higher plasma density is desirable, a plasma density of 1 × 10 ¹⁴ cm ⁻³ is almost a limit value in the current high vacuum plasma processing apparatus.

The bias power supply 13 sets the bias energy (ion incident energy) separately from the generated plasma energy, and it is desirable to set the bias energy to about 10 V or more and about 300 V or less (the bias voltage is In the case of a via plug described later, 250 to 5
It is necessary to set a little higher to 00V). In this manner, by performing rare gas plasma processing with low ion energy using high-density plasma, low-damage cleaning can be performed while securing throughput. Depending on the type of the plasma generation source, the antenna or coil for plasma generation may interfere with the lamp 16 in some cases. In this case, as shown in FIG. What is necessary is just to arrange | position a device separately and connect with a gate valve.

On the other hand, the film forming apparatus 20 is configured as, for example, a DC sputtering apparatus. This is connected to the lamp light irradiation and plasma processing apparatus 10 via a gate valve 17, and a stage 22 on which the substrate 11 to be processed is mounted and a sputtering power supply 24 are connected in a chamber 27. The target 23 is arranged opposite.

This film forming method is a DC sputtering method, but may be RF (AC) sputtering, EC
R sputtering method, evaporation, CVD (Chemical Vapor
Any method may be used as long as it is a film formation method suitable for the material of the upper conductive layer, such as a deposition method.

According to the continuous processing apparatus shown in FIG. 2, the step of irradiating the substrate 11 to be treated with lamp light in a non-oxidizing reduced-pressure atmosphere is the same as the step of performing discharge plasma treatment of a rare gas. After the cleaning step, the step of forming the upper conductive layer in the film forming apparatus 20 can be performed continuously without exposing the substrate 11 to be processed. There is also an advantage that the device configuration can be made compact and small.

The processing apparatus shown in FIG. 3 is an apparatus in which a lamp light irradiation device 30, a film forming pre-processing device 40, and a film forming device 20 are connected in series via gate valves 37 and 47. Also in FIG. 3, details of the apparatus such as a load chamber for loading the substrate 11 to be processed, an unload chamber for unloading the substrate 11, and a device for transporting the substrate 11 are omitted.

The lamp light irradiation device 30 includes a stage 32 in which a substrate 11 to be processed is placed and a heater 56 of a resistance heating type or the like is built in the chamber 25. The upper surface of the chamber is a light irradiation window 19 made of, for example, pressure-resistant quartz glass, through which the surface of the substrate 11 to be processed can be heated by a lamp 36 such as a halogen lamp or a Xe arc lamp.

The film forming pre-processing apparatus 40 is configured as, for example, a triode parallel plate RF plasma processing apparatus. In the chamber 26, the stage 42 on which the substrate 11 to be processed is placed and which also serves as one electrode, the counter electrode 4
5 and a grid electrode 48 located in the middle of these parallel plate electrodes. A bias power supply 43 for applying a bias is connected to the stage 42, and a plasma generation power supply (RF power supply) 46 is connected to the counter electrode 45, while the grid electrode 48 is set to the ground potential.

According to the film-forming pretreatment apparatus 40 shown in FIG. 3, the gap between the counter electrode 45 and the grid electrode 48 is 10 ⁹ cm ^−3.
Plasma is generated and the coupling capacitor 2
9 allows the bias power supply 43 to independently control the ion incident energy from the plasma. That is, due to the weak bias potential generated by the bias power supply 43, ions such as Ar ^{+ in} the plasma pass through the grid electrode 48, enter the target substrate 11, and clean the surface thereof by reverse sputtering. Note that this bias potential has an advantage that, in the case of a via plug described later, mainly ions of relatively high energy can be uniformly extracted to the wafer side.

The film forming pre-processing apparatus 40 shown in FIG.
If a magnet is arranged on the back side of the counter electrode 45 and around the chamber to constitute a magnetron type parallel plate type plasma processing apparatus using magnetron motion of electrons in the plasma, the plasma density of the order of 10 ¹⁰ cm ⁻³ can be obtained. Can be obtained.

The film forming apparatus 20 is the same as the film forming apparatus 2 shown in FIG.
Since the configuration is the same as that of 0, duplicate description is omitted.

According to the continuous processing apparatus shown in FIG. 3, the substrate to be processed 11 is irradiated with light by the lamp 36 in the non-oxidizing reduced-pressure atmosphere in the apparatus 30;
The step of performing reverse sputtering and the step of forming the upper conductive layer in the film forming apparatus 20 following the cleaning step can be continuously performed without exposing the substrate 11 to be processed to the atmosphere.

In this cleaning step, the lamp light irradiation step is performed, for example, in a high vacuum atmosphere of, for example, about 10 ⁻⁵ Pa or less, or while flowing a small amount of a rare gas or an inert gas.
It is applied in the following reduced pressure atmosphere. At this time, only the adsorbed moisture on the surface can be removed by irradiating the substrate 11 to be treated with lamp light and heating the surface to several hundred degrees Celsius. If the stage temperature is set to, for example, about 100 ° C. by the heater 56 built in the stage 32, the controllability of the heating temperature by lamp light irradiation is improved.

The rare gas used in the discharge plasma treatment of the rare gas or the reverse sputtering may be Ar or the like which has been conventionally used, but by employing Xe, Kr or Rn, it is possible to further reduce the damage before drying. Processing can be performed. A reducing gas such as H ₂ may be added to the rare gas.

Next, a method of manufacturing a highly integrated semiconductor device as an example of an electronic device will be described with reference to FIG.

FIG. 1 is a schematic cross-sectional view showing main steps of a method of manufacturing a semiconductor device. Among them, FIG.
2 shows a substrate to be processed before a cleaning step is performed, and shows a semiconductor substrate 1
A device isolation region 2 formed of a selective oxide film formed on the surface of the device, a gate electrode 3 and an impurity diffusion layer 5 formed in the device region surrounded by the device isolation region 2, and further facing the impurity diffusion layer 5, It has connection holes (contact holes) 7 and the like opened in the interlayer insulating film 6. Also,
Reference numeral 3 'in the figure indicates an adjacent gate electrode (usually W polycide) in a portion extending from the element region onto the isolation region 2 (accordingly, the base is different, but the connection hole 7').
Are also called contact holes).

The impurity diffusion layer 5 and the gate electrodes 3, 3 '
Constitute a conductive layer. On the exposed surfaces of these conductive layers, natural oxide films 8 and the like 8 are formed. As described above, the natural oxide film 8 includes an original natural oxide film and an organic substance such as an etching residue, a resist residue, or a reaction product in a process of forming the connection holes 7 and 7 ′.
Further, a moisture adsorption layer is formed on the surface of the substrate to be processed. This adsorption layer has a very small thickness and is not shown in the figure, but is firmly attached to the surface of the substrate to be processed.

The natural oxide film 8 and the like are removed by the discharge plasma treatment of the rare gas or the reverse sputtering treatment.
That is, although it should be cleaned, the adsorbed layer of water cannot be completely removed by these treatments and may be adsorbed again.

Therefore, before performing discharge plasma treatment or reverse sputtering treatment of these rare gases, lamp light irradiation is performed in a non-oxidizing, reduced-pressure atmosphere, and the surface of the substrate to be treated is treated in a short time, ie, several seconds to several tens of seconds. Is raised to several hundred degrees, and only the moisture adsorption layer is removed. The temperature of the substrate to be processed is selected so that the impurity diffusion layer of an element such as a MOS transistor already formed on the substrate to be processed does not re-diffuse. Then, the interlayer insulating film is cured by heating at the time of lamp light irradiation, and the parasitic capacitance between the upper and lower wirings is reduced (the same applies hereinafter).

FIG. 1B shows a cleaning step by discharge plasma treatment of rare gas or reverse sputtering treatment. Here, a state in which Ar ⁺ is incident on the substrate to be processed and particles such as natural oxide films at the bottoms of the connection holes 7 and 7 ′ are sputtered out is shown. As a rare gas, general A
In addition to r, Xe, Kr, He, Rn, or the like can also be used. Further, a reducing gas such as H ₂ may be added together with the rare gas.

FIG. 1 (c) shows the cleaned connection holes 7,
This is a state in which an upper conductive layer 9 contacting 7 'has been formed. The upper conductive layer 9 is formed by continuously exposing the cleaned substrate to be processed without exposing the substrate to the atmosphere. The upper conductive layer 9 includes a barrier layer 9b and a wiring layer 9a. The barrier layer 9b is made of Ti, TiN, TiSiN, TiS
a single layer or a stack of i refractory metal or its compound such as _2. The wiring layer 9a is made of polycrystalline silicon, Al-based metal,
It is made of a high melting point metal such as W or Mo, or Cu or the like. FIG.
(C) shows a structure in which a contact plug filling the connection holes 7 and 7 ′ and an upper wiring extending over the interlayer insulating film 6 are integrated, but these are formed separately from different materials. You may.

In FIG. 1, the impurity diffusion layer 5 and the gate electrode wiring 3 'of the semiconductor substrate 1 have been described as a lower conductive layer as an example. However, the upper wiring is a conductive layer, and an interlayer insulating film is formed so as to face the upper wiring. May be subjected to the same cleaning step as described above. Further, the pad electrode exposed from the opening of the final passivation film is used as a conductive layer,
This pad electrode may be subjected to the same cleaning step as described above.

FIG. 4 is a schematic cross-sectional view showing main steps of another method of manufacturing a semiconductor device. Among these, FIG.
Shows a substrate to be processed before a cleaning step is performed, and a connection hole (contact hole) 57 is opened in an insulating layer 52 made of an oxide film formed on the surface of a semiconductor substrate 51.
A barrier layer 53b composed of a single layer or a laminate of a refractory metal such as Ti, TiN, TiSiN, TiSi ₂ or a compound thereof and a wiring composed of a refractory metal such as polycrystalline silicon, an Al-based metal, W or Mo, or Cu. A lower conductive layer 53 having a layered structure with the layer 53a is formed. Then, the interlayer insulating film 5
On the exposed surface of the lower conductive layer 53 exposed to the connection hole (via hole) 55 of No. 4, a natural oxide film 58 or the like is formed. As described above, the natural oxide film 58 includes an original natural oxide film and an organic substance such as an etching residue, a resist residue, or a reaction product in a process of forming the connection hole 57. Further, a moisture adsorption layer is formed on the surface of the substrate to be processed. This adsorption layer has an extremely thin layer,
Although not shown, it is firmly attached to the surface of the substrate to be processed.

The natural oxide film 58 and the like should be removed, that is, cleaned by the rare gas discharge plasma treatment or the reverse sputtering treatment, but the moisture adsorption layer can be completely removed by these treatments. And may be re-adsorbed.

Therefore, before performing the discharge plasma treatment or the reverse sputtering treatment of the rare gas, the apparatus shown in FIG. 2 is used to irradiate the lamp light in a non-oxidizing reduced pressure atmosphere for a short time, that is, several seconds. The temperature of the surface of the substrate to be treated is raised to several hundred degrees in several tens of seconds, and only the moisture adsorption layer is removed. The temperature of the substrate to be processed is selected so that the impurity diffusion layer of an element such as a MOS transistor already formed on the substrate to be processed does not re-diffuse.

FIG. 4B shows a cleaning step by removing water by irradiating a lamp light and removing a natural oxide film 58 by a discharge plasma treatment of rare gas or reverse sputtering treatment. Here, Ar ⁺ is incident on the substrate to be processed, and the connection holes 5
5 schematically shows a state where particles such as a natural oxide film at the bottom of the sample No. 5 are sputtered out. As the rare gas, Xe, Kr, He, Rn, or the like can be used in addition to general Ar. Further, a reducing gas such as H ₂ may be added together with the rare gas.

FIG. 4C shows a state in which an upper conductive layer 59 which contacts the cleaned connection hole 55 is formed.
The upper conductive layer 59 is formed continuously without exposing the cleaned substrate to be processed to the atmosphere. The upper conductive layer 59 is composed of a laminate of a barrier layer 59b and a wiring layer 59a. The barrier layer is made of Ti, TiN, TiSi
N, made of single layer or multilayer of a refractory metal or a compound thereof, such as TiSi _2, also, the wiring layer is made of polycrystalline silicon, Al-based metal, W or refractory metal such as Mo, or Cu.

As described above, similarly to the case of forming the contact hole 57, when forming the multilayer wiring structure via the via hole 55, by applying the present invention, miniaturization, high integration, high performance, and high reliability can be achieved. This is advantageous for device manufacturing.

Here, a dry pretreatment method which is particularly excellent in device characteristics and reliability as a wafer pretreatment method in the metal film forming step of the via plug as shown in FIG. 4 will be described in further detail.

First, in a metal film forming step of a via plug for making contact with the lower metal wiring layer 53, FIG.
As shown in (1), the pretreatment for metal film formation is performed using the plasma processing apparatus 10 having at least the lamp heating mechanism.

That is, when a via plug is formed in the manufacture of an VLSI device, means for improving the electrical characteristics at the interface of the metal junction and the reliability thereof are provided. In the metal film forming process for the wafer that has been processed, plasma processing (commonly called reverse sputtering) is performed as a pre-metal film forming process mainly for cleaning the surface of the lower metal wiring layer, and plasma processing provided with a lamp heating mechanism is also performed. This is performed using an apparatus.

Thus, in the pretreatment process immediately before metal film formation, in addition to the heat transfer from the wafer stage whose temperature has been controlled and heated, vacuum heating from the wafer surface by the infrared lamp can be quickly performed. Therefore, compared with the case of using only the radiant heat and ion irradiation from the conventional plasma, the water adsorbed on the wafer surface after the via hole is formed is more effectively desorbed and removed from the wafer to be processed.
The surface of the lower metal wiring layer at the bottom of the via hole can be cleaned. For this reason, during the subsequent formation of the barrier metal and the wiring material layer, outgas from the wafer to be processed is suppressed, and the process is not adversely affected by the impurity gas. Can be formed. As a result, the electrical characteristics of the via plug are improved, such as the contact resistance at the metal interface of the fine via hole of the sub-quarter micron generation is reduced, and the manufacture of a high-speed ultra LSI device can be performed stably. .

In the plasma treatment for the via hole, the ion assist effect (cathode voltage drop) under the action of the high-frequency electric field can be used, so that the exposed surface of the lower metal can be sufficiently treated (this is because This is an advantage of using plasma, and in this sense, the same applies to the other examples described above and examples described later.)

As another wafer processing method, in the metal film forming step of the via plug for making contact with the lower metal wiring layer, the wafer to be processed can be lamp-heated at least before the process processing as shown in FIG. This is to perform a pretreatment for metal film formation after applying a vacuum heating process in advance using the plasma processing apparatus 40 having the preliminary vacuum chamber 30.

That is, as described above, when forming a via plug in the manufacture of an VLSI device, a lamp heating method is provided to provide a means for further improving the electrical characteristics at the interface of the metal junction and the reliability thereof. Using a plasma processing apparatus having a mechanism in a preliminary vacuum (load lock) chamber, a metal film forming process is performed on a wafer having a via hole formed therein.

Thus, before performing the reverse sputtering process by the discharge plasma as the pre-process of the metal sputtering film formation of the via hole, the infrared light is held while holding the wafer to be processed on the wafer stage heated and controlled in the preliminary vacuum chamber. By performing lamp heating by irradiation, it becomes possible to perform a wafer heating process under a high vacuum, and by the heating effect, moisture adsorbed on the wafer surface after the via hole is formed without adversely affecting a subsequent sputtering process. It can be effectively evaporated and removed from the wafer to be processed in advance. For this reason, outgassing from the wafer to be processed in the reverse sputtering process before metal film formation is suppressed, and processing optimized for cleaning the surface of the lower metal wiring layer at the via hole opening is required. In addition to improving the stability of the pretreatment process, outgassing during the subsequent deposition process of the barrier metal and the wiring material layer is more effectively suppressed. , It is possible to form a via plug with high purity metal. As a result,
The electrical characteristics of the via plug are improved, such as the contact resistance at the metal interface of the fine via hole of the quarter-micron generation is further reduced, and it becomes possible to more stably manufacture a high-speed LSI device.

Further, as still another wafer processing method,
In the metal film forming step of the via plug for making contact with the lower metal wiring layer, a metal film pre-treatment is performed by using at least a discharge plasma of a reducing gas in the apparatus of FIG. 2 or FIG.

That is, in order to form a via plug having better electric characteristics at the interface of the metal junction, as in the above-described case, as a pretreatment for forming a metal film in the via hole, the wafer is heated and then sputter-etched. When performing the treatment, instead of an inert gas usually used, such as HCl,
A plasma treatment is performed by introducing a gas having a reducing property to the lower conductive layer into the processing chamber.

Thus, sputter etching is performed while chemically reducing and removing the natural oxide film on the surface of the lower metal wiring layer under the via hole, which is formed due to moisture adsorbed on the wafer surface or oxygen in the atmosphere. Progresses, and the metal film pretreatment can be performed in a form in which the above-described processing effect is further enhanced. In addition, dangling bonds of metal atoms that may be formed on the surface of the lower metal wiring layer serving as an interface of the metal junction are terminated by Cl atoms (other halogen elements) having a high electronegativity and disappear, thereby chemically reducing the dangling bonds. Since the active state is formed, the bonding state with the metal to be formed next is also stabilized, and the contact resistance of the via plug can be further reduced.

[0078]

EXAMPLES Hereinafter, the present invention will be described in more detail with reference to examples (however, the following examples are merely illustrative and do not limit the present invention in any way).

Embodiment 1 In this embodiment, the first method of the present invention is applied to the formation of a contact in a contact hole in a manufacturing process of an VLSI device, and the process is performed by a continuous processing apparatus shown in FIG. This is an example in which after removing a moisture adsorption layer on the surface of a treatment substrate by irradiation with lamp light, a natural oxide film or the like of a conductive layer exposed at the bottom of a connection hole is cleaned by discharge plasma of a rare gas. This step will be described below with reference to FIG.

The substrate 11 to be processed before the cleaning process shown in FIG. 1A has the above-described structure, of which the semiconductor substrate 1 is a single crystal silicon, the interlayer insulating film 6 is SiO ₂ , and the gate electrode 3 is Each was made of polycrystalline silicon, high melting point metal polycide, or the like. The opening diameter of the connection holes 7 and 7 'is about 0.
24 μm, and the thickness of the interlayer insulating film 6 was about 1.0 μm. On the exposed surfaces of the gate electrode 3 ′, which is a conductive layer, and the impurity diffusion layer 5, a natural oxide film 8 was formed.
In (a), the native oxide film 8 is shown thicker than it actually is for the sake of explanation.) Further, a moisture adsorption layer (not shown) was present on the entire surface of the substrate 11 to be processed.

The substrate 11 shown in FIG. 1A is loaded onto the stage 12 of the lamp light irradiation / plasma processing apparatus 10 shown in FIG. 2 and irradiated with the lamp light by the lamp 16 under the following conditions. gave. Lamp light irradiation: Ar 100 sccm Pressure 3 Pa Stage temperature 100 ° C. Time 120 sec By this lamp light irradiation, the surface of the substrate 11 to be treated was heated to several hundred ° C., and the moisture adsorption layer was removed.

Thereafter, in the same lamp light irradiation and plasma processing apparatus 10, a rare gas discharge plasma processing is performed under the following conditions. At this time, the lamp light power was turned off. Discharge plasma treatment of rare gas: Ar 25 sccm Pressure 0.7 Pa Stage temperature 100 ° C. ICP source power 1 kW (450 kHz) Substrate bias voltage 200 V (13.56 MHz) Time 60 sec The substrate bias voltage suppresses damage to the substrate 11 to be processed. For example, about 10 to 300 V, preferably 50
２５０250 V is selected, and here, it is set to 200 V.

In the step of removing the natural oxide film and the like, that is, in the step of cleaning, A shown by a solid arrow as shown in FIG.
By the irradiation of r ⁺ ions, the native oxide film 8 and the like 8 at the bottoms of the connection holes 7 and 7 ′ are sputtered out and removed as sputtered particles indicated by broken arrows. The irradiation energy of Ar ⁺ ions in this example was relatively low, and the possibility of damaging the substrate 11 to be processed was small.

The cleaned substrate 11 was conveyed under vacuum to the stage 22 of the film forming apparatus 20 via the gate valve 17, and the upper conductive layer 9 was immediately formed. In this embodiment, as the upper conductive layer 9, a barrier layer 9b having a thickness of 120 nm and a wiring layer 9a made of an Al-Cu alloy having a thickness of 600 nm are formed by sputtering. Among them, the barrier layer 9b had a three-layer structure of Ti / TiN / Ti, and was formed to have a thickness of 30 nm / 60 nm / 30 nm.
FIG. 1C shows a state in which the upper conductive layer 9 is formed. Thereafter, the upper conductive layer 9 was etched into a desired wiring pattern or buried in the connection holes 7 and 7 'by CMP (Chemical Mechanical Polishing) to form a contact plug.

According to the present embodiment, the plasma discharge treatment of the rare gas is performed after the adsorbed moisture is removed by irradiating the lamp light, so that the low resistance interlayer connection free from the influence of the natural oxide film or the adsorbed water is stabilized. It was possible to form.

Embodiment 2 In this embodiment, the second method of the present invention is applied to the formation of a contact in a contact hole in a manufacturing process of an VLSI device, and the process is performed by a continuous processing apparatus shown in FIG. This is an example in which after removing the moisture adsorbing layer on the surface of the processing substrate by irradiation with lamp light, a natural oxide film or the like on the conductive layer surface exposed at the bottom of the connection hole is cleaned by reverse sputtering. This step will be described below with reference to FIG.

The substrate 11 to be processed before the cleaning process shown in FIG. 1A is the same as that of the first embodiment, and a duplicate description will be omitted. The substrate to be processed is carried on the stage 32 of the lamp light irradiation device 30 shown in FIG.
6, and irradiation with lamp light was performed. Lamp light irradiation conditions: Pressure 1 × 10 ⁻⁷ Pa Stage temperature 110 ° C. Time 120 sec In this lamp light irradiation step, a processing gas such as Ar was not flown, and a vacuum was pulled by a high vacuum pump (the pressure was 1
If it is × 10 ⁻⁷ Pa or less, there is no possibility that the substrate 11 to be processed is oxidized.) By the irradiation with the lamp light, the surface of the substrate 11 to be treated was heated to several hundred degrees Celsius, and the moisture adsorption layer was removed.

Thereafter, the substrate 11 to be processed was transferred onto the stage 42 of the film forming pretreatment apparatus 40, and subjected to reverse sputtering with Ar gas under the following conditions. Reverse sputtering conditions: Ar 25 sccm Pressure 0.7 Pa Stage temperature 100 ° C. Plasma generation power 600 W (2 MHz) Bias voltage 250 V (13.56 MHz) Time 60 sec The bias voltage is, for example, 10 to 300 V in order to suppress damage to the substrate 11 to be processed. Degree, preferably 50-2
A voltage of about 50 V was selected, and was set to 250 V here.

In the step of removing the natural oxide film or the like, that is, in the step of cleaning, A shown by a solid arrow as shown in FIG.
By the irradiation of r ⁺ ions, the native oxide film 8 and the like 8 at the bottoms of the connection holes 7 and 7 ′ are sputtered out and removed as sputtered particles indicated by broken arrows. In this embodiment, the irradiation energy of Ar ⁺ ions was controlled to be relatively low, and the possibility of damaging the substrate 11 to be processed was small.

The cleaned substrate 11 was conveyed under vacuum to the stage 22 of the film forming apparatus 20 via the gate valve 47, and the upper conductive layer 9 was immediately formed. The process of forming the upper conductive layer 9 may be the same as that of the first embodiment, and a duplicate description will be omitted.

According to the present embodiment, the removal of adsorbed moisture by lamp light irradiation is performed in an independent lamp light irradiation device, so that the released moisture does not contaminate the inside of the chamber of the reverse sputtering device. The same effect as that of No. 1 was able to be further enhanced.

Embodiment 3 In this embodiment, the third method of the present invention is applied to formation of a via plug in a process for manufacturing an VLSI device, and an ICP having a lamp heating mechanism shown in FIG.
(Inductively Coupled Plasma) This is an example in which a pre-process of forming a metal film on a via hole is performed using a processing apparatus. This step will be described below with reference to FIG.

As shown in FIG. 4A, a wafer used as a sample in this embodiment was prepared in which a via hole 55 desired in a lower metal wiring layer 53 was formed in an interlayer insulating film 54. Here, the lower metal wiring layer 5
3 is a barrier metal 53b made of TiN / Ti (thickness 70 nm / 30 nm) and Al-0.5% Cu (thickness 0.3 mm).
5 μm). At this time, a natural oxide film 58 or the like was grown thinly on the metal surface at the bottom of the via hole 55, and moisture was adsorbed on the surface of the substrate to be processed (however, in the drawing, for convenience of expression). , Thicker than it actually is).

The wafer 11 in this state was set in the sputtering apparatus 10 shown in FIG. In this sputtering apparatus, an inductively coupled plasma (ICP) connected to a metal film forming chamber 20 under a high vacuum and having a lamp heating mechanism is provided.
a) In the on-board deposition pre-processing chamber 21, metal deposition pre-processing was performed, for example, under the following conditions.

Vacuum heating holding (lamp light irradiation): Ar 100 sccm pressure 3 Pa Wafer stage temperature 100 ° C. ICP source power 0 kW (450 kHz) Substrate bias voltage 0 V (13.56 MHz) IR lamp ON time 120 sec Reverse sputtering process (discharge of rare gas) Plasma treatment): Ar 25 sccm Pressure 0.7 Pa Wafer stage temperature 100 ° C. ICP source power 1 kW (450 kHz) Substrate bias voltage 350 V (13.56 MHz) IR lamp OFF time 60 sec

In the present embodiment, the first stage of vacuum heating and holding is performed several times by irradiation of the resistance heater 56 built in the wafer stage 12 and the infrared light lamp 16 installed opposite to the wafer stage 12. Rapid wafer temperature rise to 100 ° C and uniform and high-precision wafer temperature control were realized.

The state of the wafer after the plasma processing is substantially as shown in FIG.
^{Due to the +} ion irradiation, the natural oxide film 58 growing on the bottom of the via hole 55 is effectively removed by sputtering.
The surface of the lower metal wiring layer 53 serving as the contact interface of the via plug was cleaned.

In the present embodiment, the heat transfer from the wafer stage 12 which has been first temperature-controlled and heated and the infrared light lamp 1
Since the wafer before the plasma processing is subjected to the vacuum heat treatment in advance by the irradiation of the step 6, the substantial wafer processing is performed, so that the moisture adsorbed on the wafer surface after the formation of the via holes 55 is processed by the vacuum heat processing. After the wafer was effectively desorbed and removed from the wafer, a process for film formation pretreatment gradually progressed under relatively low substrate bias conditions while the wafer was subjected to plasma radiation heat and ion incident energy.

The wafer having been subjected to the film forming pretreatment is transferred to the metal film forming chamber 20 connected under high vacuum through the gate valve 17 and, as an example, TiN / Ti
(Thickness 60 nm / 30 nm) barrier metal layer 5
9b and an Al-0.5% Cu layer 59a (0.6 μm thick)
By forming the upper metal wiring layer 59 consisting of m) continuously by sputtering, the formation of the via plug and the wiring material layer was completed as shown in FIG. 4C.

During the metal film forming process, the generation of gas released from the wafer to be processed is effectively suppressed by the film forming pretreatment to which the present invention is applied, and the process atmosphere is adversely affected by the impurity gas. Thus, a via plug and a wiring material layer could be formed.

According to the present embodiment, since the gas released from the wafer to be processed is suppressed during the metal film forming process of the via hole, a high-purity metal is formed and the adhesion of the metal around the via plug is reduced. And the connection resistance and the wiring resistance at the metal interface can be reduced.
As a result, the electrical characteristics and reliability of the fine via plugs of the sub-quarter micron generation were improved, and the manufacturing yield of the VLSI device operating at high speed could be improved.

Embodiment 4 In this embodiment, the second method of the present invention is applied to the formation of a via plug in the process of manufacturing an VLSI device. This is an example in which a wafer is preliminarily vacuum-heated in a (load lock) chamber, then transferred to a triode-type RF plasma processing chamber, and pre-processed for metal film formation in a via hole. This step will be described below with reference to FIG.

The wafer used as a sample in this example was the same as that used in Example 3 (see FIG. 4A).

The wafer 11 in this state was set on the lamp light irradiation device 30 shown in FIG. The lamp light irradiation device 30 was connected to a metal film pretreatment chamber 40 under a high vacuum, and in the pre-vacuum chamber 25, for example, a vacuum heating process was performed on the wafer under the following conditions. Vacuum heating and holding (irradiation with lamp light): pressure 1 × 10 ⁻⁷ Pa or less Wafer stage temperature 110 ° C. time 120 sec.
Irradiation of the resistance heater 56 built in 2 and the infrared light lamp 38 installed opposite to the wafer stage 32 enables rapid temperature rise of the wafer to several hundred degrees Celsius and uniform and accurate wafer temperature control. It was realized.

Next, the wafer 11 was transferred to a metal film pre-processing chamber 26, which is a triode type RF plasma apparatus, and subjected to a film pre-processing by sputter etching under the following conditions as an example. Reverse sputtering treatment: HCl / Ar 5/25 sccm Pressure 0.7 Pa Wafer stage temperature 100 ° C. Plasma source power 600 W (2 MHz) Substrate bias voltage 350 V (13.56 MHz) Time 60 sec

[0106] wafer state after the plasma treatment in the same manner as in Example 3, as generally shown in FIG. 4 (b), receives and Ar ⁺ ion irradiation from the discharge plasma, the growth on the bottom of the via hole 55 The natural oxide film 58 that had been removed was effectively removed by spattering, and the surface of the lower metal wiring layer 53, which was the contact interface of the via plug, was cleaned.

In this embodiment, in a pre-vacuum (load lock) chamber independent of the process chamber for performing the plasma processing, heat is transferred from the wafer stage heated and controlled in advance and the lamp is irradiated with infrared light. Since vacuum heating is applied to the wafer before the plasma processing, the moisture adsorbed on the wafer surface after the via hole is formed is effectively removed and removed from the wafer by the vacuum heating. The wafer is carried into the pre-processing chamber.

Therefore, in this embodiment, the amount of gas released from the base in the reverse sputtering process before metal film formation can be reduced without the moisture desorbed from the wafer contaminating the process chamber due to the heating effect in advance. Therefore, even when the number of processed wafers is increased, the stability of the film forming pretreatment process is greatly improved.

In the plasma treatment as the film forming pretreatment, in addition to the sputtering action of Ar ⁺ ions,
The natural oxide film 58 on the surface of the lower metal wiring layer 53 was more effectively removed with a chemical reaction due to the reducing action by Cl, and a cleaner metal surface was exposed. Furthermore, in the present embodiment, the dangling bonds of the metal atoms on the outermost surface of the wiring layer 53 are terminated by Cl atoms having a high electronegativity, and are in a chemically more active state.

The wafer 11 which has been subjected to the film forming pretreatment is transferred to the metal film forming chamber 27 connected under a high vacuum through the gate valve 47, and as an example, TaN / Ta
(Thickness 60 nm / 30 nm) barrier metal layer 5
9b and Cu-0.5% Al layer 59a (0.6 μm thick)
By forming the upper metal wiring layer 59 consisting of m) continuously by sputtering, the formation of the via plug and the wiring material layer was completed as shown in FIG. 4C.

During the metal film forming process, the same effect as that of the third embodiment (the effect of suppressing the generation of outgassed gas from the wafer to be processed) is further enhanced by the film forming pretreatment to which the present invention is applied. Thus, a higher quality via plug and wiring material layer could be formed without the process atmosphere being adversely affected by the impurity gas.

According to the present embodiment, after the surface of the lower metal wiring layer serving as the contact interface is further cleaned, outgassing from the wafer to be processed is more effectively suppressed during the metal film forming process of the via hole. Therefore, the adhesion of the metal around the via plug is further improved, and the connection resistance and the wiring resistance at the metal interface can be further reduced. As a result, the electrical characteristics and reliability of the fine via plugs of the sub-quarter micron generation were further improved, and the production yield of ultra-high speed LSI devices could be further improved.

The present invention has been described above. However, the present invention is not limited to the above-described examples, and the device or element structure, the processing apparatus, the process conditions, and the like in the above-described examples do not depart from the gist of the present invention. It can be appropriately modified or selected within the range.

For example, in the above-mentioned example, the case where the ICP high-density plasma processing apparatus and the triode type RF plasma processing apparatus are used as the metal film pre-processing apparatus has been described.
In addition, orthodox parallel plate RF plasma processing equipment, TCP, ECR, helicon wave plasma, etc.
Application to a manufacturing method using a high-density plasma processing apparatus other than ICP is also possible.

Although Ar was used in the discharge plasma treatment step and the reverse sputtering step of the rare gas, He, Xe,
As Kr, another rare gas such as Rn may be used, or a reducing gas such as H ₂ may be added and used. As the reducing gas, HCl was used in Example 4 described above, but other gases such as H ₂ and HF can be used. Among them, in the case of a liquid source such as HCl or HF, it is preferable to introduce the liquid source into the process chamber by a method such as bubbling with a carrier gas such as He, heating and vaporizing, and ultrasonic vaporizing.

Further, a halogen lamp, a Xe arc lamp, an infrared lamp, or the like may be used for lamp light irradiation for removing moisture in the metal film formation pretreatment.

The conductive layer on the substrate to be processed may be a semiconductor film of a thin film transistor in addition to the impurity diffusion layer and the gate electrode / wiring formed on the silicon substrate. As a semiconductor substrate, in addition to silicon, SiG
Compound semiconductors such as e, Ge, and GaAs may be used.
In addition, the configuration of the substrate to be processed can be appropriately changed.

[0118]

As described above, according to the present invention, moisture adsorbed on the surface of the substrate to be treated is rapidly desorbed and removed by irradiating light in a non-oxidizing, reduced-pressure atmosphere. A natural oxide film or the like is removed by subjecting the processing substrate to at least a rare gas discharge plasma treatment or a reverse sputtering treatment.

Therefore, it is possible to stably remove adsorbed moisture, a natural oxide film and the like or etching residues without damaging the substrate to be treated as a base, and the surface of the substrate to be treated after cleaning is adsorbed by the adsorbed moisture. No natural oxide film, etc. are present, and if the upper conductive layer is formed continuously, no outgassing occurs, the contact resistance at the contact interface is reduced, and a connection with a fine opening diameter and a high aspect ratio is formed. Even with holes, a low-resistance and highly reliable interlayer connection structure can be formed.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device as an example of an electronic device according to the present invention in the order of steps.

FIG. 2 is a schematic cross-sectional view of an example of a continuous processing apparatus applied to a method of manufacturing an electronic device according to the present invention.

FIG. 3 is a schematic cross-sectional view of another example of a continuous processing apparatus applied to a method of manufacturing an electronic device according to the present invention.

FIG. 4 shows a UL as another example of an electronic device according to the present invention.
FIG. 4 is a schematic cross-sectional view illustrating a method for manufacturing an SI device in the order of steps.

[Explanation of symbols]

1, 51: semiconductor substrate, 2: element isolation region, 3, 3 '...
Gate electrode, 5 ... impurity diffusion layer, 6, 52, 54 ... interlayer insulating film, 7, 7 ', 55, 57 ... connection hole, 8, 58 ... natural oxide film, etc. 9, 59 ... upper conductive layer, 9a, 53a, 5
9a: wiring layer, 9b, 53b, 59b: barrier layer, 10
... Lamp light irradiation and plasma processing apparatus, 11 ... Substrate to be processed, 12, 22, 32, 42 ... Stage, 13, 43 ...
Bias power supply, 14 ICP coil, 15 ICP power supply, 16, 36 lamp, 17, 37, 47 gate valve, 20 film forming apparatus, 21, 25, 26, 27 ... chamber, 23 ... target, 24 ... Sputtering power supply,
Reference numeral 30: lamp light irradiation device, 40: film forming pretreatment device, 45
... counter electrode, 46 ... plasma generation power supply, 48 ... grid electrode, 53 ... lower wiring, 56 ... heater

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA01 AA02 AA05 BB14 BB25 BB30 CC01 DD22 DD23 DD37 DD78 DD80 FF16 HH15 5F004 AA14 BA14 BA20 BB05 BB26 BC05 BC06 BD05 DA22 DA23 DA24 DA29 EB01 EB03 FA08 5F033H00H08H11H08 HH18 HH19 HH20 HH27 HH33 JJ01 JJ04 JJ08 JJ11 JJ18 JJ19 JJ20 JJ27 JJ33 KK01 KK04 KK08 KK11 KK18 KK19 KK20 KK27 KK33 MM05 MM07 MM08 NN06 NN07 PP06 PP15 PP19 Q78Q98 Q92 Q92

Claims (17)

[Claims] A step of opening a connection hole facing the conductive layer in an interlayer insulating film formed on the conductive layer formed on the substrate to be processed; and a surface of the conductive layer exposed at the bottom of the connection hole. A method of manufacturing an electronic device, comprising: a step of cleaning; and a step of continuously forming an upper conductive layer at least in the connection hole. A step of irradiating the substrate with a lamp light in a reduced-pressure atmosphere, and a step of subjecting the substrate to be processed to discharge plasma treatment of at least a rare gas. 2. The cleaning step is performed in a plasma processing chamber provided with a lamp light irradiation device, and the upper conductive layer forming step is performed by connecting a gate valve to the plasma processing chamber. The method for manufacturing an electronic device according to claim 1, wherein the method is performed in a film chamber. 3. A step of opening a connection hole facing the conductive layer in an interlayer insulating film formed on the conductive layer formed on the substrate to be processed, and a surface of the conductive layer exposed at a bottom of the connection hole. A method of manufacturing an electronic device, comprising: a step of cleaning the substrate to be processed; and a step of continuously forming an upper conductive layer at least in the connection hole. A step of irradiating the substrate with a lamp light in a reduced-pressure atmosphere, and a step of subjecting the substrate to be processed to reverse sputtering. 4. The step of irradiating the lamp light in the cleaning step is performed in a preliminary vacuum chamber provided with a lamp light irradiation device, and the reverse sputtering process includes a step of setting a gate valve in the preliminary vacuum chamber. 4. The method according to claim 3, wherein the step of forming the upper conductive layer is performed in a film formation chamber connected to the film formation pretreatment chamber via a gate valve. 6. The method for manufacturing an electronic device according to claim 1. 5. A step of opening a connection hole as a via hole facing the lower conductive layer in an interlayer insulating film formed on the lower conductive layer formed on the substrate to be processed, and exposing a bottom of the connection hole. A method of manufacturing an electronic device, comprising: a step of cleaning the surface of the lower conductive layer thus formed; and a step of forming at least an upper conductive layer in the connection hole. In the equipped plasma processing chamber,
A method of manufacturing an electronic device, wherein the method is performed by irradiating the substrate to be processed with light and performing plasma processing. 6. The cleaning step includes: irradiating the substrate to be processed with lamp light in a non-oxidizing, reduced-pressure atmosphere; and performing reverse sputtering or at least discharge plasma treatment of a rare gas on the substrate to be processed. The method of manufacturing an electronic device according to claim 5, further comprising: 7. The method for manufacturing an electronic device according to claim 6, wherein the plasma processing is performed under the action of discharge plasma of a gas having a reducing action. 8. The method according to claim 5, wherein the step of forming the upper conductive layer is performed continuously in a film forming chamber connected to the plasma processing chamber. 9. The method according to claim 8, wherein the film is formed by sputtering. 10. A cleaning chamber for cleaning the surface of the conductive layer exposed at the bottom of the connection hole opened in the interlayer insulating film on the conductive layer formed on the substrate to be processed; An apparatus for manufacturing an electronic device, comprising: a film formation chamber for forming an upper conductive layer; wherein the cleaning chamber is a plasma processing chamber including at least a light irradiation device, and is configured to irradiate the substrate to be processed with light irradiation and plasma processing. An apparatus for manufacturing an electronic device, characterized in that the apparatus is configured to perform the following. 11. The cleaning chamber includes: a light source for irradiating the substrate to be processed with lamp light in a non-oxidizing reduced-pressure atmosphere; and a reverse sputtering process or at least a discharge of a rare gas to the substrate to be processed. The apparatus for manufacturing an electronic device according to claim 10, further comprising: a plasma generating unit that performs a plasma process. 12. The light source according to claim 1, wherein the light source is arranged outside the cleaning chamber having a light transmitting part at least in part.
2. The apparatus for manufacturing an electronic device according to claim 1. 13. The apparatus for manufacturing an electronic device according to claim 11, wherein said plasma generating means is configured to generate inductively coupled plasma. 14. The apparatus for manufacturing an electronic device according to claim 11, wherein the plasma processing is performed under the action of discharge plasma of a gas having a reducing action. 15. The apparatus for manufacturing an electronic device according to claim 10, wherein the upper conductive layer is continuously formed in a film forming chamber connected to the plasma processing chamber. 16. The apparatus according to claim 15, wherein the film is formed by sputtering. 17. The apparatus according to claim 10, wherein the connection hole is formed as a contact hole or a via hole.