JP4158248B2 - Manufacturing method of electronic device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing an electronic device, and more particularly, to an electronic device including a highly integrated semiconductor device, before entering a metallization step of an upper conductive layer in an interconnection of a multilayer wiring structure. The present invention relates to a method for manufacturing an electronic device characterized by a pretreatment process.
[0002]
[Prior art]
With the progress of high integration of semiconductor devices such as ULSI (Ultra Large Scale Integrated Circuits), the design and design rules thereof are becoming finer, and multilayer wiring structures are being used frequently. In a multilayer wiring structure, a lower conductive layer and an upper conductive layer are electrically connected via a connection hole (via contact hole, hereinafter abbreviated as a via hole) formed in an interlayer insulating film. This via hole is also in the direction of miniaturization. For example, in a semiconductor device having a minimum design rule of 0.18 μm, the opening diameter of the via hole is about 0.24 μm. Since the thickness of the interlayer insulating film itself is about 0.5 μm from the relationship between the capacitance between wirings and the withstand voltage, the aspect ratio of the connection hole is about 2.
[0003]
In order to realize a low-resistance and high-reliability multi-layer wiring structure with such a fine opening diameter via hole, a natural oxide film inevitably formed on the lower conductive layer surface exposed at the bottom of the via hole or A pretreatment process for removing contaminants (hereinafter abbreviated as a natural oxide film), that is, a cleaning process is indispensable.
[0004]
The natural oxide film or the like on the surface of the lower conductive layer exposed at the bottom of the via hole is mainly composed of an oxide of the lower conductive layer material, and also contains etching residue, resist residue, adsorbed moisture, and the like. For removal of this natural oxide film etc., Ar⁺Dry cleaning using reverse sputtering with ions has been proposed, and has been put into practical use for pretreatment of via holes using Al-based metal or the like as a lower conductive layer. Ar⁺Since the directionality of ions can be controlled by an electric field or the like, it is easy to remove a natural oxide film or the like at the bottom of a fine via hole. However, in removing the natural oxide film etc. on the surface of the lower conductive layer extending from the gate electrode, incident Ar⁺Concerns have been pointed out that the gate insulating film may be destroyed due to the accumulation of charges due to ions.
[0005]
Therefore, the present inventor has disclosed a soft etching method using a low substrate bias and a high-density plasma processing apparatus as a pretreatment method in forming an upper conductive layer through a via hole in Japanese Patent Application Laid-Open No. 7-094473. . According to this method, low energy Ar⁺Low damage cleaning using ions is possible. Further, the decrease in the etching rate that is concerned about this can be compensated by the improvement of the plasma density.
[0006]
[Problems to be solved by the invention]
By adopting a pre-processing method by soft etching using such a low substrate bias and high-density plasma processing apparatus, great progress has been made in cleaning the natural oxide film and the like at the bottom of via holes that have been miniaturized. However, the moisture firmly adsorbed on the surface of the substrate to be processed cannot be completely removed, and an outgas is generated when the upper conductive layer is formed, or the electrical characteristics at the contact interface are unstable in the long term. He left a fear of becoming a factor.
[0007]
In the present situation where the degree of integration of semiconductor devices is further advanced, for example, the thickness of the gate insulating film is 10 nm or less, and the depth of the impurity diffusion layer is also becoming thinner, there is a further less damage and stable cleaning method. desired. In addition to sputtering formation of Al-based metal as the upper conductive layer, a stricter degree of cleanness is required when a high melting point metal such as tungsten or a metal such as low resistance copper is formed by CVD or electroplating. Is done.
[0008]
This invention makes it the subject to solve the problem of the background art mentioned above.
That is, the present invention can remove and clean a small amount of adsorbed water as well as a natural oxide film on a substrate to be processed even in a semiconductor device to which a sub-quarter micron design rule is applied. An object of the present invention is to provide an electronic device manufacturing method that can be performed without damaging the substrate to be processed.
[0009]
[Means for Solving the Problems]
  The method of manufacturing an electronic device according to the present invention is proposed in order to achieve the above-described problem. That is, in the method for manufacturing an electronic device according to the present invention, the step of opening a connection hole facing the lower conductive layer in the interlayer insulating film formed on the lower conductive layer on the substrate to be processed, exposed at the bottom of the connection hole A method of manufacturing an electronic device comprising a step of cleaning a surface of a lower conductive layer, and a step of continuously forming an upper conductive layer in at least the connection hole, wherein the cleaning step includes plasma generation power and a substrate. Using a plasma processing apparatus that can control the bias voltage independently, after gradually increasing the plasma generation power to a predetermined power value, a substrate bias voltage with a constant voltage is applied, and the substrate to be processed is sputter-etched to the bottom of the connection hole This is a step of removing the natural oxide film on the exposed surface of the lower conductive layer. Sputter etching is performed in a rare gas.HCl or H ₂ Consist ofIt is characterized by being applied by a non-oxidizing gas to which a reducing gas is added.
[0010]
  According to another method of manufacturing the electronic device of the present invention, a step of opening a connection hole facing the lower conductive layer in a lower interlayer insulating film formed on the conductive layer on the substrate to be processed, exposed at the bottom of the connection hole. A method of manufacturing an electronic device comprising: a step of cleaning the surface of the lower conductive layer, and a step of continuously forming an upper conductive layer in at least the connection hole. Using a plasma processing apparatus capable of independently controlling the substrate bias voltage, the plasma generation power is gradually increased to a predetermined power value, and the substrate bias voltage is gradually increased to the predetermined voltage value, and the substrate to be processed is sputter etched, This is a process to remove the natural oxide film on the surface of the lower conductive layer exposed at the bottom of the connection hole.HCl or H ₂ Consist ofIt is characterized by being applied by a non-oxidizing gas to which a reducing gas is added.
[0011]
  In any electronic device manufacturing method, this sputter etching isIn rare gas, HCl or H ₂ A reducing gas consisting ofIt is desirable to apply with a non-oxidizing gas. Non-oxidizing means inactive or reducing.
[0012]
In any method for manufacturing an electronic device, the plasma processing apparatus is 1 × 10^Tencm^-31 × 10 or more¹⁴cm^-3It is desirable to have a plasma source that can provide a plasma density of less than.
[0013]
Needless to say, continuous means that the substrate to be processed is transported to a conductive layer forming apparatus by a vacuum gate valve or the like without being exposed to a polluted atmosphere such as the air, and the next step of forming an upper conductive layer is performed. . By such continuous processing, it is possible to avoid reoxidation and re-adsorption of the cleaned substrate to be processed, and to form an upper conductive layer.
[0014]
As a plasma generation method suitably employed in the present invention, the plasma generation power and the substrate bias voltage can be individually controlled, and a triode type parallel plate type plasma processing apparatus is exemplified. In addition, an ICP (Inductively Coupled Plasma) method, a TCP (Transformer Coupled Plasma) method, a helicon wave plasma method, an ECR (Electron Cyclotron Resonance) plasma method, etc. having a higher density plasma generation source are more preferably employed. These devices are 1x10¹¹cm^-3It has the above high-density plasma generation source. Higher plasma density is desirable, but 1 × 10¹⁴cm^-3The plasma density is almost the limit value in the current high-density plasma processing apparatus.
[0015]
Electronic devices targeted by the present invention include TFT (Thin Film Transistor), highly integrated semiconductor devices such as memory, logic, CCD (Charge Coupled Device), multilayer coil type thin film magnetic head device, thin film Examples thereof include microelectronic devices such as an inductor device, a thin film coil device, a micromachine device, etc., in which multilayer wiring using connection holes is employed.
[0016]
[Action]
According to the present invention, even when the impedance of the processing chamber changes due to contamination or the like, impedance matching can be easily obtained by gradually increasing the plasma generation power, that is, in a small step or steplessly, and the plasma is smooth. The discharge can be continued stably. By applying a substrate bias in this state, stable sputter etching can be performed on the substrate to be processed.
[0017]
Further, when the substrate bias is gradually increased, the influence on the sustaining of the discharge is small, so that the plasma becomes more stable, and more stable sputter etching can be performed on the substrate to be processed.
[0018]
Therefore, even if the number of batches of the substrate to be processed is repeated, it is possible to perform cleaning with uniform and low damage.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
First, a configuration example of a plasma processing apparatus used in the method for manufacturing an electronic device according to the present invention will be described with reference to FIGS.
[0020]
FIG. 2 is a schematic cross-sectional view of a triode parallel plate type plasma processing apparatus.
In other words, the substrate 10 to be processed is placed in the plasma processing chamber 16, and the grid electrode 15 is positioned at an intermediate position between the substrate stage 11, which is also one of the electrodes, the counter electrode 13, and the capacitive electrodes arranged in parallel. Is arranged. A substrate bias power source 12 for applying a substrate bias potential is connected to the substrate stage 11, and a plasma generation power source 14 is connected to the counter electrode 13, while the lattice electrode 15 is set to the ground potential.
In FIG. 2, details of the apparatus such as a gas introduction unit, a gas exhaust unit, and a loading / unloading unit for the substrate 10 to be processed are not shown. Further, a film forming apparatus such as a sputtering apparatus for vacuum-transferring the substrate 10 to be processed in a subsequent process and continuously forming an upper conductive layer is not shown.
[0021]
According to the plasma processing apparatus of FIG.⁹cm^-3While the plasma 17 of the stage is generated, the incident energy of ions to the substrate 10 can be controlled independently of the input level of the plasma generation power source 14. That is, Ar in the plasma 17⁺The positive ions, such as ions, pass through the lattice electrode 15 and are incident on the substrate 10 to be processed by the weak substrate bias potential formed by the substrate bias power source 12 to clean the surface. Most of the generated gaseous reaction product is exhausted by the gas exhaust means.
If a magnet is arranged on the back side of the counter electrode 13 or around the plasma processing chamber 16 and configured as a magnetron parallel plate type plasma processing apparatus using the magnetron motion of electrons in the plasma 17, 10.^Tencm^-3The plasma density of the stage can be obtained.
[0022]
FIG. 3 is a schematic cross-sectional view of an inductively coupled plasma (ICP) processing apparatus.
That is, the substrate stage 11 on which the substrate 10 to be processed is placed is disposed in the plasma processing chamber 16. A substrate bias power source 12 that applies a substrate bias potential is connected to the substrate stage 11. Inductive coupling coils 18 are wound around the plasma processing chamber 16 made of a dielectric material such as quartz or alumina, and an ICP power source 19 is connected thereto.
In FIG. 3, details of the apparatus such as the gas introducing means, the gas exhausting means, and the means for carrying in / out the substrate 10 to be processed are not shown. Further, a film forming apparatus such as a sputtering apparatus for vacuum-transferring the substrate 10 to be processed in a subsequent process and continuously forming an upper conductive layer is not shown.
[0023]
According to the plasma processing apparatus of FIG. 3, the alternating electric field formed by the inductive coupling coil 18 causes 1 × 10 1.¹¹cm^-31 × 10 or more¹⁴cm^-3It is possible to generate a high-density plasma 17 of less than about. A large amount of Ar in the plasma 17⁺The positive ions such as are incident on the substrate 10 to be processed by a weak substrate bias potential formed by the substrate bias power source 12.
[0024]
A schematic cross-sectional view of the substrate stage 11 of the plasma processing apparatus of FIGS. 2 and 3 is shown in FIG.
In the substrate stage 11 on which the substrate 10 to be processed is placed, a heater 21 and a refrigerant pipe 22 for circulating a refrigerant such as ethanol and Fluorinert (trade name) are arranged. A temperature sensor and temperature control (not shown) are provided. By means, the temperature of the substrate to be processed 10 can be controlled to a desired temperature. The surface of the substrate stage 11 immediately below the substrate 10 to be processed is made of ceramics such as quartz in which fine grooves having a radial shape or the like are formed, and an electrostatic chucking electrode 20 is embedded below the ceramic stage. A heat conduction medium introduction hole 23 is formed through the central portion of the substrate stage 11 to introduce a heat conduction gas such as He gas.
[0025]
With the configuration of the substrate stage 11 in FIG. 4, the substrate 10 to be processed is in close contact with the surface of the substrate stage 11, and the temperature of the substrate 10 to be processed can be controlled with high accuracy by adding a heat conduction effect by the heat conduction gas. .
[0026]
According to the plasma processing apparatus illustrated in FIGS. 2 and 3, the temperature of the substrate to be processed is controlled to a desired temperature within a range of, for example, 80 ° C. to 700 ° C., and the substrate bias potential is relatively high within a range of 10V to 300V. While maintaining a low potential, the substrate to be treated can be irradiated with rare gas ions or hydrogen active species. Therefore, not only the removal of the natural oxide film under low damage conditions, but also the adsorbed moisture is sufficiently removed, there is no risk of recontamination and reoxidation, and low resistance and high reliability in the subsequent upper conductive layer formation process. Can be formed.
[0027]
Next, a method for manufacturing a highly integrated semiconductor device will be described as an example of an electronic device with reference to FIG.
[0028]
FIG. 1 is a schematic cross-sectional view showing the main steps of the semiconductor device manufacturing method.
Among these, FIG. 1A shows the substrate to be processed before the cleaning process is performed. A lower interlayer insulating film 2 is formed on the semiconductor substrate 1, and a contact hole 3 is opened facing an impurity diffusion layer (not shown) formed in the semiconductor substrate 1. A lower conductive layer 4 is formed in the contact hole 3 and on the lower interlayer insulating film 2. The lower conductive layer 4 includes a barrier layer and a wiring layer from the bottom. The lower barrier layer is Ti, TiN, Ti or TiSi₂It consists of a single layer or a laminate of a refractory metal such as, or a compound thereof. The wiring layer is made of Al-based metal, refractory metal such as W or Mo, refractory metal polycide, polycrystalline silicon, or Cu or Ag which is a low resistance wiring material.
[0029]
An upper interlayer insulating film 6 is formed on the lower conductive layer 4, and a connection hole (via hole) 7 is opened here. A natural oxide film 5 or the like is formed on the surface of the lower conductive layer 4 exposed at the bottom of the connection hole 7. The natural oxide film 5 includes an original natural oxide film and an organic substance such as an etching residue, a resist residue, or a reaction product in the connection hole 7 forming step. Further, a moisture adsorption layer (not shown) is formed on the entire surface of the substrate to be processed. The adsorption layer has a very thin layer thickness and is firmly attached to the surface of the substrate to be processed, although not shown.
[0030]
If the upper conductive layer forming step is performed in a later step while the natural oxide film 5 or the like is present, adverse effects such as deterioration of the embedded shape and an increase in contact resistance are caused.
Therefore, an object of the present invention is to remove the natural oxide film 5 and the like completely and without damaging elements such as MOS transistors formed on the semiconductor substrate.
[0031]
FIG. 1B shows a cleaning process in which the natural oxide film 5 or the like is being removed. That is, discharge plasma treatment of non-oxidizing gas, here Ar⁺The state where the natural oxide film 5 is sputtered out by ion irradiation treatment is schematically shown. At this time, the temperature of the substrate to be processed is controlled to 100 ° C. or higher. Alternatively, the substrate to be processed has already been heat-treated in a reduced pressure atmosphere. In this state, adsorbed moisture is also removed at the same time. If the substrate to be treated is preheated, most of the adsorbed moisture has already been removed, but this discharge plasma treatment removes it almost completely.
As the rare gas, Xe, Kr, He, Rn or the like can be used in addition to general Ar. Along with rare gas, H₂A reducing gas such as HCl or HF may be added.
[0032]
FIG. 1C shows a state in which an upper conductive layer 8 exposed to the bottom of the connection hole 7 and in contact with the cleaned lower conductive layer 4 surface is formed. The upper conductive layer 8 is formed continuously without exposing the cleaned substrate to be processed to the atmosphere, and is patterned. The upper conductive layer 8 is also composed of a barrier layer and a wiring layer from the bottom. The lower barrier layer is Ti, TiN, Ti or TiSi₂It consists of a single layer or a laminate of a refractory metal such as, or a compound thereof. The upper wiring layer is made of an Al-based metal, a refractory metal such as W or Mo, polycrystalline silicon, or Cu or Ag which is a low resistance wiring material.
FIG. 1C shows a structure in which a contact plug for embedding the connection hole 7 and an upper layer wiring extending on the upper interlayer insulating film 6 are integrated. However, even if these are configured separately from different materials, FIG. Good.
[0033]
FIG. 1 shows a cleaning process of the natural oxide film 5 on the surface of the lower conductive layer 4 exposed at the bottom of the connection hole 7 as an example. An interlayer insulating film is further formed on the upper conductive layer 8, and this interlayer insulation is formed. A cleaning step may be performed on the connection hole formed facing the upper conductive layer 8 exposed from the connection hole opened in the film. Further, the pad electrode exposed from the opening of the final passivation film may be a lower conductive layer, and the pad electrode may be cleaned.
[0034]
【Example】
Hereinafter, the present invention will be described in more detail by way of examples. However, these examples are merely illustrative, and the present invention is not limited to the following examples.
[0035]
[Example 1]
In this embodiment, the trioxide parallel plate type plasma processing apparatus shown in FIG. 2 is used to clean the natural oxide film on the surface of the lower conductive layer exposed at the bottom of the connection hole by sputtering with a rare gas. At this time, the plasma generation power was gradually increased to a predetermined value, and then a substrate bias voltage having a predetermined value was applied. This process will be described again with reference to FIG.
[0036]
The substrate to be processed before the cleaning process shown in FIG. 1A has the above-described configuration. Among these, the semiconductor substrate 1 is a silicon single crystal, and the lower interlayer insulating film 2 is SiO.₂The lower conductive layer 4 has a laminated structure of a barrier layer made of TiN / Ti = 70/30 nm and a wiring layer made of Al-0.5% Cu and having a thickness of 0.5 μm. On this lower conductive layer 4, there is SiO.₂An upper interlayer insulating film 6 made of is formed, and a connection hole 7 facing the lower conductive layer 4 is formed. The opening diameter of the connection hole 7 is about 0.24 μm, the thickness of the upper interlayer insulating film 6 is about 0.5 μm, and the aspect ratio of the connection hole 7 is about 2.
[0037]
A natural oxide film 5 or the like is undesirably formed on the surface of the lower conductive layer 4 exposed at the bottom of the connection hole 7, and an adsorbed moisture layer (not shown) is firmly attached. In FIG. 1A, the natural oxide film 5 is displayed thicker than the actual thickness for the sake of explanation.
[0038]
The substrate to be processed shown in FIG. 1A was loaded onto the substrate stage 11 of the plasma processing apparatus shown in FIG. 2, and sputter etching with a rare gas was performed in the following three steps.
(Step 1)
Ar 25 sccm
Pressure 0.7 Pa
Plasma generation power 300 W (2 MHz)
Substrate bias voltage 0 V
Substrate stage temperature 50 ℃
Time 5 sec
(Step 2)
Ar 25 sccm
Pressure 0.7 Pa
Plasma generation power 600 W (2 MHz)
Substrate bias voltage 0 V
Substrate stage temperature 50 ℃
Time 5 sec
(Step 3)
Ar 25 sccm
Pressure 0.7 Pa
Plasma generation power 600 W (2 MHz)
Substrate bias voltage 250 V (13.56 MHz)
Substrate stage temperature 50 ℃
60 sec
[0039]
In this sputter etching process, plasma discharge rises smoothly in step 1, plasma is stabilized with a predetermined power in step 2, and in the last step 3, sputter etching with relatively low energy rare gas ions is started.
[0040]
In this sputter etching process, Ar indicated by a solid arrow as shown in FIG.⁺By the ion irradiation, the natural oxide film 5 etc. at the bottom of the connection hole 7 is sputtered out and removed as a gaseous reaction product indicated by a broken line arrow. Ar in this example⁺The ion irradiation energy is relatively low, and there is little risk of damage to the substrate 10 to be processed. Ar⁺The ion irradiation density is high, and the etching rate does not decrease.
[0041]
The cleaned substrate 10 is vacuum-transferred via a gate valve onto a stage of a sputtering apparatus, which is an example of a film forming apparatus (not shown), and the upper conductive layer 8 is immediately formed. In this embodiment, as the upper conductive layer 8, a barrier layer made of TiN / Ti = 60/30 nm and a wiring layer made of Al-0.5% Cu and having a thickness of 0.6 μm are continuously formed by sputtering. It consists of a laminated structure. The state where the upper conductive layer 8 is formed is shown in FIG. In the sputtering process of the upper conductive layer 8, the amount of gas released from the substrate 10 to be processed is small, and the surface of the lower conductive layer 4 exposed from the connection hole 7 is cleaned. Can be formed. Thereafter, the upper conductive layer 8 is etched into a desired wiring pattern or buried in the connection hole 7 by CMP (Chemical Mechanical Polishing) to form a via contact plug.
[0042]
10 samples per 100 batches continuously processed according to this example.^FourAlthough the resistance value in the test circuit in which each via chain was formed was within a predetermined value, the yield rate was 100%.
In contrast, the non-defective product ratio of the same test circuit of the sample subjected to 100 batch continuous processing by adding the plasma generation power and the substrate bias voltage in one step remained at 30%.
[0043]
[Example 2]
In this embodiment, the natural oxide film on the surface of the conductive layer exposed at the bottom of the connection hole is cleaned by sputter etching using the plasma processing apparatus shown in FIG. At this time, both the plasma generation power and the substrate bias voltage were applied while gradually increasing. Sputter etching was performed by adding reducing gas HCl. This process will be described again with reference to FIG.
[0044]
The substrate to be processed before the cleaning process shown in FIG. 1A is the same as that in the first embodiment, and a duplicate description is omitted.
The substrate to be processed was carried onto the substrate stage 11 of the plasma processing apparatus shown in FIG. 3, and sputter etching with an Ar / HCl mixed gas was performed in the following three steps.
(Step 1)
Ar 25 sccm
HCl 5 sccm
Pressure 0.3 Pa
ICP power 500 W (450 kHz)
Substrate bias voltage 0 V
Substrate stage temperature 50 ℃
Time 5 sec
(Step 2)
Ar 25 sccm
HCl 5 sccm
Pressure 0.3 Pa
ICP power 750 W (450 kHz)
Substrate bias voltage 50 V (13.56 MHz)
Substrate stage temperature 50 ℃
Time 5 sec
(Step 3)
Ar 25 sccm
HCl 5 sccm
Pressure 0.3 Pa
ICP power 1000 W (450 kHz)
Substrate bias voltage 100 V (13.56 MHz)
Substrate stage temperature 50 ℃
Time 40 sec
[0045]
In this sputter etching process, plasma discharge rises smoothly at step 1, and plasma generation power is increased at step 2, and a substrate bias voltage with very low energy is applied. In step 3, the plasma is stabilized with a predetermined power and sputter etching is performed with Ar / HCl with a predetermined substrate bias.
Note that the application of the substrate bias voltage may be started in step 3.
[0046]
In this sputter etching process, since the sputter etching is performed in a higher vacuum atmosphere than in the first embodiment, high-density ion species enter the substrate to be processed without scattering. This incident energy is relatively low energy, and Ar indicated by a solid arrow as shown in FIG.⁺The natural oxide film 5 exposed at the bottom of the connection hole 7 is sputtered out by ion irradiation, and is removed as a gaseous reaction product indicated by a broken arrow. At the same time, due to the added HCl, the natural oxide film 5 is also subjected to a reduction reaction, and is more effectively removed, exposing a clean conductive layer surface.
[0047]
The cleaned substrate 10 is vacuum-transferred via a gate valve onto a stage of a sputtering apparatus, which is an example of a film forming apparatus (not shown), and the upper conductive layer 8 is immediately formed. Also in this embodiment, as the upper conductive layer 8, a barrier layer made of TiN / Ti = 60/30 nm and a wiring layer made of Al-0.5% Cu and having a thickness of 0.6 μm are continuously sputtered. It consists of the laminated structure formed into a film. The state where the upper conductive layer 8 is formed is shown in FIG. Thereafter, the upper conductive layer 8 is etched into a desired wiring pattern or buried in the connection hole 7 by CMP to form a via contact plug. The upper conductive layer 8 may be formed by vacuum deposition or CVD.
[0048]
10 samples per 100 batches continuously processed according to this example.^FourAlthough the resistance value in the test circuit in which each via chain was formed was within a predetermined value, the yield rate was 100%.
In contrast, the non-defective product ratio of the same test circuit of the sample subjected to 100 batch continuous processing by adding the plasma generation power and the substrate bias voltage in one step remained at 35%.
[0049]
As mentioned above, although the present invention was explained in detail by two examples, the present invention is not limited to these examples.
[0050]
For example, the plasma generation power and the substrate bias voltage are both increased stepwise (stepped), but the number of steps is not limited to the example. Further, it may be gradually increased steplessly and smoothly.
[0051]
Further, as the plasma processing apparatus, an ECR plasma processing apparatus, a helicon wave plasma processing apparatus, or the like can be adopted in addition to the triode type parallel plate type plasma processing apparatus and the ICP apparatus. From the standpoint of cleaning with low ion energy, the ion density is 1 × 10¹¹cm^-3The above high-density plasma processing apparatus is preferably used.
[0052]
In sputter etching of these non-oxidizing gases, Ar is used, but other rare gases such as He, Xe, Kr, or Rn may be used, and H or H may be used as a reducing gas in addition to HCl.₂Etc. may be used.
[0053]
In addition to the gate electrode / wiring formed on the silicon substrate, the lower conductive layer on the substrate to be processed may be an impurity diffusion layer, a semiconductor film of a thin film transistor, or the like. In addition to silicon, the semiconductor substrate may be a compound semiconductor such as SiGe, Ge, or GaAs.
[0054]
In addition, it goes without saying that the configuration of the substrate to be processed can be appropriately changed.
The present invention is directed to a microelectronic device employing multilayer wiring or electrode formation by connection holes, such as a multilayer coil thin film magnetic head device, a thin film inductor device, a thin film coil device, or a micromachine device, in addition to a semiconductor device. .
[0055]
【The invention's effect】
As is apparent from the above description, according to the method for manufacturing an electronic device of the present invention, even in a fine electronic device such as a highly integrated semiconductor device to which a sub-quarter micron design rule is applied, the substrate to be processed is less damaged. In addition, a uniform cleaning process can be performed.
[0056]
Therefore, an interlayer connection structure using a connection hole having a fine opening diameter and a high aspect ratio in an electronic device such as a highly integrated semiconductor device can have low resistance and high reliability.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view illustrating steps of a method for manufacturing a semiconductor device as an example of an electronic device according to the invention.
FIG. 2 is a schematic cross-sectional view of a plasma processing apparatus applied to an electronic device manufacturing method of the present invention.
FIG. 3 is a schematic cross-sectional view of another plasma processing apparatus applied to the method for manufacturing an electronic device of the present invention.
4 is a schematic cross-sectional view showing a configuration of a substrate stage of the plasma processing apparatus of FIGS. 2 and 3. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Lower interlayer insulating film, 3 ... Contact hole, 4 ... Lower conductive layer, 5 ... Natural oxide film, etc. 6 ... Upper interlayer insulating film, 7 ... Connection hole (via hole), 8 ... Upper conductive layer
DESCRIPTION OF SYMBOLS 10 ... Substrate to be processed, 11 ... Substrate stage, 12 ... Substrate bias power source, 13 ... Counter electrode, 14 ... Plasma generation power source, 15 ... Grid electrode, 16 ... Plasma processing chamber, 17 ... Plasma, 18 ... Inductive coupling coil, 19 ... ICP power supply, 20 ... Electrostatic adsorption electrode, 21 ... Heater, 22 ... Refrigerant piping, 23 ... Heat conduction medium introduction hole

Claims (2)

Opening a connection hole facing the lower conductive layer in an interlayer insulating film formed on the lower conductive layer on the substrate to be processed;
Cleaning the surface of the lower conductive layer exposed at the bottom of the connection hole;
A method of manufacturing an electronic device comprising a step of continuously forming an upper conductive layer in at least the connection hole,
The cleaning step uses a plasma processing apparatus capable of independently controlling a plasma generation power and a substrate bias voltage, and gradually increases the plasma generation power to a predetermined power value, and then applies the substrate bias voltage with a predetermined voltage value. , The step of sputter etching the substrate to be processed to remove the natural oxide film on the surface of the lower conductive layer exposed at the bottom of the connection hole,
The sputter etching is performed by a non-oxidizing gas obtained by adding a reducing gas composed of HCl or H ₂ to a rare gas. Opening a connection hole facing the lower conductive layer in an interlayer insulating film formed on the lower conductive layer on the substrate to be processed;
Cleaning the surface of the lower conductive layer exposed at the bottom of the connection hole;
A method of manufacturing an electronic device comprising a step of continuously forming an upper conductive layer in at least the connection hole,
The cleaning step uses a plasma processing apparatus capable of independently controlling the plasma generation power and the substrate bias voltage, and gradually increases the plasma generation power to a predetermined power value and gradually increases the substrate bias voltage to a predetermined voltage value. Applying, sputter etching the substrate to be processed, and removing a natural oxide film on the surface of the lower conductive layer exposed at the bottom of the connection hole,
The sputter etching is performed by a non-oxidizing gas obtained by adding a reducing gas composed of HCl or H ₂ to a rare gas.

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