US20130001692A1 - Semiconductor Devices Including a Layer of Polycrystalline Silicon Having a Smooth Morphology - Google Patents
Semiconductor Devices Including a Layer of Polycrystalline Silicon Having a Smooth Morphology Download PDFInfo
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- US20130001692A1 US20130001692A1 US13/610,552 US201213610552A US2013001692A1 US 20130001692 A1 US20130001692 A1 US 20130001692A1 US 201213610552 A US201213610552 A US 201213610552A US 2013001692 A1 US2013001692 A1 US 2013001692A1
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- silicon dioxide
- semiconductor substrate
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- polycrystalline silicon
- ion implantation
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 107
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 74
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/3003—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
Definitions
- silicon dioxide films are pretreated with hydrogen ions to prepare the surface of the silicon dioxide film for the deposition of a layer of polycrystalline silicon to provide for a thinner and smoother polycrystalline silicon film.
- the silicon dioxide is pretreated by ion beam bombardment by a Kaufman ion source.
- Hydrogen ion beam pretreatment is typically performed using a Kaufman ion beam source directed normally to the substrate.
- a Kaufman ion source employs a metal grid to accelerate ions at a particular target.
- metal from the metal grid sputters off of the grid and becomes implanted in the target object causing the target object to become contaminated.
- the effect of damage caused by sputtered metal from the metal grid increases.
- PSII Plasma source ion implantation
- various materials such as tools, aluminum cans and artificial joints, to improve their wear, friction and corrosion properties.
- PSII is a process by which ions are implanted into a target at energies high enough to bury the ions below the target's surface.
- an ionized plasma is formed about the target in an enclosed chamber.
- a high voltage pulse is applied to the target relative to the conductive walls of the chamber. Ions from the plasma are then driven into the surfaces of the target from all sides simultaneously without any manipulation of the target.
- Conrad describes that plasma source ion implantations may be performed on complex three-dimensional objects formed from materials such as pure metals, alloys, semi-conductors, ceramics and organic polymers. Conrad describes the process as providing significant increases in surface hardness of metals and ceramics and providing changes in the optical properties and electrical conductivity of organic polymers.
- the present invention solves that current need by providing a method by which a silicon dioxide film is prepared so that a subsequently deposited polycrystalline film is deposited smoothly and uniformly onto the silicon dioxide film.
- One aspect of the present invention is directed to a method for controlling the morphology of deposited silicon on a layer of silicon dioxide.
- the method comprises the steps of: providing a layer of silicon dioxide; implanting hydrogen ions into the layer of silicon dioxide by plasma source ion implantation; and forming a layer of polycrystalline silicon on the layer of silicon dioxide.
- Another aspect of the present invention is directed to a method for pretreating silicon dioxide comprising the steps of: providing a layer of silicon dioxide; and implanting hydrogen ions into a surface of the layer of silicon dioxide by plasma source ion implantation.
- Yet another aspect of the present invention is directed to a method for forming a semiconductor device precursor comprising the steps of: providing a semiconductor substrate; forming a layer of silicon dioxide on the semiconductor substrate; implanting hydrogen ions by plasma source ion implantation into the layer of silicon dioxide; and forming a layer of polycrystalline silicon on the layer of silicon dioxide.
- Still another aspect of the present invention is directed to a method for forming a semiconductor device precursor comprising the steps of: providing a semiconductor substrate; forming a layer of silicon dioxide on said semiconductor substrate; exposing said semiconductor substrate to a hydrogen plasma containing hydrogen ions; and applying a high voltage pulse to said semiconductor substrate thereby implanting hydrogen ions from said ionized hydrogen plasma into a surface of said layer of silicon dioxide so that a subsequently formed layer of polycrystalline silicon has a smooth morphology.
- An additional aspect of the present invention is directed to a method for forming a semiconductor device precursor comprising the steps of: providing a semiconductor substrate; forming a layer of silicon dioxide on said semiconductor substrate; exposing said semiconductor substrate to a hydrogen plasma containing hydrogen ions; applying a high voltage pulse to said semiconductor substrate to implant hydrogen ions from said ionized hydrogen plasma into a surface of said layer of silicon dioxide so that a subsequently formed layer of polycrystalline silicon has a smooth morphology; and forming a layer of polycrystalline silicon on said surface of said layer of silicon dioxide.
- a further aspect of the present invention is directed to a method for forming a semiconductor device comprising the steps of: providing a semiconductor substrate; forming a layer of silicon dioxide on the semiconductor substrate; implanting hydrogen ions by plasma source ion implantation into the layer of silicon dioxide; and forming a layer of polycrystalline silicon on the layer of silicon dioxide.
- Another aspect of the present invention is directed to a method for forming a field effect transistor comprising the steps of: providing a semiconductor substrate having a layer of silicon dioxide formed thereon; implanting hydrogen ions by plasma source ion implantation into the layer of silicon dioxide; forming a layer of polycrystalline silicon on the layer of silicon dioxide; and forming a source, a drain and a gate in the semiconductor substrate to form a field effect transistor.
- Still another aspect of the present invention is directed to a method for forming a memory array.
- the memory array includes a plurality of memory cells arranged in rows and columns with each of the plurality of memory cells including at least one field effect transistor.
- This method comprises the steps of: providing a semiconductor substrate; forming a layer of silicon dioxide on at least a portion of the semiconductor substrate; implanting hydrogen ions into at least a portion of the layer of silicon dioxide by plasma source ion implantation; forming a layer of polycrystalline silicon over at least the portion of the layer of silicon dioxide into which the hydrogen ions were implanted; and forming a gate, a source and a drain for each of the field effect transistors, on the semiconductor substrate.
- the semiconductor device precursor includes a semiconductor substrate.
- a layer of silicon dioxide is formed on the semiconductor substrate.
- the layer of silicon dioxide has been doped with hydrogen ions deposited by a plasma source ion implantation process to provide a subsequently deposited layer of polycrystalline silicon with a smooth morphology.
- a layer of polycrystalline silicon is formed on the layer of silicon dioxide.
- Another aspect of the present invention is directed to a method for making a thin film transistor.
- the method comprises the steps of: providing a semiconductor substrate formed from a material selected from the group consisting of silicon dioxide, quartz and glass; forming a layer of a gate oxide material in the semiconductor substrate; implanting, by plasma source ion implantation, hydrogen ions into a surface of the semiconductor substrate; forming a layer of polycrystalline silicon on the surface of the semiconductor substrate; forming a layer of an insulating material on the layer of polycrystalline silicon; and forming a source region, a drain region and a gate electrode.
- the thin film transistor includes a semiconductor substrate formed from a material selected from the group consisting of silicon dioxide, quartz and glass.
- the semiconductor substrate has hydrogen ions implanted therein by plasma source ion implantation.
- a layer of polycrystalline silicon is formed on at least a portion of semiconductor substrate.
- a layer of a insulating material is formed on at least a portion of the layer of polycrystalline silicon.
- a source region and a drain region are formed on the layer of polycrystalline silicon.
- a gate electrode is formed on the layer of insulating material.
- FIGS. 2A-2C present cross sectional views of various stages in the manufacture of the field effect transistor shown in FIG. 2 ;
- FIG. 3 shows a schematic view of a memory array formed by the method of the present invention
- FIG. 3A shows a schematic view of a memory cell of the memory array shown in FIG. 3 ;
- FIG. 4 shows a schematic view of a wafer manufactured by the method of the present invention.
- the precursor 10 includes a semiconductor substrate 12 , a layer 14 of silicon dioxide 16 and a layer 18 of polycrystalline silicon 20 .
- the substrate 12 can be formed of any material currently in use in the art to form substrates for semiconductors and integrated circuits.
- the substrate 12 can be formed from silicon which can be oxidized to form the layer 14 of silicon dioxide 16 .
- Other useful materials for substrate 12 include, but are not limited to, gallium arsenide, indium phosphide, polycrystalline silicon, silicon dioxide, glass and quartz. Glass, quartz and silicon dioxide are particularly useful if the precursor 10 is further processed into a thin film transistor, such as that described below in connection with FIG. 5 .
- the layer 14 of silicon dioxide 16 is formed on the substrate 12 by any conventional oxidation process or deposition process, and has been doped with hydrogen ions to provide a surface conducive to the deposition of polycrystalline silicon.
- the layer 14 of silicon dioxide 16 can be formed by thermal oxidation, chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), metalorganic chemical vapor deposition (MOCVD), and sputtering.
- the layer 18 of polycrystalline silicon 20 is formed on the layer 14 of silicon dioxide 16 by any deposition process currently used in the art to form a layer of polycrystalline silicon on a layer of silicon dioxide.
- Useful deposition methods include, but are not limited to, CVD, LPCVD, PECVD, MOCVD and sputtering.
- the layer 14 of silicon dioxide 16 is doped by plasma source ion implantation (PSII).
- Plasma source ion implantation is also referred to as plasma doping (PLAD), plasma immersion ion implantation (PI.sup.3) and plasma implantation (PI).
- PLD plasma doping
- PI plasma immersion ion implantation
- PI plasma implantation
- the term “plasma source ion implantation” incorporates and encompasses “plasma doping,” “plasma implantation,” and “plasma immersion ion implantation.”
- a useful plasma source ion implantation technique and device are taught in U.S. Pat. No. 4,764,394 to Conrad, which is incorporated herein by reference in its entirety. Using the Conrad technique, the substrate 12 is placed in a chamber which has walls formed from an electrically conductive material.
- the substrate 12 is placed on an arm which is electrically connected to a high voltage pulse power supply, such as a pulse line-pulse transformer type or a high voltage tube modulated pulser.
- a high voltage pulse power supply such as a pulse line-pulse transformer type or a high voltage tube modulated pulser.
- the chamber is filled with hydrogen gas under a very low pressure in the range of form about 10.sup. ⁇ 1 to about 10.sup. ⁇ 4 Torr.
- the gas is; then ionized to form a plasma containing hydrogen ions.
- the plasma can be generated by any of a variety of plasma sources, including, but not limited to, hot filament, radio frequency, electron cyclotron resonance, magneton and glow discharge resulting from the target bias itself.
- a large negative pulse with respect to the chamber is applied to the substrate 12 to accelerate ions from the plasma toward the layer 14 of silicon dioxide 16 , to create a plasma sheath around the substrate 12 , and to implant the ions into the layer 14 of silicon dioxide 16 .
- a plasma density, useful for implanting an appropriate amount of hydrogen ions into the layer 14 ranges from about 10.sup.6 ions/cm.sup.3 to about 10.sup.11 ions/cm.sup.3.
- the resulting layer 18 of polycrystalline silicon 20 is provided with a smooth morphology.
- smooth it is meant that, when the layer 18 is measured by atomic force microscopy, the layer 18 of polycrystalline silicon 20 has a root mean square (rms) deviation of from about 5 nm to about 12 nm.
- FIG. 2 presents a cross sectional view of a field effect transistor 50 formed by the method of the present invention.
- the field effect transistor 50 is formed on a semiconductor substrate 52 .
- the field effect transistor 50 includes a gate oxide 54 , a source 56 and a drain 58 .
- the gate oxide 54 , the source 56 and the drain 58 are formed on the substrate 52 .
- a layer 64 of polysilicon 66 is formed on the gate oxide 54 to form a gate electrode 70 .
- a pair of spacers 68 are formed on the sides of the layer 64 of polysilicon 66 .
- a layer 72 of a field oxide 74 is also formed on the substrate 52 .
- FIGS. 2A-2C A method for making the field effect transistor 50 is shown in FIGS. 2A-2C .
- the layer 72 of the field oxide 74 is formed on the substrate 52 by means of a conventional local oxidation of silicon (LOCOS) process.
- LOC local oxidation of silicon
- a gate oxide 54 is formed on substrate 52 .
- the surface of the substrate 52 is then conditioned or pretreated so that the subsequently formed layer 64 of polycrystalline silicon 66 has a smooth morphology.
- the surface of the substrate 52 is pretreated by implanting hydrogen ions into the surface of the substrate 52 through plasma source ion implantation by the method described above.
- FIG. 2A shows a layer 64 of polysilicon 66 having been formed on the surface of the substrate 52 .
- the layer 64 of polysilicon 66 covers and, as shown in FIG. 2A , is in contact with the gate oxide 54 .
- the source 56 and the drain 58 are formed by any conventional conductive doping technique currently in use in the art. Desirably, the source 56 and the drain 58 are formed by a self aligned technique.
- a layer 80 of a dielectric material 68 is formed on the gate 54 and over the source 56 and drain 58 .
- the layer 80 will be a layer of an oxidized material and is provided at a thickness such that it serves as an insulating layer. Any material used in the art to form spacers would be useful for forming the layer 80 of dielectric material 68 .
- the dielectric material 68 is silicon dioxide or silicon nitride.
- the resulting field effect transistor 50 is shown in FIG. 2 .
- the field effect transistor 50 may also be used in a typical memory array, such as, for example, a static random access memory (SRAM) array or a dynamic random access memory (DRAM) array 100 , which is shown in FIG. 3 .
- the DRAM array 100 comprises a plurality of memory cells 102 arranged in rows and columns. As shown in FIG. 3A , each of the memory cells 102 includes at least one field effect transistor 50 and one capacitor 104 .
- the field effect transistor 50 may be the field effect transistor 50 , described above and shown in FIG. 2 . The method for forming the field effect transistor 50 is described above in connection with the description of FIGS. 2A to 2C . Each field effect transistor 50 is coupled to a capacitor 104 .
- the gate of the field effect transistor 50 is coupled to a word line 106 via an interconnect structure. It should be apparent that other devices such as other transistors, bipolar transistors, resistors, other capacitors and the like, may be interconnected with the field effect transistor 50 .
- the semiconductor device precursor 10 and the method of the present invention are particularly useful in forming thin film transistors and, particularly, thin film transistors which are used to make flat panel displays.
- a thinner layer of polycrystalline silicon is formed on the substrate.
- the final structure of the thin film transistor would be thinner due to the thinner polycrystalline silicon layer and to the layers which are subsequently deposited on the polycrystalline silicon also being thinner.
- a thin film transistor 200 is shown in cross section in FIG. 5 .
- the thin film transistor 200 includes an insulating substrate 202 .
- a layer 204 of a semiconducting material 206 is formed on the surface of the substrate 202 .
- a source region 208 and a drain region 210 are formed on the layer 204 of semiconducting material 206 .
- a layer 212 of a dielectric material 214 is formed on the layer 204 of semiconducting material 206 and covers the source 208 and the drain 210 .
- a layer 216 of a conducting material 218 is formed on the layer 212 of dielectric material 214 to form a gate electrode 220 .
- the insulating substrate 202 can be any material used to form insulating layers in semiconductor devices and is preferably glass, quartz or silicon dioxide. Rather than doping a layer of silicon dioxide which is subsequently deposited on a substrate as when forming a field effect transistor and as described above, when the thin film transistor 200 is being formed, the insulating substrate 202 , itself, is doped with hydrogen ions by the plasma source ion implantation technique described above.
- the layer 204 of semiconducting material 206 is formed on the substrate 202 by any conventional deposition process.
- Useful deposition methods include, but are not limited to, CVD, LPCVD, PECVD, MOCVD and sputtering.
- the layer 204 of semiconducting material 206 can be any material used to form semiconducting layers, including, but are not limited to, gallium arsenide, indium phosphide, polycrystalline silicon, and germanium. Desirably, the layer 204 of semiconducting material 206 is formed from polycrystalline silicon. Once the layer 204 of semiconducting material 206 has been formed, the layer 204 is etched to isolate the various regions of semiconducting material from each other on the surface of the substrate 202 .
- the source region 208 and the drain region 210 are formed on the layer 204 of semiconducting material 206 .
- the source region 208 and the drain region 210 can either be formed in the layer 204 of semiconducting material 206 or formed in the layer 212 of dielectric material 214 .
- the source region 208 and the drain region 210 are formed by any doping technique currently in use in the art.
- the layer 212 of dielectric material 214 is deposited on the layer 204 of semiconducting material 206 . Useful deposition methods include, but are not limited to, thermal oxidation, CVD, LPCVD, PECVD, MOCVD and sputtering.
- the layer 212 of dielectric material 214 can be any material used in the semiconductor manufacturing art to form dielectric layers. Desirably, the dielectric material 214 is silicon dioxide or silicon nitride.
- the method of the present invention can be carried out as a stand-alone process, clustered as part of the semiconductor manufacturing process or as an in situ pretreatment.
Abstract
A method for controlling the morphology of deposited silicon on a layer of silicon dioxide and semiconductor devices incorporating such deposited silicon are provided. The method comprises the steps of: providing a layer of silicon dioxide; implanting hydrogen ions into the layer of silicon dioxide by plasma source ion implantation; and forming a layer of polycrystalline silicon on the layer of silicon dioxide.
Description
- This patent resulted from a continuation application of U.S. patent application Ser. No. 09/605,293, filed Jun. 28, 2000, entitled “Semiconductor Devices Including a Layer of Polycrystalline Silicon Having a Smooth Morphology”, naming David L. Chapek as inventor, which is a division of U.S. Ser. No. 09/072,262, filed May 4, 1998, now U.S. Pat. No. 6,143,631, the disclosures of which are incorporated herein by reference.
- The present invention relates to a method for pretreating a silicon dioxide film to provide a polycrystalline silicon film, which is subsequently deposited on the silicon dioxide film, with a smooth morphology.
- Advancements in semiconductor manufacture have led to increases in the density and miniaturization of microelectronic circuits. As an example, the manufacture of 64 Mb DRAMs is now possible and 256 Mb prototypes are currently being developed. A key requirement for achieving such high device packing density is the formation of increasingly smaller components. One way to make such smaller components is to employ thinner and smoother films when fabricating those components.
- Currently in the art, silicon dioxide films are pretreated with hydrogen ions to prepare the surface of the silicon dioxide film for the deposition of a layer of polycrystalline silicon to provide for a thinner and smoother polycrystalline silicon film. The silicon dioxide is pretreated by ion beam bombardment by a Kaufman ion source. Hydrogen ion beam pretreatment is typically performed using a Kaufman ion beam source directed normally to the substrate. A Kaufman ion source employs a metal grid to accelerate ions at a particular target. During an ion implantation process using a Kaufman ion source, metal from the metal grid sputters off of the grid and becomes implanted in the target object causing the target object to become contaminated. As the size of devices on the target object decreases, the effect of damage caused by sputtered metal from the metal grid increases.
- Plasma source ion implantation (PSII) has been used to dope various materials, such as tools, aluminum cans and artificial joints, to improve their wear, friction and corrosion properties. PSII is a process by which ions are implanted into a target at energies high enough to bury the ions below the target's surface. To implant the ions in the target, an ionized plasma is formed about the target in an enclosed chamber. A high voltage pulse is applied to the target relative to the conductive walls of the chamber. Ions from the plasma are then driven into the surfaces of the target from all sides simultaneously without any manipulation of the target.
- U.S. Pat. No. 4,764,394 to Conrad teaches one method and apparatus for PSII. Conrad describes that plasma source ion implantations may be performed on complex three-dimensional objects formed from materials such as pure metals, alloys, semi-conductors, ceramics and organic polymers. Conrad describes the process as providing significant increases in surface hardness of metals and ceramics and providing changes in the optical properties and electrical conductivity of organic polymers.
- U.S. Pat. No. 5,354,381 to Sheng teaches a plasma immersion ion implantation apparatus which generally is a variation of the apparatus taught by Conrad. The Sheng apparatus uses a pair of power supplies and very short ionization negative pulses applied to the cathode underlying the target in conjunction with or followed by short ionization pulses applied to a second cathode which is facing toward the primary (target) electrode to provide neutralizing electrons.
- Thus, a need has developed in the art for a process by which silicon dioxide films can be pretreated to ensure that a subsequently deposited polycrystalline silicon film will be provided with a smooth morphology but without the contamination problems of present processes.
- The present invention solves that current need by providing a method by which a silicon dioxide film is prepared so that a subsequently deposited polycrystalline film is deposited smoothly and uniformly onto the silicon dioxide film.
- One aspect of the present invention is directed to a method for controlling the morphology of deposited silicon on a layer of silicon dioxide. The method comprises the steps of: providing a layer of silicon dioxide; implanting hydrogen ions into the layer of silicon dioxide by plasma source ion implantation; and forming a layer of polycrystalline silicon on the layer of silicon dioxide.
- Another aspect of the present invention is directed to a method for pretreating silicon dioxide comprising the steps of: providing a layer of silicon dioxide; and implanting hydrogen ions into a surface of the layer of silicon dioxide by plasma source ion implantation.
- Yet another aspect of the present invention is directed to a method for forming a semiconductor device precursor comprising the steps of: providing a semiconductor substrate; forming a layer of silicon dioxide on the semiconductor substrate; implanting hydrogen ions by plasma source ion implantation into the layer of silicon dioxide; and forming a layer of polycrystalline silicon on the layer of silicon dioxide.
- Still another aspect of the present invention is directed to a method for forming a semiconductor device precursor comprising the steps of: providing a semiconductor substrate; forming a layer of silicon dioxide on said semiconductor substrate; exposing said semiconductor substrate to a hydrogen plasma containing hydrogen ions; and applying a high voltage pulse to said semiconductor substrate thereby implanting hydrogen ions from said ionized hydrogen plasma into a surface of said layer of silicon dioxide so that a subsequently formed layer of polycrystalline silicon has a smooth morphology.
- An additional aspect of the present invention is directed to a method for forming a semiconductor device precursor comprising the steps of: providing a semiconductor substrate; forming a layer of silicon dioxide on said semiconductor substrate; exposing said semiconductor substrate to a hydrogen plasma containing hydrogen ions; applying a high voltage pulse to said semiconductor substrate to implant hydrogen ions from said ionized hydrogen plasma into a surface of said layer of silicon dioxide so that a subsequently formed layer of polycrystalline silicon has a smooth morphology; and forming a layer of polycrystalline silicon on said surface of said layer of silicon dioxide.
- A further aspect of the present invention is directed to a method for forming a semiconductor device comprising the steps of: providing a semiconductor substrate; forming a layer of silicon dioxide on the semiconductor substrate; implanting hydrogen ions by plasma source ion implantation into the layer of silicon dioxide; and forming a layer of polycrystalline silicon on the layer of silicon dioxide.
- Another aspect of the present invention is directed to a method for forming a field effect transistor comprising the steps of: providing a semiconductor substrate having a layer of silicon dioxide formed thereon; implanting hydrogen ions by plasma source ion implantation into the layer of silicon dioxide; forming a layer of polycrystalline silicon on the layer of silicon dioxide; and forming a source, a drain and a gate in the semiconductor substrate to form a field effect transistor.
- Still another aspect of the present invention is directed to a method for forming a memory array. The memory array includes a plurality of memory cells arranged in rows and columns with each of the plurality of memory cells including at least one field effect transistor. This method comprises the steps of: providing a semiconductor substrate; forming a layer of silicon dioxide on at least a portion of the semiconductor substrate; implanting hydrogen ions into at least a portion of the layer of silicon dioxide by plasma source ion implantation; forming a layer of polycrystalline silicon over at least the portion of the layer of silicon dioxide into which the hydrogen ions were implanted; and forming a gate, a source and a drain for each of the field effect transistors, on the semiconductor substrate.
- Yet another aspect of the present invention is directed to a semiconductor device precursor. The semiconductor device precursor includes a semiconductor substrate. A layer of silicon dioxide is formed on the semiconductor substrate. The layer of silicon dioxide has been doped with hydrogen ions deposited by a plasma source ion implantation process to provide a subsequently deposited layer of polycrystalline silicon with a smooth morphology. Finally, a layer of polycrystalline silicon is formed on the layer of silicon dioxide.
- An additional aspect of the present invention is directed to a field effect transistor. The field effect transistor includes a semiconductor substrate. A layer of silicon dioxide is formed on at least a portion of the semiconductor substrate. The layer of silicon dioxide has hydrogen ions implanted therein by plasma source ion implantation. A layer of polycrystalline silicon is formed on at least a portion of the layer of silicon dioxide. A source, a drain and a gate are also formed in the semiconductor substrate to complete the field effect transistor.
- Still yet another aspect of the present invention is directed to a memory array. The memory array comprises a semiconductor substrate. A layer of silicon dioxide is formed on at least a portion of the semiconductor substrate. The layer of silicon dioxide has hydrogen ions implanted into at least a portion of the layer of silicon dioxide by plasma source ion implantation. A layer of polycrystalline silicon is formed over at least the portion of the layer of silicon dioxide into which the hydrogen ions were implanted. A plurality of memory cells are arranged in rows and columns on the semiconductor substrate. Each of the plurality of memory cells comprises at least one field effect transistor. Gates, sources and drains for each of the field effect transistors are also formed on the semiconductor substrate.
- A still further aspect of the present invention is directed to a semiconductor wafer. The wafer comprises a wafer including a semiconductor substrate. The wafer is divided into a plurality of die. A layer of silicon dioxide is formed on at least a portion of the semiconductor substrate. On each of the plurality of die the layer of silicon dioxide has hydrogen ions implanted into at least a portion of the layer of silicon dioxide by plasma source ion implantation. A layer of polycrystalline silicon is formed over at least the portion of the layer of silicon dioxide into which the hydrogen ions are implanted. The wafer also includes a repeating series of gates, sources and drains for at least one field effect transistor formed on each of the plurality of die. The series of gates, sources and drains are formed on the semiconductor substrate.
- Another aspect of the present invention is directed to a method for making a thin film transistor. The method comprises the steps of: providing a semiconductor substrate formed from a material selected from the group consisting of silicon dioxide, quartz and glass; forming a layer of a gate oxide material in the semiconductor substrate; implanting, by plasma source ion implantation, hydrogen ions into a surface of the semiconductor substrate; forming a layer of polycrystalline silicon on the surface of the semiconductor substrate; forming a layer of an insulating material on the layer of polycrystalline silicon; and forming a source region, a drain region and a gate electrode.
- Still another aspect of the present invention is directed to a thin film transistor. The thin film transistor includes a semiconductor substrate formed from a material selected from the group consisting of silicon dioxide, quartz and glass. The semiconductor substrate has hydrogen ions implanted therein by plasma source ion implantation. A layer of polycrystalline silicon is formed on at least a portion of semiconductor substrate. A layer of a insulating material is formed on at least a portion of the layer of polycrystalline silicon. A source region and a drain region are formed on the layer of polycrystalline silicon. Finally, a gate electrode is formed on the layer of insulating material.
- It is an object of the present invention to provide a method by which a layer of silicon dioxide, which serves as either a semiconductor substrate or another layer on the substrate, can be pretreated so that a subsequently deposited film of polycrystalline silicon can be deposited on the layer of silicon dioxide free of contaminants and have a smooth morphology. It is also object of the present invention to provide various semiconductor parts and devices which include a layer of polycrystalline silicon having a smooth morphology.
- Other objects and advantages of the invention will be apparent from the following detailed description, the accompanying drawings and the appended claims.
-
FIG. 1 presents a cross sectional view of semiconductor device precursor formed by the method of the present invention; -
FIG. 2 presents a cross sectional view of a field effect transistor formed by the method of the present invention; -
FIGS. 2A-2C present cross sectional views of various stages in the manufacture of the field effect transistor shown inFIG. 2 ; -
FIG. 3 shows a schematic view of a memory array formed by the method of the present invention; -
FIG. 3A shows a schematic view of a memory cell of the memory array shown inFIG. 3 ; -
FIG. 4 shows a schematic view of a wafer manufactured by the method of the present invention; and -
FIG. 5 presents a cross sectional view of a thin film transistor formed by the method of the present invention. - A
semiconductor device precursor 10 formed by the method of the present invention is shown inFIG. 1 . Theprecursor 10 includes asemiconductor substrate 12, alayer 14 ofsilicon dioxide 16 and alayer 18 ofpolycrystalline silicon 20. Thesubstrate 12 can be formed of any material currently in use in the art to form substrates for semiconductors and integrated circuits. For example, thesubstrate 12 can be formed from silicon which can be oxidized to form thelayer 14 ofsilicon dioxide 16. Other useful materials forsubstrate 12 include, but are not limited to, gallium arsenide, indium phosphide, polycrystalline silicon, silicon dioxide, glass and quartz. Glass, quartz and silicon dioxide are particularly useful if theprecursor 10 is further processed into a thin film transistor, such as that described below in connection withFIG. 5 . - With continued reference to
FIG. 1 , thelayer 14 ofsilicon dioxide 16 is formed on thesubstrate 12 by any conventional oxidation process or deposition process, and has been doped with hydrogen ions to provide a surface conducive to the deposition of polycrystalline silicon. Depending upon the nature of thelayer 14 ofsilicon dioxide 16, thelayer 14 ofsilicon dioxide 16 can be formed by thermal oxidation, chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), metalorganic chemical vapor deposition (MOCVD), and sputtering. Thelayer 18 ofpolycrystalline silicon 20 is formed on thelayer 14 ofsilicon dioxide 16 by any deposition process currently used in the art to form a layer of polycrystalline silicon on a layer of silicon dioxide. Useful deposition methods include, but are not limited to, CVD, LPCVD, PECVD, MOCVD and sputtering. - The
layer 14 ofsilicon dioxide 16 is doped by plasma source ion implantation (PSII). Plasma source ion implantation is also referred to as plasma doping (PLAD), plasma immersion ion implantation (PI.sup.3) and plasma implantation (PI). As used herein, the term “plasma source ion implantation” incorporates and encompasses “plasma doping,” “plasma implantation,” and “plasma immersion ion implantation.” A useful plasma source ion implantation technique and device are taught in U.S. Pat. No. 4,764,394 to Conrad, which is incorporated herein by reference in its entirety. Using the Conrad technique, thesubstrate 12 is placed in a chamber which has walls formed from an electrically conductive material. Thesubstrate 12 is placed on an arm which is electrically connected to a high voltage pulse power supply, such as a pulse line-pulse transformer type or a high voltage tube modulated pulser. The chamber is filled with hydrogen gas under a very low pressure in the range of form about 10.sup.−1 to about 10.sup.−4 Torr. The gas is; then ionized to form a plasma containing hydrogen ions. The plasma can be generated by any of a variety of plasma sources, including, but not limited to, hot filament, radio frequency, electron cyclotron resonance, magneton and glow discharge resulting from the target bias itself. A large negative pulse with respect to the chamber is applied to thesubstrate 12 to accelerate ions from the plasma toward thelayer 14 ofsilicon dioxide 16, to create a plasma sheath around thesubstrate 12, and to implant the ions into thelayer 14 ofsilicon dioxide 16. A plasma density, useful for implanting an appropriate amount of hydrogen ions into thelayer 14, ranges from about 10.sup.6 ions/cm.sup.3 to about 10.sup.11 ions/cm.sup.3. - Another useful plasma source ion implantation apparatus and technique is described in U.S. Pat. No. 5,354,381 to Sheng which is also incorporated herein by reference in its entirety. The Sheng patent describes a technique in which a “cold” cathode is used to generate the hydrogen plasma. In this process, the
substrate 12 is mounted on a electrode, which is positioned in a wall of an implantation chamber. A pulsed negative voltage is applied to the electrode which creates electric field lines with the walls of the chamber. These electric field lines cause a hydrogen gas, which has been introduced into the chamber, to ionize and causes positive ions from the hydrogen gas to be accelerated toward thesubstrate 12 and to become implanted into thesubstrate 12. - After the hydrogen ions have been implanted into the
layer 14 ofsilicon dioxide 16, thelayer 18 ofpolycrystalline silicon 20 is formed on thelayer 14. Thelayer 18 ofpolycrystalline silicon 20 is formed on thelayer 14 by any deposition method currently in use in the art. Useful deposition methods include, but are not limited to, CVD, LPCVD, PECVD, MOCVD and sputtering. - By implanting hydrogen ions into the
layer 14 ofsilicon dioxide 16 by plasma source ion implantation, the resultinglayer 18 ofpolycrystalline silicon 20 is provided with a smooth morphology. By “smooth”, it is meant that, when thelayer 18 is measured by atomic force microscopy, thelayer 18 ofpolycrystalline silicon 20 has a root mean square (rms) deviation of from about 5 nm to about 12 nm. The method of the present invention provides alayer 18 ofpolycrystalline silicon 20 which is smoother than either a layer of polycrystalline silicon deposited on a non-treated layer of silicon dioxide (rms=22 nm) or a layer of polycrystalline silicon deposited on a layer of silicon dioxide pretreated with an H.sub.2 gas bake (rms=33 nm). While not wishing to be bound by a particular theory, it is believed that the implantation of the hydrogen ions in the silicon dioxide substrate increases the number of nucleation sites for polycrystalline silicon deposition thus affecting the morphology of the subsequently deposited layer of polycrystalline silicon. - Unlike a Kaufman ion source implantation technique, a plasma source ion implantation apparatus does not employ a metal grid to accelerate the hydrogen ions toward the target object but instead uses the target object itself, in this case the
substrate 12, to accelerate the ions toward the target object. Thus, plasma source ion implantation reduces the possibility of contamination of the target object by eliminating a device which employs a metal grid. Further, plasma source ion implantation can be used on smaller devices or substrates than a Kaufman ion source without increasing the likelihood for contamination of the target object. - The
semiconductor device precursor 10 of the present invention can be used to form any semiconductor device which requires that a layer of polycrystalline silicon be formed over a layer of silicon dioxide. Exemplary semiconductor devices which can be formed from thesemiconductor precursor 10 include, but are not limited to, field effect transistors, thin film transistors, dynamic random access memory devices (DRAMs), static random access memory devices (SRAMs), memory arrays and semiconductor wafers. -
FIG. 2 presents a cross sectional view of afield effect transistor 50 formed by the method of the present invention. Thefield effect transistor 50 is formed on asemiconductor substrate 52. Thefield effect transistor 50 includes agate oxide 54, asource 56 and adrain 58. Thegate oxide 54, thesource 56 and thedrain 58 are formed on thesubstrate 52. Alayer 64 ofpolysilicon 66 is formed on thegate oxide 54 to form agate electrode 70. A pair ofspacers 68 are formed on the sides of thelayer 64 ofpolysilicon 66. Alayer 72 of afield oxide 74 is also formed on thesubstrate 52. - The
substrate 52 can be formed of any material currently in use in the art to form substrates for semiconductors and integrated circuits. Desirably, thesubstrate 52 is formed from silicon which can be oxidized to form thelayer 72 offield oxide material 74. Otheruseful substrates 52 include, but are not limited to, gallium arsenide, indium phosphide, polycrystalline silicon, germanium, silicon dioxide, glass and quartz. As used herein, the term “substrate” is not limited to bulk substrate materials but can also denote thinner substrates such as those used to form thin film transistors. One skilled in the art will appreciate thatsubstrate 52 can be layer or part of a larger semiconductor device. - A method for making the
field effect transistor 50 is shown inFIGS. 2A-2C . As an initial step, thelayer 72 of thefield oxide 74 is formed on thesubstrate 52 by means of a conventional local oxidation of silicon (LOCOS) process. Next, agate oxide 54 is formed onsubstrate 52. The surface of thesubstrate 52 is then conditioned or pretreated so that the subsequently formedlayer 64 ofpolycrystalline silicon 66 has a smooth morphology. The surface of thesubstrate 52 is pretreated by implanting hydrogen ions into the surface of thesubstrate 52 through plasma source ion implantation by the method described above.FIG. 2A shows alayer 64 ofpolysilicon 66 having been formed on the surface of thesubstrate 52. Thelayer 64 ofpolysilicon 66 covers and, as shown inFIG. 2A , is in contact with thegate oxide 54. - As shown in
FIG. 2B , after thelayer 64 ofpolycrystalline silicon 66 has been formed on the surface of thesubstrate 52, thelayer 64 is etched to form thegate electrode 70. Thegate electrode 70 is formed by any conventional masking and etching techniques currently in use in the art. - As shown in
FIG. 2C , thesource 56 and thedrain 58 are formed by any conventional conductive doping technique currently in use in the art. Desirably, thesource 56 and thedrain 58 are formed by a self aligned technique. After thesource 56 and thedrain 58 have been formed, alayer 80 of adielectric material 68 is formed on thegate 54 and over thesource 56 anddrain 58. Typically, but not necessarily, thelayer 80 will be a layer of an oxidized material and is provided at a thickness such that it serves as an insulating layer. Any material used in the art to form spacers would be useful for forming thelayer 80 ofdielectric material 68. Desirably, thedielectric material 68 is silicon dioxide or silicon nitride. The resultingfield effect transistor 50 is shown inFIG. 2 . - The
field effect transistor 50 may also be used in a typical memory array, such as, for example, a static random access memory (SRAM) array or a dynamic random access memory (DRAM)array 100, which is shown inFIG. 3 . TheDRAM array 100 comprises a plurality ofmemory cells 102 arranged in rows and columns. As shown inFIG. 3A , each of thememory cells 102 includes at least onefield effect transistor 50 and onecapacitor 104. Thefield effect transistor 50 may be thefield effect transistor 50, described above and shown inFIG. 2 . The method for forming thefield effect transistor 50 is described above in connection with the description ofFIGS. 2A to 2C . Eachfield effect transistor 50 is coupled to acapacitor 104. The gate of thefield effect transistor 50 is coupled to aword line 106 via an interconnect structure. It should be apparent that other devices such as other transistors, bipolar transistors, resistors, other capacitors and the like, may be interconnected with thefield effect transistor 50. - The
field effect transistor 50 of the present invention may also used in the fabrication of a wafer W, as is shown inFIG. 4 . The wafer W includes a plurality ofindividual die 150 formed on a semiconductor substrate, such assubstrate 52. Wafer masks (not shown) are used to apply a desired circuit structure on each of theindividual die 150. The desired circuit structure may comprise any of the above described structures, e.g., theDRAM array 100 or an SRAM array. The wafer W is processed using standard wafer fabrication techniques. - The
semiconductor device precursor 10 and the method of the present invention are particularly useful in forming thin film transistors and, particularly, thin film transistors which are used to make flat panel displays. By providing the layer of polycrystalline silicon with a smoother morphology, a thinner layer of polycrystalline silicon is formed on the substrate. The final structure of the thin film transistor would be thinner due to the thinner polycrystalline silicon layer and to the layers which are subsequently deposited on the polycrystalline silicon also being thinner. - A
thin film transistor 200 is shown in cross section inFIG. 5 . Thethin film transistor 200 includes an insulatingsubstrate 202. Alayer 204 of asemiconducting material 206 is formed on the surface of thesubstrate 202. Asource region 208 and adrain region 210 are formed on thelayer 204 ofsemiconducting material 206. Alayer 212 of adielectric material 214 is formed on thelayer 204 ofsemiconducting material 206 and covers thesource 208 and thedrain 210. Alayer 216 of a conductingmaterial 218 is formed on thelayer 212 ofdielectric material 214 to form agate electrode 220. - The insulating
substrate 202 can be any material used to form insulating layers in semiconductor devices and is preferably glass, quartz or silicon dioxide. Rather than doping a layer of silicon dioxide which is subsequently deposited on a substrate as when forming a field effect transistor and as described above, when thethin film transistor 200 is being formed, the insulatingsubstrate 202, itself, is doped with hydrogen ions by the plasma source ion implantation technique described above. - After the insulating
substrate 202 has been doped with hydrogen ions, thelayer 204 ofsemiconducting material 206 is formed on thesubstrate 202 by any conventional deposition process. Useful deposition methods include, but are not limited to, CVD, LPCVD, PECVD, MOCVD and sputtering. Thelayer 204 ofsemiconducting material 206 can be any material used to form semiconducting layers, including, but are not limited to, gallium arsenide, indium phosphide, polycrystalline silicon, and germanium. Desirably, thelayer 204 ofsemiconducting material 206 is formed from polycrystalline silicon. Once thelayer 204 ofsemiconducting material 206 has been formed, thelayer 204 is etched to isolate the various regions of semiconducting material from each other on the surface of thesubstrate 202. - After the various regions of
semiconducting material 204 have been formed on thesubstrate 202, thesource region 208 and thedrain region 210 are formed on thelayer 204 ofsemiconducting material 206. Thesource region 208 and thedrain region 210 can either be formed in thelayer 204 ofsemiconducting material 206 or formed in thelayer 212 ofdielectric material 214. Thesource region 208 and thedrain region 210 are formed by any doping technique currently in use in the art. Thelayer 212 ofdielectric material 214 is deposited on thelayer 204 ofsemiconducting material 206. Useful deposition methods include, but are not limited to, thermal oxidation, CVD, LPCVD, PECVD, MOCVD and sputtering. Thelayer 212 ofdielectric material 214 can be any material used in the semiconductor manufacturing art to form dielectric layers. Desirably, thedielectric material 214 is silicon dioxide or silicon nitride. - As a final step, a
layer 216 of a conductingmaterial 218 is formed on thelayer 212 ofdielectric material 214. Thelayer 216 is formed in any manner currently used in the art to form such layers. Useful deposition methods include, but are not limited to, CVD, LPCVD, PECVD, MOCVD and sputtering. The conductingmaterial 218 is selected from the group consisting of polycrystalline silicon, metal and any conducting material. Thelayer 216 of conductingmaterial 218 forms thegate electrode 220. - One skilled in the art will appreciate that the method of the present invention can be carried out as a stand-alone process, clustered as part of the semiconductor manufacturing process or as an in situ pretreatment.
- Having described the invention in detail and by reference to preferred embodiments thereof, it will be apparent that modifications and variations are possible without departing from the scope of the invention which is defined in the appended claims.
Claims (11)
1-14. (canceled)
15. A semiconductor device precursor comprising:
a semiconductor substrate;
silicon dioxide formed on said semiconductor substrate, the surface of said silicon dioxide having been doped with hydrogen ions deposited by a plasma source ion implantation process, wherein said silicon dioxide has reduced sputtered metal contaminants in comparison with silicon dioxide doped with ions deposited by a Kauffman ion implantation process; and
polycrystalline silicon formed on said silicon dioxide, said polycrystalline silicon having a smooth morphology.
16. The semiconductor device precursor of claim 15 wherein the semiconductor substrate comprises at least one of gallium arsenide, indium phosphide, polycrystalline silicon, silicon dioxide, glass, and quartz.
17. A field effect transistor comprising:
a semiconductor substrate;
silicon dioxide formed on at least a portion of said semiconductor substrate, the surface of said silicon dioxide having hydrogen ions implanted therein by plasma source ion implantation, wherein said silicon dioxide has reduced sputtered metal contaminants in comparison with silicon dioxide doped with ions deposited by a Kauffman ion implantation process;
polycrystalline silicon formed on at least a portion of said silicon dioxide, said polycrystalline silicon having a smooth morphology;
a gate oxide formed on said semiconductor substrate from said silicon dioxide having hydrogen ions implanted therein by plasma source ion implantation; and
a source and a drain formed in said semiconductor substrate with a gate electrode formed on said semiconductor substrate from said polycrystalline silicon to form a field effect transistor.
18. The transistor of claim 17 wherein the semiconductor substrate comprises at least one of gallium arsenide, indium phosphide, polycrystalline silicon, silicon dioxide, glass, and quartz.
19. A memory array comprising:
a semiconductor substrate;
silicon dioxide formed on at least a portion of said semiconductor substrate, wherein hydrogen ions are implanted into at least a portion of the surface of said silicon dioxide by plasma source ion implantation, wherein said silicon dioxide has reduced sputtered metal contaminants in comparison with a silicon dioxide doped with ions deposited by a Kauffman ion implantation process;
polycrystalline silicon formed over at least said portion of said silicon dioxide into which said hydrogen ions were implanted, said polycrystalline silicon having a smooth morphology;
a plurality of memory cells arranged in rows and columns, each of said plurality of memory cells comprising at least one field effect transistor;
a gate oxide for each of said field effect transistors formed on said semiconductor substrate from said silicon dioxide having hydrogen ions implanted therein by plasma source ion implantation;
a source and a drain for each of said field effect transistors formed in said semiconductor substrate; and
a gate electrode for each of said field effect transistors formed on said semiconductor substrate from said polycrystalline silicon.
20. The memory array of claim 19 wherein the semiconductor substrate comprises at least one of gallium arsenide, indium phosphide, polycrystalline silicon, silicon dioxide, glass, and quartz.
21. The memory array of claim 19 comprising DRAM.
22. The memory array of claim 19 comprising SRAM.
23. A semiconductor wafer comprising:
a wafer including a semiconductor substrate, said wafer being divided into a plurality of die;
silicon dioxide formed on at least a portion of said semiconductor substrate, on each of said plurality of die hydrogen ions are implanted into at least a portion of the surface of said silicon dioxide by plasma source ion implantation, wherein said silicon dioxide has reduced sputtered metal contaminants in comparison with a silicon dioxide doped with ions deposited by a Kauffman ion implantation process;
polycrystalline silicon formed over at least said portion of said silicon dioxide into which said hydrogen ions were implanted, said polycrystalline silicon having a smooth morphology;
a repeating series of gate oxides formed on said semiconductor substrate from said silicon dioxide having hydrogen ions implanted therein by plasma source ion implantation;
a repeating series of sources and drains for at least one field effect transistor formed on each of said plurality of die, said series of sources and drains being formed on said semiconductor substrate; and
a repeating series of gate electrodes for at least one field effect transistor formed on each of said plurality of die, said series of gate electrodes being formed on said semiconductor substrate from said polycrystalline silicon.
24. A thin film transistor comprising:
a semiconductor substrate formed from a material selected from the group consisting of silicon dioxide, quartz and glass, the surface of said semiconductor substrate having hydrogen ions implanted therein by plasma source ion implantation, wherein said semiconductor substrate has reduced sputtered metal contaminants in comparison with a semiconductor substrate doped with ions deposited by a Kauffman ion implantation process;
polycrystalline silicon formed on at least a portion of said semiconductor substrate, said polycrystalline silicon having a smooth morphology;
insulating material formed on at least a portion of said polycrystalline silicon;
a gate oxide formed from said insulating material;
a source region and a drain region formed in said polycrystalline silicon; and
a gate electrode formed on said insulating material.
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Also Published As
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US8288832B1 (en) | 2012-10-16 |
US6143631A (en) | 2000-11-07 |
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