JPH11352184A - Ic testing device - Google Patents

Ic testing device

Info

Publication number
JPH11352184A
JPH11352184A JP10157377A JP15737798A JPH11352184A JP H11352184 A JPH11352184 A JP H11352184A JP 10157377 A JP10157377 A JP 10157377A JP 15737798 A JP15737798 A JP 15737798A JP H11352184 A JPH11352184 A JP H11352184A
Authority
JP
Japan
Prior art keywords
test
socket
lift plate
latch
supported
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10157377A
Other languages
Japanese (ja)
Other versions
JP3895041B2 (en
Inventor
Noboru Saito
登 齊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to JP15737798A priority Critical patent/JP3895041B2/en
Publication of JPH11352184A publication Critical patent/JPH11352184A/en
Application granted granted Critical
Publication of JP3895041B2 publication Critical patent/JP3895041B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce a required strength of a constitutional member and to realize a small size of the structural member by forming a structure in which a reaction to the pressure of an IC to an IC socket is not transmitted to a surrounding structural member in an IC testing device for simultaneously testing many IC. SOLUTION: A cylinder 130 and a latch means 140 are provided on every pushers giving a pressure contact force to a pin of an IC. A space between the pusher and an IC socket 21 is latched by the latch means 140. An elongation force of the cylinder 130 is absorbed by the latch means 140 by actuating the cylinder 130 in the latched state and a reaction force urging the IC is not transmitted to the outside.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は被試験ICをテス
トトレイに搭載し、テストトレイに搭載した状態のまま
被試験ICをテストヘッドに設けたICソケットに接触
させ、試験を行なう型式のIC試験装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a type of IC test in which an IC under test is mounted on a test tray, and the IC under test is brought into contact with an IC socket provided on a test head while being mounted on the test tray to perform a test. Related to the device.

【0002】[0002]

【従来の技術】図3乃至図5を用いてテストトレイを用
いたIC試験装置の概要を説明する。図3はそのIC試
験装置を略線化して示した平面図を示す。図中100は
テストヘッドを含むチャンバ部、200はこれから試験
を行なう被試験ICを格納し、また試験済のICを分類
して格納するIC格納部、300は被試験ICをチャン
バ部100に送り込むローダ部、400はチャンバ部1
00で試験が行われた試験済のICを分類して取り出す
アンローダ部、TSTはローダ部300で被試験ICが
積み込まれてチャンバ部100に送り込まれ、チャンバ
部100でICを試験し、試験済のICをアンローダ部
400に運び出すIC搬送用のトレイを示す。以下これ
をテストトレイTSTと称することにするチャンバ部1
00はテストトレイTSTに積み込まれた被試験ICに
目的とする高温または低温の熱ストレスを与える恒温槽
101と、この恒温槽101で熱ストレスが与えられた
状態にあるICをテストヘッドに接触させるテストチャ
ンバ102と、テストチャンバ102で試験されたIC
から、与えられた熱ストレスを除去する除熱槽103と
によって構成される。つまり、恒温槽101で高温を印
加した場合は送風により冷却し、室温に戻してアンロー
ダ部400に搬出する。また恒温槽101で例えば−3
0℃程度の低温を印加した場合は温風乃至はヒータ等で
槽内を加熱し、結露が生じない程度の温度に戻してアン
ローダ部400に搬出する。
2. Description of the Related Art An outline of an IC test apparatus using a test tray will be described with reference to FIGS. FIG. 3 is a plan view schematically showing the IC test apparatus. In the figure, reference numeral 100 denotes a chamber section including a test head, 200 denotes an IC storage section for storing ICs to be tested and ICs to be tested and classified, and 300 denotes an IC to be tested to be sent to the chamber section 100. Loader section, 400 is chamber section 1
The unloader unit that sorts and removes the tested ICs that have been tested at 00, and the TST is loaded with the IC under test by the loader unit 300 and sent to the chamber unit 100. The IC is tested by the chamber unit 100 and is tested. 5 shows an IC transfer tray for transferring the IC to the unloader unit 400. Hereinafter, this will be referred to as a test tray TST.
Reference numeral 00 denotes a constant temperature chamber 101 for applying a desired high or low temperature thermal stress to the IC under test loaded on the test tray TST, and an IC in which a thermal stress is applied in the constant temperature chamber 101 to the test head. Test chamber 102 and ICs tested in test chamber 102
And a heat removal tank 103 for removing the applied thermal stress. That is, when a high temperature is applied in the constant temperature bath 101, it is cooled by blowing air, returned to room temperature, and carried out to the unloader unit 400. In the thermostat 101, for example, -3
When a low temperature of about 0 ° C. is applied, the inside of the tank is heated by warm air or a heater to return the temperature to a level at which dew condensation does not occur, and then carried out to the unloader unit 400.

【0003】恒温槽101及び除熱槽103はテストチ
ャンバ102より上方に突出されて配置される。恒温槽
101と除熱槽103の上部間に図4に示すように基板
105が差し渡され、この基板105にテストトレイ搬
送手段108が装着され、このテストトレイ搬送手段1
08によってテストトレイTSTが、除熱槽103側か
ら恒温槽101に向かって移送される。テストトレイT
STはローダ部300で被試験ICを積み込み、恒温槽
101に運び込まれる。恒温槽101には垂直搬送手段
が装着されており、この垂直搬送手段によって複数枚の
テストトレイTSTが支持されてテストチャンバ102
が空くまで待機する。この待機中に被試験ICに高温ま
たは低温の熱ストレスを印加する。テストチャンバ10
2にはその中央にテストヘッド104が配置され、テス
トヘッド104の上にテストトレイTSTが運ばれて被
試験ICをテストヘッド104に設けたICソケットに
電気的に接触させ試験を行なう。試験が終了したテスト
トレイTSTは除熱槽103で除熱し、ICの温度を室
温に戻し、アンローダ部400に排出する。
A constant temperature bath 101 and a heat removal bath 103 are arranged to protrude above the test chamber 102. As shown in FIG. 4, a substrate 105 is inserted between the constant temperature bath 101 and the heat removal bath 103, and a test tray transport unit 108 is mounted on the substrate 105.
In step 08, the test tray TST is transferred from the heat removal tank 103 to the thermostatic chamber 101. Test tray T
In the ST, the IC under test is loaded by the loader unit 300 and is carried into the thermostat 101. The constant temperature bath 101 is provided with a vertical transport unit, and the vertical transport unit supports a plurality of test trays TST to form a test chamber 102.
Wait until is available. During this standby, a high or low temperature thermal stress is applied to the IC under test. Test chamber 10
A test head 104 is disposed at the center of the test head 2, and a test tray TST is carried on the test head 104 so that an IC to be tested is brought into electrical contact with an IC socket provided on the test head 104 to perform a test. After the test, the test tray TST is heat-removed in the heat-removal tank 103, the temperature of the IC is returned to room temperature, and the IC is discharged to the unloader unit 400.

【0004】IC格納部200には被試験ICを格納す
る被試験ICストッカ201と、試験の結果に応じて分
類されたICを格納する試験済ICストッカ202とが
設けられる。被試験ICストッカ201には被試験IC
を格納した汎用トレイKSTが積層されて保持される。
この汎用トレイKSTがローダ部300に運ばれ、ロー
ダ部300に運ばれた汎用トレイKSTからローダ部3
00に停止しているテストトレイTSTに被試験ICを
積み替える。汎用トレイKSTからテストトレイTST
にICを運び込むIC搬送手段としては図4に示すよう
に、基板105の上部に架設した2本のレール301
と、この2本のレール301によってテストトレイTS
Tと汎用トレイKSTとの間を往復(この方向をY方向
とする)することができる可動アーム302と、この可
動アーム302によって支持され、可動アーム302に
沿ってX方向に移動できる可動ヘッド303とによって
構成されるX−Y搬送手段304を用いることができ
る。可動ヘッド303には下向きに吸着ヘッドが装着さ
れ、この吸着ヘッドが空気を吸引しながら移動し、汎用
トレイKSTからICを吸着し、そのICをテストトレ
イTSTに搬送する。吸着ヘッドは可動ヘッド303に
対して例えば8本程度装着され、一度に8個のICをテ
ストトレイTSTに搬送する。
[0004] The IC storage section 200 is provided with an IC tester stocker 201 for storing ICs to be tested and a tested IC stocker 202 for storing ICs classified according to the test results. The IC under test 201
Are stacked and held.
The general-purpose tray KST is carried to the loader unit 300, and the general-purpose tray KST carried to the loader unit 300 is moved from the general-purpose tray KST to the loader unit 3.
The IC under test is transferred to the test tray TST stopped at 00. General-purpose tray KST to test tray TST
As shown in FIG. 4, two rails 301 provided on the upper portion of the substrate 105 are used as IC transport means for transporting the IC to the substrate.
And the test tray TS by these two rails 301
A movable arm 302 capable of reciprocating between the T and the general-purpose tray KST (this direction is defined as a Y direction); and a movable head 303 supported by the movable arm 302 and capable of moving in the X direction along the movable arm 302. XY transport means 304 constituted by A suction head is attached to the movable head 303 downward, and the suction head moves while sucking air, sucks an IC from the general-purpose tray KST, and transports the IC to the test tray TST. For example, about eight suction heads are mounted on the movable head 303, and convey eight ICs to the test tray TST at a time.

【0005】図5にテストトレイTSTの構造を示す。
テストトレイTSTは方形の金属フレーム12に複数の
仕切フレーム13が平行かつ等間隔に形成され、これ等
仕切フレーム13の両側、或いは仕切フレーム13と対
向するフレーム12の辺12aにそれぞれ複数の取付け
片14が等間隔に突出形成され、これ等仕切フレーム1
3間、または仕切フレーム13及び辺12a間と、2つ
の取付け片14とによりキャリア収納部15が配列構成
されている。各キャリア収納部15にそれぞれ1個のI
Cキャリア16が収納され、2つの取付け片14にファ
スナ17によりフローティング状態で取付けられる。I
Cキャリア16は1つのテストトレイTSTに16×4
個程度取付けられる。
FIG. 5 shows the structure of the test tray TST.
In the test tray TST, a plurality of partition frames 13 are formed on a rectangular metal frame 12 in parallel and at equal intervals, and a plurality of mounting pieces are respectively provided on both sides of the partition frame 13 or on sides 12a of the frame 12 facing the partition frame 13. 14 are formed so as to protrude at equal intervals.
The carrier accommodating portions 15 are arranged and arranged between the three or between the partition frame 13 and the side 12a and the two mounting pieces 14. Each carrier storage unit 15 has one I
The C carrier 16 is housed, and is mounted on the two mounting pieces 14 in a floating state by the fastener 17. I
C carrier 16 is 16 × 4 on one test tray TST
It can be mounted in pieces.

【0006】ICキャリア16は図6に示すようにIC
のピン18を下面側に露出して保持する。テストヘッド
104ではこの露出したICのピン18をプッシャ19
によってICソケット21のソケットコンタクト21A
に押し付け、ICをICソケット21に電気的に接触さ
せている。このためにテストヘッド104の上部には上
下に移動できる昇降手段120を配置すると共に、下部
には上下に移動できる支持フレーム110が設けられ
る。この支持フレーム110にテストトレイTSTを位
置決めして支持させ、テストトレイTSTとICを上部
から抑え付け、ソケットコンタクト21AにICのピン
18を接触させている。
[0006] As shown in FIG.
Pin 18 is exposed and held on the lower surface side. In the test head 104, the pins 18 of the exposed IC are
Socket contact 21A of IC socket 21
To bring the IC into electrical contact with the IC socket 21. To this end, an elevating means 120 that can move up and down is arranged above the test head 104, and a support frame 110 that can move up and down is provided below. The test tray TST is positioned and supported by the support frame 110, the test tray TST and the IC are pressed down from above, and the pins 18 of the IC are brought into contact with the socket contacts 21A.

【0007】支持フレーム110は例えば下基板111
に植設した垂直シャフト112に貫通して上下方向に移
動自在に支持され、バネ113によって上方に偏倚力が
与えられ、垂直シャフト112の上端に設けたフランジ
114によって抜け止めされ、非押下状態では支持フレ
ーム110はフランジ114の高さの位置に支持され
る。この状態で上方から昇降手段120によりテストト
レイTSTとICに押圧力を与えることにより、支持フ
レーム110はテストトレイTSTと共に下向きに移動
し、ICのピン18をソケットコンタクト21Aに接触
させる。
The support frame 110 is, for example, a lower substrate 111
Is vertically movably supported through a vertical shaft 112 implanted in the vertical shaft 112. A biasing force is applied upward by a spring 113, and the vertical shaft 112 is prevented from falling off by a flange 114 provided at an upper end of the vertical shaft 112. The support frame 110 is supported at the height of the flange 114. In this state, by applying a pressing force to the test tray TST and the IC from above by the elevating means 120, the support frame 110 moves downward together with the test tray TST, and brings the pins 18 of the IC into contact with the socket contacts 21A.

【0008】昇降手段120は上基板121に装着され
たパワーシリンダ122と、このパワーシリンダ122
の可動ロッド122Aに装着された可動板123と、上
基板121を推動自在に貫通し、昇降板125に連結し
た推動ロッド124とによって構成される。126は上
基板121と下基板111との間を一体化する支柱を示
す。
The elevating means 120 includes a power cylinder 122 mounted on the upper substrate 121 and the power cylinder 122
And a thrust rod 124 penetrating the upper substrate 121 so as to be freely slidable and connected to an elevating plate 125. Reference numeral 126 denotes a support that integrates the upper substrate 121 and the lower substrate 111.

【0009】[0009]

【発明が解決しようとする課題】従来は昇降手段120
によってテストトレイTSTとこれに搭載されているI
Cに下向の圧接力を与えているから、昇降手段120は
比較的大きい押圧力を発生する必要がある。特にテスト
トレイTSTに搭載されている複数のICに対して同時
に圧接力を与えるから大きな圧接力が必要となる。
Conventionally, the lifting / lowering means 120 is used.
Test tray TST and I mounted on it
Since a downward pressure contact force is applied to C, the lifting / lowering means 120 needs to generate a relatively large pressing force. In particular, a large pressing force is required because a pressing force is simultaneously applied to a plurality of ICs mounted on the test tray TST.

【0010】短時間に多量のICを試験するには同時に
試験するICの数は多くなり、16個乃至は32個程度
となり、今後この数は増える傾向にある。この結果昇降
手段120の圧接力が大きくなり、これに伴なって上基
板121、下基板111、支柱126の強度を大きく採
らなければならないから、装置全体が大形になること
と、重量も大きくなり、更に製造コストも高くなる欠点
がある。今後同時に試験するICの数は更に大きくなる
ことが予想されるため、この傾向は益々強くなり装置の
大形化は避けられない状況にある。
In order to test a large number of ICs in a short time, the number of ICs to be tested at the same time increases, and becomes about 16 or 32, and this number tends to increase in the future. As a result, the pressing force of the lifting / lowering means 120 increases, and accordingly, the strength of the upper substrate 121, the lower substrate 111, and the support columns 126 must be increased. Therefore, the entire apparatus becomes large and the weight increases. In addition, there is a disadvantage that the manufacturing cost is increased. Since it is expected that the number of ICs to be tested simultaneously will be further increased in the future, this tendency will become stronger and the size of the device will be unavoidable.

【0011】[0011]

【課題を解決するための手段】この発明では同時に試験
されるICに対して別々に押圧力を与えるシリンダを設
け、このシリンダによってICに別々に押圧力を与える
と共に、この押圧力に対する反力を各IC毎に設けたラ
ッチ手段によって吸収させる構成とするものである。
According to the present invention, there is provided a cylinder for separately applying a pressing force to the ICs to be tested at the same time. The cylinder applies the pressing force to the ICs separately, and the reaction force against the pressing force is reduced. This is configured to be absorbed by latch means provided for each IC.

【0012】この発明の構成によれば試験される各IC
には各IC毎に設けたシリンダから押圧力が与えられ、
更にその押圧力によって発生する反力は各IC毎に設け
たラッチ手段によって吸収する。従って昇降手段120
は昇降板を昇降させるだけの作業を行なえばよく、大き
な圧接力を発生させる必要はない。この結果、昇降手段
を支持する上基板及び下基板、支柱等の強度を大きく採
る必要がなくなり、装置の小形化及び低コスト化が可能
となる。
According to the configuration of the present invention, each IC to be tested
Is given a pressing force from a cylinder provided for each IC.
Further, the reaction force generated by the pressing force is absorbed by the latch means provided for each IC. Therefore, the lifting means 120
It is only necessary to perform the work of raising and lowering the lifting plate, and it is not necessary to generate a large pressing force. As a result, it is not necessary to increase the strength of the upper substrate, the lower substrate, the columns, and the like that support the lifting / lowering means, and the apparatus can be reduced in size and cost.

【0013】[0013]

【発明の実施の形態】図1にこの発明によるIC試験装
置の実施例を示す。この発明ではテストトレイTSTに
搭載され、テストトレイに搭載された状態のままにある
ICをテストヘッドのICソケットに圧接させ、ICの
試験を行なう構造のIC試験装置において、IC及びテ
ストトレイTSTに下向の圧接力を与える昇降手段12
0に試験を行なう各IC毎に押圧用シリンダ130と、
この押圧用シリンダ130とICソケット21の何れか
一方にラッチ手段140とを設けた点を特徴とするもの
である。
FIG. 1 shows an embodiment of an IC test apparatus according to the present invention. In the present invention, an IC mounted on a test tray TST and held in a state of being mounted on the test tray is pressed against an IC socket of a test head to test the IC. Elevating means 12 for applying downward pressure contact force
A pressing cylinder 130 for each IC to be tested to zero;
It is characterized in that a latch means 140 is provided on one of the pressing cylinder 130 and the IC socket 21.

【0014】図1に示す例ではラッチ手段140を一対
のラッチレバー141,141と、このラッチレバー1
41,141にその回動遊端を互に近接する方向に偏倚
力を与えるバネ142と、ラッチレバー141の回動遊
端に形成した爪143とによって構成した場合を示す。
このラッチ手段140によれば昇降板125を降下させ
ると、一対のラッチレバー141がテストトレイTST
に搭載され試験しようとするICの両側に入り込み、爪
143がICソケット21に形成した突起部21Bに係
合する。この係合状態はバネ142の偏倚力によって維
持される。
In the example shown in FIG. 1, the latch means 140 is composed of a pair of latch levers 141 and 141 and this latch lever 1
A case is shown in which the springs 41 and 141 are provided with a spring 142 for applying a biasing force in the direction in which the free ends of rotation come close to each other, and a claw 143 formed at the free end of rotation of the latch lever 141.
According to the latch means 140, when the elevating plate 125 is lowered, the pair of latch levers 141 move the test tray TST.
Of the IC to be tested mounted on the IC socket 21, and the claw 143 engages with the protrusion 21 </ b> B formed on the IC socket 21. This engaged state is maintained by the biasing force of the spring 142.

【0015】この状態で押圧用シリンダ130を伸張さ
せることにより、シリンダ130はプッシャ19を押下
し、ICのピン18をソケットコンタクト21Aに圧接
させる。このときシリンダ130に与えられる反力はラ
ッチ手段140で吸収するから、複数のICのピン18
から反力が発生しても上基板121と下基板111にそ
の反力が伝わることはない。
In this state, when the pressing cylinder 130 is extended, the cylinder 130 presses the pusher 19 to press the pin 18 of the IC against the socket contact 21A. At this time, since the reaction force applied to the cylinder 130 is absorbed by the latch means 140, a plurality of pins 18
Even when a reaction force is generated, the reaction force is not transmitted to the upper substrate 121 and the lower substrate 111.

【0016】従って昇降手段120は単に昇降板125
を昇降させるだけの駆動力を持てばよく、また上基板1
21と下基板111及び支柱126は多数のICから発
生する反力に耐える強度を持つ必要はなく、昇降手段1
20の重量を支持する強度を持てば充分である。図1の
実施例において、150はラッチ手段140のラッチ状
態を解除する解除手段を示す。この解除手段140は例
えばシリンダ151と、アクチュエータ152とによっ
て構成することができ、アクチュエータ152をラッチ
レバー141の回動遊端に係合させ、爪143を突起2
1Bとの係合状態から外すことによりラッチ手段140
のラッチ状態を解除する。従ってICの試験終了時点で
ラッチ手段140のラッチ状態を解除することにより、
昇降手段120を上昇させ、この状態でテストトレイT
STを例えば1ピッチ分移動させることにより他のIC
を試験する。
Therefore, the lifting means 120 is simply a lifting plate 125
It is only necessary to have a driving force enough to raise and lower the upper substrate 1
21, the lower substrate 111, and the columns 126 do not need to have the strength to withstand the reaction force generated from a large number of ICs.
It is sufficient to have the strength to support the weight of 20. In the embodiment of FIG. 1, reference numeral 150 denotes a releasing means for releasing the latch state of the latch means 140. The release means 140 can be constituted by, for example, a cylinder 151 and an actuator 152. The actuator 152 is engaged with the free rotation end of the latch lever 141, and the pawl 143 is
1B, the latch means 140 is released.
Release the latched state of. Therefore, by releasing the latch state of the latch means 140 at the end of the IC test,
The elevating means 120 is raised, and the test tray T
By moving ST one pitch, for example, another IC
To test.

【0017】図2はこの発明の他の実施例を示す。この
実施例ではラッチレバー141をICソケット21側に
軸支させ、その回動遊端部に形成した爪143を昇降板
125側に設けた段部127に係合させる構造とした場
合を示す。この構造によっても図1に示した実施例と同
様の作用効果を奏することができることは容易に理解で
きよう。
FIG. 2 shows another embodiment of the present invention. In this embodiment, a case is shown in which the latch lever 141 is pivotally supported on the IC socket 21 side, and the pawl 143 formed on the free play end of the latch lever 141 is engaged with the step 127 provided on the lift plate 125 side. It can be easily understood that this structure can provide the same operation and effect as the embodiment shown in FIG.

【0018】[0018]

【発明の効果】以上説明したように、この発明によれば
ICソケット21に圧接させ各IC毎にラッチ手段14
0と、押圧用シリンダ130を設け、ラッチ手段140
によって各ICのピン18をICソケット21のソケッ
トコンタクト21Aに圧接させるときに発生する反力を
吸収させる構造としたから、上基板121と、下基板1
11と、支柱126の強度は昇降手段120の重量を支
える強度だけで済む。
As described above, according to the present invention, the latch means 14 is brought into pressure contact with the IC socket 21 for each IC.
0, and a pressing cylinder 130,
Thus, the reaction force generated when the pin 18 of each IC is pressed against the socket contact 21A of the IC socket 21 is absorbed, so that the upper substrate 121 and the lower substrate 1
11 and the strength of the support 126 need only be the strength supporting the weight of the lifting / lowering means 120.

【0019】この結果、上基板121と、下基板111
と、支柱126の厚み及び直径等を小さくすることがで
きるから、装置を小形化することができ、また全体の重
量を軽減することができる。また材料も安価にすること
ができるから、コストダウンが期待できる。
As a result, the upper substrate 121 and the lower substrate 111
Since the thickness and diameter of the support 126 can be reduced, the size of the apparatus can be reduced, and the overall weight can be reduced. In addition, since the material can be made inexpensive, cost reduction can be expected.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の一実施例を説明するための断面図。FIG. 1 is a sectional view for explaining an embodiment of the present invention.

【図2】この発明の他の実施例を説明するための断面
図。
FIG. 2 is a sectional view for explaining another embodiment of the present invention.

【図3】従来の技術を説明するための略線的平面図。FIG. 3 is a schematic plan view for explaining a conventional technique.

【図4】従来の技術を説明するための斜視図。FIG. 4 is a perspective view for explaining a conventional technique.

【図5】従来の技術を説明するためのテストトレイを示
す分解斜視図。
FIG. 5 is an exploded perspective view showing a test tray for explaining a conventional technique.

【図6】この発明の解決すべき課題を説明するための断
面図。
FIG. 6 is a sectional view for explaining a problem to be solved by the present invention.

【符号の説明】[Explanation of symbols]

18 ピン 19 プッシャ 21 ICソケット 21A ソケットコンタクト 110 支持フレーム 111 下基板 120 昇降手段 121 上基板 122 パワーシリンダ 123 可動板 124 推動ロッド 125 昇降板 126 支柱 127 段部 130 シリンダ 140 ラッチ手段 141 ラッチレバー 142 バネ 143 爪 150 解除手段 18 pin 19 pusher 21 IC socket 21A socket contact 110 support frame 111 lower substrate 120 elevating means 121 upper substrate 122 power cylinder 123 movable plate 124 thrust rod 125 elevating plate 126 column 127 step 130 cylinder 140 latch means 141 latch lever 142 spring 143 Claw 150 release means

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 A.平面状に複数のICを搭載したテス
トトレイと、 B.このテストトレイに支持されたICの下部に配置さ
れるICソケットと、 C.上記テストトレイの上部において昇降自在に支持さ
れた昇降板と、 D.この昇降板に支持され上記昇降板が降下動作すると
き上記テストトレイに支持されたICと係合する複数の
プッシャと、 E.各プッシャと上記昇降板との間に装着され各プッシ
ャに下向の偏倚力を与える押圧用シリンダと、 F.上記昇降板と上記ICソケットの何れか一方に回動
自在に支持され、上記昇降板が降下動作時に他方と係合
して上記押圧用シリンダの伸張力を上記プッシャを介し
て上記ICに与え、上記押圧用シリンダに与えられる反
力を吸収するラッチ手段と、 G.このラッチ手段の係合状態を外す解除手段と、によ
って構成したことを特徴とするIC試験装置。
1. A. First Embodiment B. a test tray on which a plurality of ICs are mounted in a plane; B. an IC socket disposed below the IC supported by the test tray; An elevating plate supported on the upper portion of the test tray so as to be movable up and down; A. A plurality of pushers supported by the lift plate and engaging with the ICs supported by the test tray when the lift plate moves downward; B. a pressing cylinder mounted between each pusher and said elevating plate to apply a downward biasing force to each pusher; The lift plate and the IC socket are rotatably supported by one of the IC sockets, and the lift plate engages with the other during the lowering operation to apply the extension force of the pressing cylinder to the IC via the pusher, L. latch means for absorbing a reaction force applied to the pressing cylinder; An IC test apparatus comprising: a release unit for releasing an engagement state of the latch unit.
【請求項2】 請求項1記載のIC試験装置において、
上記ラッチ手段は上記昇降板側に回動自在に支持した一
対のラッチレバーによって構成し、上記昇降板が降下し
た状態で上記ラッチレバーの回動遊端に形成した爪を上
記ICソケットに係合させる構造としたことを特徴とす
るIC試験装置。
2. The IC test apparatus according to claim 1, wherein
The latch means is constituted by a pair of latch levers rotatably supported on the lift plate side, and a hook formed at a free play end of the latch lever is engaged with the IC socket when the lift plate is lowered. An IC test apparatus characterized by having a structure for causing the test.
【請求項3】 請求項1記載のIC試験装置において、
上記ラッチ手段を構成する上記ラッチレバーを上記IC
ソケット側に回動自在に支持し、上記昇降板が降下した
状態で上記ラッチレバーの回動遊端に形成した爪を上記
昇降板側に係合させる構造としたことを特徴とするIC
試験装置。
3. The IC test apparatus according to claim 1, wherein
The latch lever constituting the latch means is mounted on the IC
An IC having a structure rotatably supported on a socket side and a pawl formed at a free play end of the latch lever engaged with the lift plate side when the lift plate is lowered.
Testing equipment.
JP15737798A 1998-06-05 1998-06-05 IC test equipment Expired - Fee Related JP3895041B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15737798A JP3895041B2 (en) 1998-06-05 1998-06-05 IC test equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15737798A JP3895041B2 (en) 1998-06-05 1998-06-05 IC test equipment

Publications (2)

Publication Number Publication Date
JPH11352184A true JPH11352184A (en) 1999-12-24
JP3895041B2 JP3895041B2 (en) 2007-03-22

Family

ID=15648334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15737798A Expired - Fee Related JP3895041B2 (en) 1998-06-05 1998-06-05 IC test equipment

Country Status (1)

Country Link
JP (1) JP3895041B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180028148A (en) * 2016-09-08 2018-03-16 주식회사 윌테크 Jig pallet auto cleaner for electronic goods aging test equipment
KR102065972B1 (en) * 2018-11-01 2020-01-14 세메스 주식회사 Test handler
CN117406067A (en) * 2023-12-11 2024-01-16 上海捷策创电子科技有限公司 Pressure detection device and method for chip test seat

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180028148A (en) * 2016-09-08 2018-03-16 주식회사 윌테크 Jig pallet auto cleaner for electronic goods aging test equipment
KR102065972B1 (en) * 2018-11-01 2020-01-14 세메스 주식회사 Test handler
CN117406067A (en) * 2023-12-11 2024-01-16 上海捷策创电子科技有限公司 Pressure detection device and method for chip test seat
CN117406067B (en) * 2023-12-11 2024-02-13 上海捷策创电子科技有限公司 Pressure detection device and method for chip test seat

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Publication number Publication date
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