JPH11345742A - Manufacture of multilayer ceramic electronic device - Google Patents

Manufacture of multilayer ceramic electronic device

Info

Publication number
JPH11345742A
JPH11345742A JP15172798A JP15172798A JPH11345742A JP H11345742 A JPH11345742 A JP H11345742A JP 15172798 A JP15172798 A JP 15172798A JP 15172798 A JP15172798 A JP 15172798A JP H11345742 A JPH11345742 A JP H11345742A
Authority
JP
Japan
Prior art keywords
electronic component
ceramic electronic
laminate
multilayer ceramic
cutting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15172798A
Other languages
Japanese (ja)
Other versions
JP3428434B2 (en
Inventor
Giichi Takagi
義一 高木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP15172798A priority Critical patent/JP3428434B2/en
Publication of JPH11345742A publication Critical patent/JPH11345742A/en
Application granted granted Critical
Publication of JP3428434B2 publication Critical patent/JP3428434B2/en
Anticipated expiration legal-status Critical
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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing multilayer ceramic electronic device in which delamination between ceramic layers or stripping of inner electrode from ceramic layer is retarded in sintered ceramic. SOLUTION: A unfired mother laminate 6 having a plurality of inner electrodes 4, 5 laminated through a ceramic layer is prepared. When the mother laminate 6 is pressed in the laminating direction and cut into individual units of multilayer ceramic electronic device, it is cut such that the laminate is removed over a width at (1/3)X or more substantially in the center of adjacent electronic device parts, where X is the interval between the inner electrode 4 of a multilayer ceramic electronic device 7 and the inner electrode 4 of an adjacent multilayer ceramic electronic device 8. The resulting laminate is fired to obtained a sintered laminate and an outer electrode is formed on the outer surface thereof.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、例えば積層コンデ
ンサのような積層セラミック電子部品の製造方法に関
し、より詳細には、未焼成のマザーの積層体から個々の
電子部品単位の積層体を分割する工程が改良された積層
セラミック電子部品の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer ceramic electronic component such as a multilayer capacitor, and more particularly to a method for dividing a laminate of individual electronic components from an unfired mother laminate. The present invention relates to a method for manufacturing a multilayer ceramic electronic component with improved processes.

【0002】[0002]

【従来の技術】従来、積層セラミック電子部品を製造す
るに際しては、量産性を高めるために、未焼成のマザー
の積層体を得、該マザーの積層体を所定の方向に切断す
ることにより、個々の積層セラミック電子部品単位の積
層体を得ていた。
2. Description of the Related Art Conventionally, in manufacturing a multilayer ceramic electronic component, in order to enhance mass productivity, an unfired mother laminate is obtained, and the mother laminate is cut in a predetermined direction to obtain an individual product. Of the multilayer ceramic electronic component.

【0003】すなわち、まず、複数の内部電極がセラミ
ック層を介して積層されている積層セラミック電子部品
部分が所定の間隔を隔てて複数形成されている未焼成の
マザーの積層体を用意する。次に、このマザーの積層体
を積み重ね方向に加圧した後、個々の積層セラミック電
子部品単位の積層体に分割するためにマザーの積層体を
所定の方向に切断する。しかる後、切断により得られた
個々の積層セラミック電子部品単位の積層体を焼成し、
複数の内部電極がセラミック層を介して重なり合わされ
たセラミック焼結体を得ていた。
[0003] First, an unfired mother laminate is prepared in which a plurality of laminated ceramic electronic parts in which a plurality of internal electrodes are laminated via ceramic layers are formed at predetermined intervals. Next, after the mother laminate is pressed in the stacking direction, the mother laminate is cut in a predetermined direction in order to divide the laminate into individual laminated ceramic electronic component units. Thereafter, the laminate of each individual multilayer ceramic electronic component obtained by cutting is fired,
A ceramic sintered body in which a plurality of internal electrodes are overlapped via a ceramic layer has been obtained.

【0004】ところで、上記マザーの積層体を切断する
に際しては、切断刃やダイサーが用いられていた。図5
及び図6を参照して、従来の積層セラミック電子部品の
製造方法における上記切断工程を説明する。
In cutting the mother laminate, a cutting blade or a dicer has been used. FIG.
With reference to FIG. 6 and FIG. 6, the cutting step in the conventional method for manufacturing a multilayer ceramic electronic component will be described.

【0005】図5は、切断刃を用いて、マザーの積層体
を切断する工程を説明するための部分切欠断面図であ
る。マザーの積層体51では、複数の内部電極52がセ
ラミック層を介して積層されて、積層セラミック電子部
品部分53,54が形成されている。図5では、特に図
示はしないが、積層セラミック電子部品部分53,54
以外にも、多数の積層セラミック電子部品部分が同様に
構成されている。
FIG. 5 is a partially cutaway sectional view for explaining a step of cutting a mother laminate using a cutting blade. In the mother laminate 51, a plurality of internal electrodes 52 are laminated via a ceramic layer to form laminated ceramic electronic component parts 53 and 54. In FIG. 5, although not particularly shown, the laminated ceramic electronic component parts 53 and 54 are not shown.
Besides, many multilayer ceramic electronic components are similarly configured.

【0006】上記マザーの積層体51を得た後、まず、
積み重ね方向に加圧し、セラミック層と内部電極とを密
着させる。しかる後、個々の積層セラミック電子部品部
分単位に分割するために、切断刃55を用いて図示の破
線Aに沿ってマザーの積層体51を切断する。すなわ
ち、隣接する積層セラミック電子部品部分53,54の
内部電極52,52間のギャップの中央において、破線
Aに沿って切断刃55を用いてマザーの積層体51を切
断する。
After obtaining the mother laminate 51, first,
Pressure is applied in the stacking direction to bring the ceramic layer and the internal electrode into close contact. Thereafter, the mother laminate 51 is cut along the dashed line A by using the cutting blade 55 in order to divide the multilayer ceramic electronic component into partial units. That is, at the center of the gap between the internal electrodes 52, 52 of the adjacent laminated ceramic electronic component parts 53, 54, the mother laminate 51 is cut along the broken line A using the cutting blade 55.

【0007】この切断により、積層セラミック電子部品
部分53と積層セラミック電子部品部分54とが分割さ
れる。このようにして、切断刃55を用いてマザーの積
層体51を切断することにより、個々の積層セラミック
電子部品部分53,54が得られる。この切断刃55を
用いた切断においては、マザーの積層体51が破線Aに
沿って分割されるだけであり、切断によりマザーの積層
体51の一部は殆ど除去されない。
By this cutting, the multilayer ceramic electronic component portion 53 and the multilayer ceramic electronic component portion 54 are divided. By cutting the mother laminate 51 using the cutting blades 55 in this manner, individual laminated ceramic electronic component parts 53 and 54 are obtained. In the cutting using the cutting blade 55, the mother laminate 51 is merely divided along the broken line A, and a part of the mother laminate 51 is hardly removed by the cutting.

【0008】他方、図6に示すように、ダイサー56を
用いてマザーの積層体51を切断する方法も用いられて
いる。ダイサー56を用いる方法では、図5の場合と同
様に、隣り合う積層セラミック電子部品部分53,54
間の間隔のほぼ中央において、マザーの積層体51を切
断する。もっとも、ダイサー56を用いた場合には、ダ
イサー56の切断幅に応じて、マザーの積層体51を構
成している未焼成のセラミック部分が除去される。
On the other hand, as shown in FIG. 6, a method of cutting a mother laminate 51 using a dicer 56 is also used. In the method using the dicer 56, as in the case of FIG.
The mother laminated body 51 is cut at substantially the center of the interval between them. However, when the dicer 56 is used, the unsintered ceramic portion constituting the mother laminate 51 is removed according to the cutting width of the dicer 56.

【0009】[0009]

【発明が解決しようとする課題】例えば積層コンデンサ
のような積層セラミック電子部品では、小型化を進める
ために、より多くの内部電極が積層されると共に、重な
り合っている内部電極間のセラミック層の厚みがより薄
くなってきている。その結果、上記のようにマザーの積
層体51を得た後に、積み重ね方向に加圧してセラミッ
ク層と内部電極とを密着させ、切断する方法により積層
セラミック電子部品を得た場合、焼成後に、セラミック
焼結体端面において、セラミック層の層間剥離、いわゆ
るデラミネーションと称されている現象が生じがちであ
るという問題があった。
In a multilayer ceramic electronic component such as a multilayer capacitor, more internal electrodes are laminated and the thickness of the ceramic layer between the overlapping internal electrodes is reduced in order to reduce the size. Is getting thinner. As a result, after obtaining the mother laminate 51 as described above, when a multilayer ceramic electronic component is obtained by a method in which the ceramic layer and the internal electrode are brought into close contact with each other by pressing in the stacking direction and cut, On the end face of the sintered body, there has been a problem that a phenomenon called delamination, that is, delamination of the ceramic layer tends to occur.

【0010】本発明の目的は、マザーの積層体を用いて
積層セラミック電子部品を効率良く製造する方法におい
て、最終的に得られた積層セラミック電子部品における
セラミック層間のデラミネーションが生じがたい、積層
セラミック電子部品の製造方法を提供することにある。
An object of the present invention is to provide a method for efficiently manufacturing a multilayer ceramic electronic component using a mother laminate, in which delamination between ceramic layers in a finally obtained multilayer ceramic electronic component is unlikely to occur. An object of the present invention is to provide a method for manufacturing a ceramic electronic component.

【0011】[0011]

【課題を解決するための手段】請求項1に記載の発明に
係る積層セラミック電子部品の製造方法は、複数の内部
電極がセラミック層を介して積層されている積層セラミ
ック電子部品部分が所定の間隔を隔てて複数形成されて
いる未焼成のマザーの積層体を用意する工程と、前記マ
ザーの積層体を積み重ね方向に加圧する工程と、前記マ
ザーの積層体を個々の積層セラミック電子部品単位の積
層体に分割するために切断するにあたり、積層セラミッ
ク電子部品部分の内部電極と、該電子部品部分に隣接す
る積層セラミック電子部品部分の内部電極との間の間隔
をXとしたとき、隣接する電子部品部分間のほぼ中央部
において、(1/3)X以上の幅の積層体部分が除去さ
れるようにマザーの積層体を切断する工程と、前記切断
工程により得られた個々の積層セラミック電子部品単位
の積層体を焼成して焼結体を得る工程と、前記焼結体の
外表面に内部電極に接続されるように外部電極を形成す
る工程とを備えることを特徴とする。
According to a first aspect of the present invention, there is provided a method of manufacturing a multilayer ceramic electronic component, wherein a portion of the multilayer ceramic electronic component in which a plurality of internal electrodes are stacked via a ceramic layer is disposed at a predetermined interval. Preparing a plurality of unfired mother laminates formed at a distance from each other; pressing the mother laminate in a stacking direction; and laminating the mother laminate in individual multilayer ceramic electronic component units. When the space between the internal electrode of the multilayer ceramic electronic component portion and the internal electrode of the multilayer ceramic electronic component portion adjacent to the electronic component portion is defined as X when cutting to divide into the body, the adjacent electronic component A step of cutting the mother laminate such that a portion of the laminate having a width of (1 /) X or more is removed at a substantially central portion between the portions; A step of firing a laminate of individual multilayer ceramic electronic component units to obtain a sintered body; and a step of forming an external electrode on the outer surface of the sintered body so as to be connected to an internal electrode. And

【0012】請求項2に記載の発明では、上記切断は、
切断幅が(1/3)X以上のダイサーを用いて行われ
る。請求項3に記載の発明では、上記積層セラミック電
子部品として積層コンデンサが製造される。
In the invention according to claim 2, the cutting is performed by:
The cutting is performed using a dicer having a cutting width of (1 /) X or more. According to the third aspect of the invention, a multilayer capacitor is manufactured as the multilayer ceramic electronic component.

【0013】以下、本発明の詳細を説明する。従来の積
層セラミック電子部品おいて、小型化及び多層化を進め
た場合にデラミネーションが生じがちとなる理由につい
て検討した結果、マザーの積層体から個々の積層セラミ
ック電子部品単位の積層体に切断した際に、切断面近傍
において歪みが生じており、焼成後に歪みに起因するデ
ラミネーションが生じていることが確かめられた。
Hereinafter, the present invention will be described in detail. In a conventional multilayer ceramic electronic component, as a result of examining the reason why delamination tends to occur when miniaturization and multilayering are promoted, the mother multilayer was cut into individual multilayer ceramic electronic component units. At this time, distortion occurred near the cut surface, and it was confirmed that delamination due to the distortion occurred after firing.

【0014】すなわち、積層セラミック電子部品の製造
にあたり、内部電極の積層数を増大し、小型化及び多層
化を進めた場合、マザーの積層体を得た後に加圧する
と、内部電極52が積層されている部分と、積層されて
いない部分B(図5参照)とでは、圧力の加わり方に大
きな差が生じている。内部電極52が積層されていない
部分Bでは、圧力が加わりがたいため、密度が低く、逆
に、内部電極52が積層されている部分では圧力が加わ
りやすく、加圧後の密度が高められている。
That is, in the production of a multilayer ceramic electronic component, when the number of laminated internal electrodes is increased, and miniaturization and multi-layering are promoted, when a mother laminate is pressed and then pressed, the internal electrodes 52 are laminated. There is a large difference in the way in which pressure is applied between the portion where the pressure is applied and the portion B where the layers are not stacked (see FIG. 5). In the portion B where the internal electrodes 52 are not laminated, pressure is hard to be applied, so that the density is low, and conversely, in the portion where the internal electrodes 52 are laminated, pressure is easily applied, and the density after pressurization is increased. I have.

【0015】従って、内部電極52が積層されている部
分と、積層されていない部分Bとの間で未焼成のセラミ
ック層に図6に破線Cで示すような歪みが生じていた。
この歪みは、隣接する積層セラミック電子部品53,5
4間のギャップの中央で最も大きくなっているものと考
えられる。
Accordingly, a distortion as shown by a broken line C in FIG. 6 occurs in the unfired ceramic layer between the portion where the internal electrode 52 is laminated and the portion B where the internal electrode 52 is not laminated.
This distortion is caused by the adjacent multilayer ceramic electronic components 53 and 5.
It is considered that it is the largest at the center of the gap between the four.

【0016】そのため、切断刃55やダイサー56を用
いてマザーの積層体51を切断した場合、切断面近傍に
歪みが残存しており、後工程で個々の積層体を焼成して
得られた焼結体において、上記切断面に相当する面にお
いてデラミネーションが発生しているものと考えられ
る。
Therefore, when the mother laminate 51 is cut using the cutting blade 55 and the dicer 56, distortion remains near the cut surface, and the firing obtained by firing the individual laminates in a later step is performed. It is considered that delamination has occurred in the surface corresponding to the cut surface in the union.

【0017】本発明は、内部電極が積層されていない部
分Bの歪みに起因するデラミネーションを抑制するため
に、上記のように、隣接する積層セラミック電子部品の
内部電極間の間隔をXとしたときに、隣接する電子部品
部分間のほぼ中央部において、(1/3)X以上の幅の
積層体部分が除去されるようにマザーの積層体を切断す
ることにより、歪みの大きな積層体部分を除去し、それ
によって上記デラミネーションの発生を抑制したことに
特徴を有する。
In the present invention, in order to suppress the delamination caused by the distortion of the portion B where the internal electrodes are not stacked, the distance between the internal electrodes of the adjacent multilayer ceramic electronic components is set to X as described above. In some cases, the mother laminate is cut such that a laminate having a width of (1 /) X or more is removed at a substantially central portion between adjacent electronic component parts, thereby providing a laminate having a large distortion. , Thereby suppressing the occurrence of the delamination.

【0018】[0018]

【発明の実施の形態】以下、本発明の一実施例を図面を
参照しつつ、より具体的に説明する。本実施例では、マ
ザーの積層体を用い、図3に略図的に示す積層コンデン
サ1を製造する。まず、図4に示すマザーのセラミック
グリーンシート2,3を用意する。マザーのセラミック
グリーンシート2,3は、チタン酸バリウム系セラミッ
クスのような適宜の誘電体セラミックスを主体とするセ
ラミックスラリーをシート成形することにより得られ
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below more specifically with reference to the drawings. In the present embodiment, a multilayer capacitor 1 schematically shown in FIG. 3 is manufactured using a mother laminate. First, mother ceramic green sheets 2 and 3 shown in FIG. 4 are prepared. The mother ceramic green sheets 2 and 3 are obtained by sheet-forming a ceramic slurry mainly composed of an appropriate dielectric ceramic such as a barium titanate-based ceramic.

【0019】マザーのセラミックグリーンシート2,3
上に、それぞれ、例えばNiを主体とする導電ペースト
をスクリーン印刷することにより、内部電極4,5を形
成する。
Mother's ceramic green sheets 2 and 3
The internal electrodes 4 and 5 are formed on the upper surface by screen printing, for example, a conductive paste mainly composed of Ni.

【0020】次に、マザーのセラミックグリーンシート
2,3を交互に複数枚積層し、上下に、内部電極が印刷
されていない無地のセラミックグリーンシートを適宜の
枚数積層し、マザーの積層体を得る。
Next, a plurality of mother ceramic green sheets 2 and 3 are alternately laminated, and an appropriate number of plain ceramic green sheets on which no internal electrodes are printed are laminated above and below to obtain a mother laminate. .

【0021】このようにして得られたマザーの積層体を
積層方向に加圧した後、図1及び図2に示すように切断
する。すなわち、図1に示すように、マザーの積層体6
では、上記した内部電極4,5が交互に積層されている
積層セラミック電子部品部分7,8が所定の間隔を隔て
て配置されている。なお、図1は、図4中のE−E線に
相当の部分で切断した部分の断面図である。また、図2
は、上記マザーの積層体6を図1の紙面−紙背方向に沿
って切断した部分の断面図に相当する。すなわち、図4
のD−D線に沿う部分に相当する部分の断面図である。
After the mother laminate thus obtained is pressed in the laminating direction, it is cut as shown in FIGS. That is, as shown in FIG.
In this example, the laminated ceramic electronic component portions 7, 8 in which the internal electrodes 4, 5 described above are alternately laminated are arranged at predetermined intervals. FIG. 1 is a cross-sectional view of a portion cut along a portion corresponding to line EE in FIG. FIG.
Corresponds to a cross-sectional view of a portion of the mother laminate 6 cut along the paper surface-back direction of FIG. That is, FIG.
FIG. 4 is a cross-sectional view of a portion corresponding to a portion along the line DD of FIG.

【0022】上記マザーの積層体6を切断し、個々の積
層セラミック電子部品部分7,8を得るにあたっては、
積層セラミック電子部品部分7の内部電極4と、隣接す
る積層セラミック電子部品部分8の内部電極4との間の
間隔をXとしたときに、隣接する両電子部品部分7,8
間のほぼ中央部において、(1/3)X以上の幅の積層
体部分が除去されるように切断を行う。本実施例では、
この切断を行うために、切断幅が(1/3)X以上のダ
イサー9が用いられる。
In cutting the mother laminate 6 to obtain individual multilayer ceramic electronic component parts 7 and 8,
When the distance between the internal electrode 4 of the multilayer ceramic electronic component portion 7 and the internal electrode 4 of the adjacent multilayer ceramic electronic component portion 8 is X, the two adjacent electronic component portions 7, 8
The cutting is performed so that the laminated body portion having a width of (1 /) X or more is removed at a substantially central portion between them. In this embodiment,
In order to perform this cutting, a dicer 9 having a cutting width of (1 /) X or more is used.

【0023】上記のように、ダイサー9を用いてマザー
の積層体6を厚み方向に切断し、個々の積層セラミック
電子部品部分7,8を得る。なお、図2に示すように、
図1に示されている部分とは直交する方向の端面におい
ては、個々の積層セラミック電子部品部分7,10が隣
りあっている。この場合、積層セラミック電子部品部分
7の内部電極5と、隣り合う積層セラミック電子部品部
分10の内部電極5との間の間隔がXとされ、隣接する
両電子部品部分7,10間のほぼ中央部において、同様
に(1/3)X以上の幅の積層体部分が除去されるよう
に、マザーの積層体6を切断する。すなわち、内部電極
4は、図2に示す断面方向では、隣り合う積層セラミッ
ク電子部品部分間に至るように形成されているため、こ
の方向においては内部電極5,5間の間隔が間隔Xとさ
れる。
As described above, the mother laminate 6 is cut in the thickness direction using the dicer 9 to obtain individual multilayer ceramic electronic component parts 7 and 8. In addition, as shown in FIG.
On the end face in a direction orthogonal to the portion shown in FIG. 1, the individual multilayer ceramic electronic component portions 7 and 10 are adjacent to each other. In this case, the distance between the internal electrode 5 of the multilayer ceramic electronic component portion 7 and the internal electrode 5 of the adjacent multilayer ceramic electronic component portion 10 is X, and the center between the adjacent electronic component portions 7 and 10 is substantially the center. In the part, similarly, the mother laminate 6 is cut so that the laminate portion having a width of (1 /) X or more is removed. That is, in the cross-sectional direction shown in FIG. 2, the internal electrodes 4 are formed so as to extend between adjacent multilayer ceramic electronic component parts. You.

【0024】上記のようにして、個々の積層セラミック
電子部品部分の積層体を得、常法に従って焼成すること
により、個々の積層セラミック電子部品単位の焼結体を
得ることができる。このようにして、図3に示す焼結体
11が得られる。焼結体11内においては、複数の内部
電極4A,5Aが交互に積層されている。
As described above, a laminate of individual multilayer ceramic electronic component parts is obtained and fired according to a conventional method, whereby a sintered body of each multilayer ceramic electronic component unit can be obtained. Thus, the sintered body 11 shown in FIG. 3 is obtained. In the sintered body 11, a plurality of internal electrodes 4A and 5A are alternately stacked.

【0025】内部電極4Aは、セラミック焼結体11の
一方の端面11aに引き出されており、内部電極5Aは
端面11aとは反対側の端面11bに引き出されてい
る。端面11a,11bを覆うように、例えばAgペー
ストを塗布し、焼き付けることにより、外部電極12、
13が形成され、それによって積層コンデンサが1が得
られる。
The internal electrode 4A is extended to one end face 11a of the ceramic sintered body 11, and the internal electrode 5A is extended to an end face 11b opposite to the end face 11a. By coating and baking, for example, an Ag paste so as to cover the end surfaces 11a, 11b, the external electrodes 12,
Thus, a multilayer capacitor 1 is obtained.

【0026】本実施例の製造方法では、上記のようにマ
ザーの積層体6を厚み方向に切断するに際し、隣接する
電子部品部分間のほぼ中央部において、(1/3)X以
上の幅の積層体部分が除去されるようにマザーの積層体
6が切断される。従って、歪みの最も大きな積層体部分
が切断により除去されることになるため、得られた個々
の積層体において切断面近傍の歪みが小さくされてい
る。よって、焼結体11の側面及び端面におけるデラミ
ネーションの発生が効果的に抑制される。これを、具体
的な実験例に基づき説明する。
According to the manufacturing method of this embodiment, when the mother laminate 6 is cut in the thickness direction as described above, the width of (1/3) X or more is approximately at the center between the adjacent electronic parts. The mother laminate 6 is cut so that the laminate portion is removed. Therefore, since the portion of the laminate having the largest distortion is removed by cutting, the distortion in the vicinity of the cut surface of each obtained laminate is reduced. Therefore, the occurrence of delamination on the side surface and the end surface of the sintered body 11 is effectively suppressed. This will be described based on specific experimental examples.

【0027】上記積層コンデンサ1として、1.6×
0.8×0.8mmの寸法を有し、Niを主体とする内
部電極が160枚積層されており、隣接する内部電極間
のセラミック層の厚みが3μmであり、設計静電容量値
が1μFの積層コンデンサ1を製造した。この場合、マ
ザーの積層体6を切断するにあたり、下記の表1に示す
ように間隔Xに対し、切断により積層体が除去される部
分の幅を、0、0.1X、0.2X、0.3X、及び
0.5Xとし、それぞれ積層体を得た。そして、得られ
た積層体を焼成し、焼結体を得た。このようにして得ら
れた各焼結体について、側面及び端面を観察し、内部
電極とセラミック層との間の剥がれの発生割合及びデ
ラミネーションの発生割合を以下の要領で評価した。
As the multilayer capacitor 1, 1.6 ×
It has dimensions of 0.8 × 0.8 mm, 160 internal electrodes mainly composed of Ni are laminated, the thickness of the ceramic layer between adjacent internal electrodes is 3 μm, and the design capacitance value is 1 μF. Was manufactured. In this case, when cutting the mother laminate 6, the width of the portion where the laminate is removed by cutting is set to 0, 0.1X, 0.2X, 0 with respect to the interval X as shown in Table 1 below. .3X and 0.5X to obtain laminates. Then, the obtained laminate was fired to obtain a sintered body. With respect to each of the thus obtained sintered bodies, the side face and the end face were observed, and the rate of occurrence of peeling and the rate of occurrence of delamination between the internal electrode and the ceramic layer were evaluated in the following manner.

【0028】内部電極とセラミック層との剥がれの割
合…目視による外観の検査により不良品の割合を算出し
た。 デラミネーションの発生割合…焼結体の長さ方向と積
層方向とに平行な面を研磨し、電子顕微鏡による検査か
ら不具合の発生率を算出した。
Ratio of peeling between internal electrode and ceramic layer: The ratio of defective products was calculated by visual inspection of appearance. Delamination generation rate: A surface parallel to the length direction and the laminating direction of the sintered body was polished, and the occurrence rate of defects was calculated from inspection with an electron microscope.

【0029】結果を下記の表1に示す。なお、表1にお
いては、上記,の評価は、それぞれ1000個の焼
結体についての平均値である。
The results are shown in Table 1 below. In Table 1, the above evaluations are average values for 1000 sintered bodies.

【0030】[0030]

【表1】 [Table 1]

【0031】表1から明らかなように、切断幅、すなわ
ち切断によりマザーの積層体が除去される部分の幅を
0.3X以上とした場合、内部電極とセラミック層との
間の剥がれ及びデラミネーションの発生が皆無であった
のに対し、切断幅が0.2X以下の場合には、内部電極
とセラミック層との剥がれ及びデラミネーションの発生
が認められた。従って、上記実施例のように、隣接する
積層セラミック電子部品部分間において、切断幅を0.
3X以上とすれば、内部電極とセラミック層との間の剥
がれ及びセラミック層間のデラミネーションを確実に防
止し得ることがわかる。
As is clear from Table 1, when the cut width, that is, the width of the portion where the mother laminate is removed by cutting is set to 0.3X or more, peeling and delamination between the internal electrode and the ceramic layer are performed. When the cutting width was 0.2X or less, peeling between the internal electrode and the ceramic layer and occurrence of delamination were observed. Therefore, as in the above embodiment, the cutting width between adjacent multilayer ceramic electronic component portions is set to 0.
It can be seen that when the value is 3X or more, peeling between the internal electrode and the ceramic layer and delamination between the ceramic layers can be reliably prevented.

【0032】なお、上記実施例では、積層コンデンサの
製造方法につき説明したが、本発明は、複数の内部電極
を介してセラミック層が積層されている未焼成のマザー
の積層体における上記部分的な歪みに起因するデラミネ
ーションの発生を抑制するものであるため、積層コンデ
ンサだげでなく、積層バリスタ、積層セラミック基板、
積層セラミック圧電部品、積層サーミスタなど様々な積
層セラミック電子部品の製造に用いることができ、上記
と同様の効果を得ることができる。
In the above embodiment, a method of manufacturing a multilayer capacitor has been described. However, the present invention relates to a method for manufacturing a multilayer capacitor in which a ceramic layer is stacked via a plurality of internal electrodes. Since it suppresses the occurrence of delamination due to distortion, not only multilayer capacitors but also multilayer varistors, multilayer ceramic substrates,
It can be used for manufacturing various multilayer ceramic electronic components such as a multilayer ceramic piezoelectric component and a multilayer thermistor, and the same effects as described above can be obtained.

【0033】[0033]

【発明の効果】請求項1に記載の発明に係る積層セラミ
ック電子部品の製造方法では、マザーの積層体を切断し
て個々の積層セラミック電子部品単位の積層体を得るに
あたり、隣接する積層セラミック電子部品部分間の内部
電極間の間隔をXとしたときに、隣接する電子部品部分
間のほぼ中央部において、(1/3)X以上の幅の積層
体部分が除去されるようにマザーの積層体が切断され
る。従って、最も歪みの大きな部分が切断により除去さ
れるため、得られた個々の積層体の切断面近傍は低歪化
される。よって、該積層体を焼成することにより得られ
た焼結体における内部電極とセラミック層との間の剥離
やセラミック層間のデラミネーションを効果的に抑制す
ることができ、耐湿性などの信頼性に優れた積層セラミ
ック電子部品を安定に提供することが可能となる。
In the method for manufacturing a multilayer ceramic electronic component according to the first aspect of the present invention, when the mother laminate is cut to obtain a laminate of individual multilayer ceramic electronic components, adjacent multilayer ceramic electronic components are obtained. Assuming that the interval between the internal electrodes between the component parts is X, the mother lamination is performed so that a laminate part having a width of (1 /) X or more is removed at a substantially central portion between adjacent electronic component parts. The body is severed. Therefore, since the portion having the largest distortion is removed by cutting, the vicinity of the cut surface of each obtained laminate is reduced in distortion. Therefore, peeling between the internal electrode and the ceramic layer and delamination between the ceramic layers in the sintered body obtained by firing the laminate can be effectively suppressed, and reliability such as moisture resistance can be improved. It is possible to stably provide excellent multilayer ceramic electronic components.

【0034】請求項2に記載の発明では、切断が、切断
幅が(1/3)X以上のダイサーを用いて切断されるた
め、従来のダイサーに代えて、切断幅が異なるダイサー
を用意するだけで、工程数を増加することなく、従来と
同じ工程で、デラミネーションの発生や内部電極とセラ
ミック層との間の剥離を確実に防止することができる。
According to the second aspect of the present invention, since the cutting is performed by using a dicer having a cutting width of (3) X or more, a dicer having a different cutting width is prepared instead of the conventional dicer. In this way, it is possible to reliably prevent the occurrence of delamination and the separation between the internal electrode and the ceramic layer in the same steps as in the related art without increasing the number of steps.

【0035】請求項3に記載の発明では、上記積層セラ
ミック電子部品として、積層コンデンサが得られるの
で、積層コンデンサの小型化及び多層化に容易に対応す
ることができる。
According to the third aspect of the present invention, since a multilayer capacitor is obtained as the multilayer ceramic electronic component, it is possible to easily cope with miniaturization and multilayering of the multilayer capacitor.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例においてマザーの積層体をダ
イサーを用いて切断する工程を説明するための部分切欠
断面図。
FIG. 1 is a partially cutaway sectional view for explaining a step of cutting a mother laminate using a dicer in one embodiment of the present invention.

【図2】図1に示したマザーの積層体の異なる方向に沿
う断面において、マザーの積層体をダイサーを用いて切
断する工程を説明するための部分切欠断面図。
FIG. 2 is a partially cutaway cross-sectional view for explaining a step of cutting the mother laminate using a dicer in cross sections along different directions of the mother laminate illustrated in FIG. 1;

【図3】本発明の一実施例で得られる積層セラミック電
子部品としての積層コンデンサを示す断面図。
FIG. 3 is a sectional view showing a multilayer capacitor as a multilayer ceramic electronic component obtained in one embodiment of the present invention.

【図4】(a),(b)は、それぞれ、本発明の一実施
例において用意られるマザーのセラミックグリーンシー
ト及びその上に形成される内部電極パターンを説明する
ための各平面図。
FIGS. 4A and 4B are plan views respectively illustrating a mother ceramic green sheet prepared in an embodiment of the present invention and an internal electrode pattern formed thereon.

【図5】従来の積層コンデンサの製造方法においてマザ
ーの積層体を切断刃により切断する工程を説明するため
の部分切欠断面図。
FIG. 5 is a partially cutaway sectional view for explaining a step of cutting a mother laminate by a cutting blade in a conventional method for manufacturing a multilayer capacitor.

【図6】従来の積層コンデンサの製造に際しマザーの積
層体をダイサーを用いて切断する工程を説明するための
部分切欠断面図。
FIG. 6 is a partially cutaway cross-sectional view for explaining a step of cutting a mother laminate using a dicer in manufacturing a conventional multilayer capacitor.

【符号の説明】[Explanation of symbols]

1…積層コンデンサ(積層セラミック電子部品) 2,3…マザーのセラミックグリーンシート 4,5…内部電極 4A,5A…内部電極 6…マザーの積層体 7,8…個々の積層セラミック電子部品部分 9…ダイサー 10…積層セラミック電子部品部分 11…焼結体 12,13…外部電極 DESCRIPTION OF SYMBOLS 1 ... Multilayer capacitor (multilayer ceramic electronic component) 2, 3 ... Mother ceramic green sheet 4, 5 ... Internal electrode 4A, 5A ... Internal electrode 6 ... Mother laminated body 7, 8 ... Individual multilayer ceramic electronic component part 9 ... Dicer 10 ... Multilayer ceramic electronic parts 11 ... Sintered body 12,13 ... External electrode

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 複数の内部電極がセラミック層を介して
積層されている積層セラミック電子部品部分が所定の間
隔を隔てて複数形成されている未焼成のマザーの積層体
を用意する工程と、 前記マザーの積層体を積層方向に加圧する工程と、 前記マザーの積層体を個々の積層セラミック電子部品単
位の積層体に分割するために切断するにあたり、積層セ
ラミック電子部品部分の内部電極と、該電子部品部分に
隣接する積層セラミック電子部品部分の内部電極との間
の間隔をXとしたとき、隣接する電子部品部分間のほぼ
中央部において、(1/3)X以上の幅の積層体部分が
除去されるようにマザーの積層体を厚み方向に切断する
工程と、 前記切断工程により得られた個々の積層セラミック電子
部品単位の積層体を焼成して焼結体を得る工程と、 前記焼結体の外表面に内部電極に接続されるように外部
電極を形成する工程とを備えることを特徴とする、積層
セラミック電子部品の製造方法。
1. A step of preparing an unfired mother laminate in which a plurality of laminated ceramic electronic component parts in which a plurality of internal electrodes are laminated via a ceramic layer are formed at predetermined intervals. Pressing the mother laminate in the laminating direction; and cutting the mother laminate into individual laminate ceramic electronic component unit laminates, wherein the internal electrodes of the multilayer ceramic electronic component portion and the electronic Assuming that the distance between the internal electrode of the multilayer ceramic electronic component portion adjacent to the component portion is X, a laminate portion having a width of (1 /) X or more is substantially at the center between the adjacent electronic component portions. Cutting the mother laminate in the thickness direction so as to be removed; and firing the individual multilayer ceramic electronic component unit laminate obtained in the cutting step to obtain a sintered body. Forming an external electrode on the outer surface of the sintered body so as to be connected to the internal electrode.
【請求項2】 前記切断を、切断幅が(1/3)X以上
のダイサーを用いて行う、請求項1に記載の積層セラミ
ック電子部品の製造方法。
2. The method according to claim 1, wherein the cutting is performed using a dicer having a cutting width of (サ ー) X or more.
【請求項3】 前記積層セラミック電子部品が積層コン
デンサである請求項1または2に記載の積層セラミック
電子部品の製造方法。
3. The method for manufacturing a multilayer ceramic electronic component according to claim 1, wherein the multilayer ceramic electronic component is a multilayer capacitor.
JP15172798A 1998-06-01 1998-06-01 Manufacturing method of multilayer ceramic electronic component Expired - Lifetime JP3428434B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15172798A JP3428434B2 (en) 1998-06-01 1998-06-01 Manufacturing method of multilayer ceramic electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15172798A JP3428434B2 (en) 1998-06-01 1998-06-01 Manufacturing method of multilayer ceramic electronic component

Publications (2)

Publication Number Publication Date
JPH11345742A true JPH11345742A (en) 1999-12-14
JP3428434B2 JP3428434B2 (en) 2003-07-22

Family

ID=15524977

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Country Status (1)

Country Link
JP (1) JP3428434B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001313227A (en) * 2000-04-28 2001-11-09 Matsushita Electric Ind Co Ltd Manufacturing method of laminate and electronic component, and electronic component
JP2003017362A (en) * 2001-06-28 2003-01-17 Kyocera Corp Method of manufacturing ceramic laminate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001313227A (en) * 2000-04-28 2001-11-09 Matsushita Electric Ind Co Ltd Manufacturing method of laminate and electronic component, and electronic component
JP4533504B2 (en) * 2000-04-28 2010-09-01 パナソニック株式会社 Manufacturing method of electronic parts
JP2003017362A (en) * 2001-06-28 2003-01-17 Kyocera Corp Method of manufacturing ceramic laminate

Also Published As

Publication number Publication date
JP3428434B2 (en) 2003-07-22

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