JP2008091400A - Laminated ceramic capacitor and its manufacturing method - Google Patents

Laminated ceramic capacitor and its manufacturing method Download PDF

Info

Publication number
JP2008091400A
JP2008091400A JP2006267532A JP2006267532A JP2008091400A JP 2008091400 A JP2008091400 A JP 2008091400A JP 2006267532 A JP2006267532 A JP 2006267532A JP 2006267532 A JP2006267532 A JP 2006267532A JP 2008091400 A JP2008091400 A JP 2008091400A
Authority
JP
Japan
Prior art keywords
internal electrode
thickness
dielectric substrate
width
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006267532A
Other languages
Japanese (ja)
Inventor
Tatsuya Kojima
Raitaro Masaoka
Ryutaro Yamazaki
達也 小島
龍太郎 山▲崎▼
雷太郎 政岡
Original Assignee
Tdk Corp
Tdk株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tdk Corp, Tdk株式会社 filed Critical Tdk Corp
Priority to JP2006267532A priority Critical patent/JP2008091400A/en
Publication of JP2008091400A publication Critical patent/JP2008091400A/en
Pending legal-status Critical Current

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated ceramic capacitor that can ensure capacitance and prevent the deterioration of reliability due to the entry of a plating liquid into an internal electrode. <P>SOLUTION: When assuming that a first internal electrode formation area S1 is defined as a minimum rectangle surrounding internal electrodes 31 to 3n-1 at the end face 11 of a dielectric substrate 1 and that a second internal electrode formation area S2 is defined as a minimum rectangle surrounding internal electrodes 31 to 3n in the cross section 101 of the central part of the dielectric substrate 1, the first internal electrode formation area S1 and the second internal electrode S2 are formed so that the width W1 and thickness T1 of the first internal electrode formation area S1 and the width W2 and thickness T2 of the second internal electrode formation area S2 may satisfy the following inequalities: 0.35≤W1/W2≤0.9 and 0.35≤T1/T2≤0.9. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a multilayer ceramic capacitor and a method for manufacturing the same.

  In general, a multilayer ceramic capacitor is formed in a substantially rectangular parallelepiped dielectric base defined by a length direction, a width direction, and a thickness direction, an end face in the length direction of the dielectric base, and a corner portion around the end face. And an external electrode. A plurality of internal electrodes are embedded in the dielectric substrate so as to extend in the lengthwise direction with an interval in the thickness direction, and one end is drawn out to the end face of the dielectric substrate and connected to the external electrode. ing.

  The external electrode has a structure in which a plating film such as a Ni plating film is laminated on a base film (see Patent Document 1). The base film serves as an electrode film for depositing a plating film on the base film, and plays a role of ensuring the bonding strength with the dielectric substrate. The plating film plays a role of ensuring heat resistance when soldering the multilayer ceramic capacitor.

  In order to form such an external electrode, first, a base film is formed by attaching and baking a conductor paste on the end face and corner portion of the dielectric substrate. In the corner portion, since the amount of the conductive paste attached is small, the base film tends to be thin.

  Next, the dielectric substrate is immersed in the plating solution together with the base film to deposit a plating film on the base film. At this time, since the film thickness of the base film is thin at the corner portion of the dielectric substrate, the plating solution passes through the base film and reaches the surface of the corner portion of the dielectric substrate and penetrates into the internal electrode drawn to the end surface of the dielectric substrate. there's a possibility that. If the plating solution penetrates into the internal electrodes, the reliability of the multilayer ceramic capacitor is reduced, for example, the insulation resistance characteristic is deteriorated.

  As a technique for preventing the plating solution from entering the internal electrode, the internal electrode is not formed around the area where the internal electrode is formed, as viewed in a cross section perpendicular to the longitudinal direction of the dielectric substrate. A method of moving the internal electrode away from the corner portion of the dielectric substrate by making it considerably smaller than the region can be considered.

However, with this method, the area where the internal electrodes are formed becomes considerably small, and it is difficult to ensure the capacitance necessary for the multilayer ceramic capacitor.
JP 2000-114097 A

  An object of the present invention is to provide a multilayer ceramic capacitor and a method for manufacturing the same that can prevent deterioration in reliability due to penetration of a plating solution into an internal electrode while securing capacitance.

  In order to solve the above-described problem, a multilayer ceramic capacitor according to the present invention includes a dielectric substrate and a plurality of internal electrodes.

  The dielectric substrate has a substantially rectangular parallelepiped shape having a length direction, a width direction, and a thickness direction. The internal electrode is formed in such a manner that the internal electrode is embedded in layers in the thickness direction with a space therebetween, and one end is drawn out to the end surface in the length direction of the dielectric substrate.

  Forming a first internal electrode defined as a rectangle having a minimum dimension surrounding the internal electrode on the end face of the dielectric substrate, having two sides facing the width direction and two sides facing the thickness direction An area is assumed, and in the cross section parallel to the width direction and the thickness direction of the central portion of the dielectric substrate as viewed in the length direction, the two sides facing the width direction and the thickness direction are opposed. When assuming a second internal electrode formation region having two sides and defined as a rectangle of the minimum size surrounding the internal electrode, the first internal electrode formation region and the second internal electrode formation region are: The width and thickness dimensions of the first internal electrode formation region are W1 and T1, respectively, and the width and thickness dimensions of the second internal electrode formation region are W2 and T2, respectively. 0.35 ≦ W1 / W2 ≦ 0.9 And it is formed so as to satisfy 0.35 ≦ T1 / T2 ≦ 0.9.

  In the multilayer ceramic capacitor according to the present invention described above, the width dimension of the first and second internal electrode formation regions satisfies W1 / W2 ≦ 0.9, and the thickness dimension of the first and second internal electrode formation regions is T1. Since /T2≦0.9 is satisfied, both the width dimension and the thickness dimension of the internal electrode formation region are narrowed at the end face of the dielectric substrate with reference to the center portion of the dielectric substrate viewed in the length direction. become. Therefore, while ensuring the capacitance required for the multilayer ceramic capacitor at the center of the dielectric substrate, the internal electrode is kept away from the corner portion at the end surface of the dielectric substrate, thereby preventing the plating solution from entering the internal electrode. Can do.

  Furthermore, according to the results of experiments conducted by the inventors, it is understood that reliability deterioration due to penetration of the plating solution into the internal electrode can be prevented by satisfying W1 / W2 ≦ 0.9 and T1 / T2 ≦ 0.9. It was. It has also been found that the occurrence of cracks in the dielectric substrate can be prevented by satisfying W1 / W2 ≧ 0.35 and W1 / W2 ≧ 0.35.

  Furthermore, the present invention provides a method for manufacturing a multilayer ceramic capacitor. In the multilayer ceramic capacitor according to the present invention, the first dielectric green is formed in such a manner that the internal electrode layer has a capacitance forming portion and a lead portion narrower than the capacitance forming portion as viewed in one chip region. Prepare a sheet. Then, there is prepared a second dielectric green sheet that does not have an internal electrode layer on one side, and that has a thickness-imparting layer that overlaps with the lead portion and does not overlap with the capacitance forming portion as seen in one chip region. . Then, a sheet laminate including a plurality of the first dielectric green sheets and the second dielectric green sheets in the upper and lower layers of the plurality of first dielectric green sheets is manufactured. Then, by pressing the sheet laminated body in the laminating direction, the leading portion of the internal electrode layer is brought close to the center of the sheet laminated body in the laminating direction using the thickness of the thickness providing layer. Thereafter, the sheet laminate is cut into one chip region.

  According to the method for manufacturing a multilayer ceramic capacitor according to the present invention, the multilayer ceramic capacitor according to the present invention described above can be manufactured.

  Further, a step absorption layer may be formed in a region excluding the region where the internal electrode layer is formed on the one surface of the first dielectric green sheet.

  As described above, according to the present invention, it is possible to provide a multilayer ceramic capacitor and a method for manufacturing the same that can prevent deterioration in reliability due to penetration of a plating solution into an internal electrode while securing capacitance. .

  FIG. 1 is a perspective view showing an embodiment of a multilayer ceramic capacitor according to the present invention, and FIG. 2 is a cross-sectional view taken along line 2-2 of FIG. The illustrated multilayer ceramic capacitor includes a dielectric substrate 1, a plurality (n) of internal electrodes 31 to 3 n, and a pair of external electrodes 4 and 5.

  First, referring to FIG. 1, the dielectric substrate 1 is made of a ceramic material mainly composed of, for example, barium titanate, and is typically a ceramic sintered body. The dielectric substrate 1 has a substantially rectangular parallelepiped shape defined by the length direction L, the width direction W, and the thickness direction T. The dielectric substrate 1 has two end faces 11 and 12 facing the length direction L and Two side surfaces 13 and 14 and an upper surface 15 and a lower surface 16 opposite to the thickness direction T. In the drawing, the width dimension of the dielectric substrate 1 viewed in the width direction W and the thickness dimension viewed in the thickness direction are respectively represented by W0 and T0.

  Next, referring to FIG. 2, the internal electrodes 31 to 3 n are embedded in the dielectric substrate 1 in layers in the thickness direction T so as to be spaced apart from each other, and are alternately drawn out to the end surfaces 11 and 12 of the dielectric substrate. Formed. The internal electrodes 31 to 3n extend straight in the length direction L at the central portion in the length direction L of the dielectric substrate 1, and the central portions in the thickness direction T of the dielectric substrate 1 on the end surfaces 11 and 12 side. It is sent to. The internal electrodes 31 to 3n are made of, for example, Cu or Ni.

  FIG. 3 is a diagram showing a shape pattern of internal electrodes in the multilayer ceramic capacitor shown in FIGS. 1 and 2. As shown in FIG. 3A, an internal electrode with an odd number, for example, the internal electrode 31 includes a capacitance forming portion 301 and a lead portion 302. The capacitance forming unit 301 plays a role of securing a capacitance as a multilayer ceramic capacitor. The lead portion 32 plays a role of ensuring electrical continuity with the external electrode 4 (or the external electrode 5). The lead portion 32 is set to a width dimension W1 that is smaller than the width dimension W2 of the capacitance forming portion when viewed in the width direction W, and is drawn to the end face 11 of the dielectric substrate 1.

  As shown in FIG. 3B, the even-numbered internal electrode, for example, the internal electrode 32 also has a capacitance forming portion 301 and a lead-out portion 302. The internal electrodes with even numbers are the same as the internal electrodes with odd numbers except that the arrangement relationship between the capacitance forming portion 301 and the lead-out portion 302 is reversed left and right. Omitted.

  FIG. 4 is a view showing the end surface of the dielectric substrate along line 4-4 of FIG. On the end face 11 of the dielectric substrate 1, internal electrodes 31 to 3n-1 with odd numbers appear. The first internal electrode formation region S1 in the end face 11 has two sides opposite to the width direction W and two sides opposite to the thickness direction T, and is defined as a rectangle having the smallest dimension surrounding the internal electrodes 31 to 3n-1. can do. The first internal electrode formation region S1 has a width dimension W1 viewed in the width direction W and a thickness dimension T1 viewed in the thickness direction T.

  In FIG. 4, the internal electrodes 31 to 3n-1 do not cause any stacking deviation and are arranged at the same position as viewed in the width direction W. However, unlike FIG. 4, the internal electrodes 31 to 3n are arranged. In the case where any one of -1 causes misalignment and the positions viewed in the width direction W are misaligned, the first internal electrode formation region S1 has a rectangular shape including the internal electrodes where misalignment has occurred. Defined.

  Further, FIG. 4 shows a side margin dimension WG1 and an outer layer thickness dimension TG1 on the end face 11 of the dielectric substrate 1. The side margin dimension WG1 can be defined as the distance between the first internal electrode formation region S1 and the surface of the dielectric substrate 1 (for example, the back surface 14) viewed in the width direction W. The outer layer thickness dimension TG1 can be defined as the distance between the first internal electrode formation region S1 viewed in the thickness direction T and the surface of the dielectric substrate 1 (for example, the upper surface 15).

  FIG. 5 is a cross-sectional view taken along the line 5-5 in FIG. 2 at the center of the dielectric substrate as viewed in the length direction. In the cross section 101 at the center of the dielectric substrate 1, n layers of internal electrodes 31 to 3n appear. The second internal electrode formation region S2 in the cross section 101 has two sides opposite to the width direction W and two sides opposite to the thickness direction T, and is defined as a rectangle having the smallest dimension surrounding the internal electrodes 31 to 3n. Can do. The second internal electrode formation region S2 has a width dimension W2 viewed in the width direction W and a thickness dimension T2 viewed in the thickness direction. When any one of the internal electrodes 31 to 3n is misaligned and disposed in a position shifted in the width direction W, the second internal electrode formation region S2 includes the internal electrode in which the misalignment occurs. It is the same as the first internal electrode formation region S1 that is defined as a rectangular shape.

  Further, FIG. 5 shows a side margin dimension WG2 and an outer layer thickness dimension TG2 in the central section 101 of the dielectric substrate 1. The side margin dimension WG2 can be defined as the distance between the second internal electrode formation region S2 viewed in the width direction W and the surface of the dielectric substrate 1 (for example, the back surface 14). The outer layer thickness dimension TG2 can be defined as the distance between the second internal electrode formation region S2 viewed in the thickness direction T and the surface of the dielectric substrate 1 (for example, the upper surface 15).

  Again, referring back to FIG. 1 and FIG. The external electrode 4 has a structure in which a base film 41, a first plating film 42 and a second plating film are laminated, and straddles the end surface 11, the side surfaces 13 and 14, the upper surface 15 and the lower surface 16 of the dielectric substrate 1. Is formed.

  First, the base film 41 is a sintered metal film attached to the end surface 11, the side surfaces 13 and 14, the upper surface 15, and the lower surface 16 of the dielectric substrate 1, and is connected to the internal electrode 2 on the end surface 11 of the dielectric substrate 1. ing. The base film 41 made of a sintered metal film is prepared by mixing a metal powder or an alloy powder with a binder and a solvent to prepare a conductive paste. The conductive paste is used for the end face 11, the side faces 13 and 14, and the upper face 15 of the dielectric substrate 1. And it can form by apply | coating to the lower surface 16, and baking. Examples of the sintered metal film include a sintered film of Cu, Ni, Ag, or Ag—Pd.

  Next, the first plating film 42 is a plating film formed by electroplating, and is formed in an upper layer of the base film 41. Specifically, the first plating film 42 is directly attached to the surface of the base film 41. An example of the first plating film 42 is a Ni plating film.

  Finally, the second plating film 43 is a plating film formed by electroplating, and is formed in the upper layer of the first plating film 42. Specifically, the second plating film 43 is directly attached to the surface of the first plating film 42. An example of the second plating film 43 is a Sn plating film.

  Similar to the external electrode 4, the external electrode 5 has a structure in which a base film 41, a first plating film 42, and a second plating film are laminated, and the end surface 12, the side surfaces 13, 14, and the top surface of the dielectric substrate 1. 15 and the lower surface 16. Hereinafter, the description of the external electrode 5 is omitted, and the external electrode 4 is representatively described.

  The second plating film 43 located in the uppermost layer in the external electrode 4 is an Sn plating film. The second plating film 43 made of Sn plating film plays a role of ensuring affinity with solder during soldering.

  The first plating film 42 located below the second plating film 43 is a Ni plating film. The 1st plating film 42 which consists of Ni plating film plays the role which prevents the role which ensures the heat resistance at the time of soldering.

  The base film 41 located below the first plating film 42 is a sintered metal film. The base film 41 made of a sintered metal film serves as an electrode film for depositing the first plating film 42 thereon and plays a role of ensuring the bonding strength with the dielectric substrate 1.

  In order to form such an external electrode 4, first, a conductive paste is attached to the end surface 11, the side surfaces 13, 14, the upper surface 15, and the lower surface 16 of the dielectric substrate 1 by a dip method (dip method) and baked. Then, the base film 41 is formed. At this time, in the corner portions 21 to 24 (see FIG. 1) of the dielectric substrate 1, since the amount of the conductive paste attached is small, the film thickness of the base film 41 tends to be thin.

  Next, the dielectric substrate 1 is immersed in the plating solution together with the base film 41, and a first plating film 42 is deposited on the base film 41. At this time, since the base film 41 is thin at the corner portions 21 to 24 of the dielectric substrate 1, the plating solution passes through the base film 41 and reaches the surfaces of the corner portions 21 to 24 of the dielectric substrate 1. There is a possibility that the internal electrodes 31 to 3n-1 led out to the end face 11 of the substrate 1 may enter. If the plating solution enters the internal electrodes 31 to 3n-1, the reliability of the multilayer ceramic capacitor is lowered, for example, the insulation resistance characteristic is deteriorated.

In the present invention, the first internal electrode formation region S1 in the end face 11 of the dielectric substrate 1 and the first internal electrode formation region S2 in the central section 101 of the dielectric substrate are expressed by the following relational expression (1) and It is formed so as to satisfy (2).
0.35 ≦ W1 / W2 ≦ 0.9 (1)
0.35 ≦ T1 / T2 ≦ 0.9 (2)
As can be seen from W1 / W2 ≦ 0.9 and T1 / T2 ≦ 0.9, the first internal electrode formation region S1 has both width and thickness dimensions on the basis of the second internal electrode formation region S2. Is squeezed about. Accordingly, the internal electrodes 31 to 3n-1 are connected from the corner portions 21 to 24 on the end surface 11 of the dielectric substrate 1 while ensuring the capacitance necessary for the multilayer ceramic capacitor at the central section 101 of the dielectric substrate 1. The plating solution intrusion into the internal electrodes 31 to 3n-1 can be suppressed.

  The same applies to the relationship between the first internal electrode formation region (not shown) on the other end face 12 of the dielectric substrate 1 and the first internal electrode formation region S2 in the central cross section 101 of the dielectric substrate. And satisfies the relational expressions (1) and (2) described above.

About the point which suppresses plating solution penetration | invasion to an internal electrode, the experimental data described in Table 1-Table 5 is given and demonstrated. The table shows the following data for each sample No.
Dielectric substrate width dimension W0 and thickness dimension T0
Side margin dimension WG1 and outer layer thickness dimension TG1 at the end face of the dielectric substrate
The width dimension W1 and the thickness dimension T1 of the first internal electrode formation region on the end face of the dielectric substrate
Side margin dimension WG2 and outer layer thickness dimension TG2 in the central section of the dielectric substrate
The width dimension W2 and the thickness dimension T2 of the second internal electrode formation region in the central section of the dielectric substrate
Dimension ratio WG1 / W1
Dimension ratio TG1 / T1
Dimension ratio W1 / W2
Dimension ratio T1 / T2
Reliability degradation rate Crack generation rate Here, the reliability degradation rate is the ratio of the multilayer ceramic capacitor whose insulation resistance value has decreased by more than one digit when measured again after 1000 hours with respect to the initial insulation resistance value. Point to. In addition, 100 laminated ceramic capacitors were produced for each sample No.

  Throughout Tables 1 to 5, both the width dimension W and the thickness dimension T of the dielectric substrate were kept constant at 500 μm. Then, for each of Tables 1 to 5, the side margin dimension WG2 and the outer layer thickness dimension TG2 in the central section of the dielectric substrate are made constant, so that the width of the first internal electrode formation region on the end surface of the dielectric substrate The dimension W1 and the thickness dimension T1 were constant. Further, by changing the side margin dimension WG1 and the outer layer thickness dimension TG1 on the end face of the dielectric substrate, the width dimension W2 and the thickness dimension T2 of the second internal electrode formation region in the central section of the dielectric substrate are changed. I let you. As a result, the dimensional ratio W1 / W2 and the dimensional ratio T1 / T2 between the first and second internal electrode formation regions were changed.

  Table 1 shows experimental data when both the side margin dimension WG2 and the outer layer thickness dimension TG2 in the central section of the dielectric substrate are 25 μm, and Table 2 shows the side margin dimension WG2 and the outer layer in the central section of the dielectric substrate. Experimental data when the thickness dimension TG2 is both 50 μm, Table 3 is experimental data when both the side margin dimension WG2 and the outer layer thickness dimension TG2 in the central section of the dielectric substrate are 75 μm, Table 4 Experimental data when both the side margin dimension WG2 and the outer layer thickness dimension TG2 in the central section of the dielectric substrate are 100 μm, Table 5 shows the side margin dimension WG2 in the central section of the dielectric substrate as 50 μm, and the outer layer thickness. This is experimental data when the dimension TG2 is 75 μm.

  First, refer to Table 1. As shown in Samples 3 to 9, when both the dimensional ratio W1 / W2 and the dimensional ratio T1 / T2 are 0.9 or less, the reliability deterioration rate can be suppressed to less than 5%. On the other hand, as shown in Samples 1 and 2, when either the dimensional ratio W1 / W2 or the dimensional ratio T1 / T2 exceeds 0.9, the reliability deterioration rate increases beyond 5%.

  Further, as shown in Samples 1 to 7, when both the dimensional ratio W1 / W2 and the dimensional ratio T1 / T2 are 0.35 or more, the crack generation rate can be suppressed to less than 5%. On the other hand, as shown in Samples 8 and 9, when either the dimensional ratio W1 / W2 or the dimensional ratio T1 / T2 is less than 0.35, the crack generation rate increases by more than 5%.

  Next, refer to Table 2. As shown in Samples 13 to 18, when both the dimensional ratio W1 / W2 and the dimensional ratio T1 / T2 are 0.9 or less, the reliability deterioration rate can be suppressed to less than 5%. On the other hand, as shown in Samples 10 to 12, when either the dimensional ratio W1 / W2 or the dimensional ratio T1 / T2 exceeds 0.9, the reliability deterioration rate increases beyond 5%.

  As shown in Samples 10 to 17, when both the dimensional ratio W1 / W2 and the dimensional ratio T1 / T2 are 0.35 or more, the crack generation rate can be suppressed to less than 5%. On the other hand, as shown in the sample 18, when either the dimensional ratio W1 / W2 or the dimensional ratio T1 / T2 is less than 0.35, the crack occurrence rate increases exceeding 5%.

  Next, refer to Table 3. As shown in Samples 23 to 27, when both the dimensional ratio W1 / W2 and the dimensional ratio T1 / T2 are 0.9 or less, the reliability deterioration rate can be suppressed to less than 5%. On the other hand, as shown in Samples 19 to 22, when either the dimensional ratio W1 / W2 or the dimensional ratio T1 / T2 exceeds 0.9, the reliability deterioration rate increases beyond 5%.

  Further, as shown in Samples 19 to 26, when both the dimensional ratio W1 / W2 and the dimensional ratio T1 / T2 are set to 0.35 or more, the crack generation rate can be suppressed to less than 5%. On the other hand, as shown in sample 27, when either the dimensional ratio W1 / W2 or the dimensional ratio T1 / T2 is less than 0.35, the crack generation rate increases exceeding 5%.

  Next, refer to Table 4. As shown in Samples 33 to 36, when both the dimensional ratio W1 / W2 and the dimensional ratio T1 / T2 are 0.9 or less, the reliability deterioration rate can be suppressed to less than 5%. On the other hand, as shown in samples 28 to 32, when either the dimensional ratio W1 / W2 or the dimensional ratio T1 / T2 exceeds 0.9, the reliability deterioration rate increases beyond 5%.

  Further, as shown in Samples 28 to 35, when both the dimensional ratio W1 / W2 and the dimensional ratio T1 / T2 are set to 0.35 or more, the crack generation rate can be suppressed to less than 5%. On the other hand, as shown in the sample 36, when either the dimensional ratio W1 / W2 or the dimensional ratio T1 / T2 is less than 0.35, the crack generation rate increases by more than 5%.

  Finally, refer to Table 5. As shown in Samples 41 to 45, when both the dimensional ratio W1 / W2 and the dimensional ratio T1 / T2 are 0.9 or less, the reliability deterioration rate can be suppressed to less than 5%. On the other hand, as shown in samples 37 to 40, when either the dimensional ratio W1 / W2 or the dimensional ratio T1 / T2 exceeds 0.9, the reliability deterioration rate increases beyond 5%.

  Further, as shown in samples 37 to 44, when both the dimensional ratio W1 / W2 and the dimensional ratio T1 / T2 are 0.35 or more, the crack generation rate can be suppressed to less than 5%. On the other hand, as shown in the sample 45, when either the dimensional ratio W1 / W2 or the dimensional ratio T1 / T2 is less than 0.35, the crack generation rate increases by more than 5%.

  Therefore, from the experimental data described in Tables 1 to 5, in order to suppress both the reliability deterioration rate and the crack generation rate, 0.35 ≦≦ size ratio W1 / W2 and dimension ratio T1 / T2. It can be seen that it is preferable to satisfy W1 / W2 ≦ 0.9 and 0.35 ≦ T1 / T2 ≦ 0.9. More preferably, 0.45 ≦ W1 / W2 ≦ 0.8 and 0.45 ≦ T1 / T2 ≦ 0.8 are satisfied. Even more preferably, 0.55 ≦ W1 / W2 ≦ 0.75 and 0.55 ≦ T1 / T2 ≦ 0.75 are satisfied.

  Next, a method for manufacturing the multilayer ceramic capacitor shown in FIGS. 1 to 5 will be described.

  First, as shown in FIG. 6, the internal electrode layer 30 is formed on the surface of the first dielectric green sheet 71. The internal electrode layer 30 is formed in such a manner that it has a capacitance forming portion 301 and a lead portion 302 as seen in the one chip region Q1. In the figure, for the sake of convenience, only one chip region Q1 is shown. One chip region Q1 is a region for one monolithic ceramic capacitor, and is shown as a rectangular region defined by boundary lines 61 and 62 in the length direction L and boundary lines 63 and 64 in the width direction W.

  The first dielectric green sheet 71 is made of a dielectric paste in which a dielectric powder, a solvent, a binder, and the like are mixed, and has a constant thickness. Further, the internal electrode layer 30 can be formed by printing a conductor paste in which a conductor powder, a solvent, a binder and the like are mixed in a predetermined pattern.

  Further, unlike the first dielectric green sheet 71 shown in FIG. 6, a step absorption layer is provided in a region excluding the region where the internal electrode layer 30 is formed on the surface of the first dielectric green sheet 71. It may be formed. For example, the step absorption layer can be formed on both sides in the width direction W as seen from the capacitance forming portion 301 of the internal electrode layer 30. The step absorption layer can be formed by printing a dielectric paste having the same main component as the first dielectric green sheet 71 in a predetermined pattern.

  Next, as shown in FIG. 7, a thickness providing layer 81 is formed on the surface of the second dielectric green sheet 72. However, the internal electrode layer is not formed. The thickness providing layer 81 is formed in such a manner that it overlaps the lead portion 302 and does not overlap the capacitance forming portion 301 when viewed in one chip region Q1. Specifically, the thickness providing layer 81 is formed on both sides of the one chip region Q1 facing the length direction L.

  The second dielectric green sheet 72 is made of a dielectric paste similar to the first dielectric green sheet 71 and has a constant thickness. Further, the thickness providing layer 81 can be formed by printing a dielectric paste having the same main component as the second dielectric green sheet 72 in a predetermined pattern. The thickness of the thickness providing layer 81 is arbitrary.

  FIG. 8 is a diagram showing another pattern of the thickness-imparting layer formed on the second dielectric green sheet. In contrast to the pattern of the thickness-imparting layer shown in FIG. 7, the thickness-imparting layer 81 shown in FIG. 8 is formed not only on both sides facing the length direction L but also on both sides facing the width direction W. Has been.

  Next, as shown in FIG. 9, a first dielectric green sheet 71 having a plurality of layers (n layers) is provided, and a second dielectric is formed on the upper and lower layers of the first dielectric green sheet 71 having n layers. A sheet laminate including the green sheet 72 is produced. Specifically, the first dielectric green sheet 71 on which the internal electrode layer 30 is formed is laminated as the unit layers 911 to 91n. Further, in addition to these unit layers 911 to 91n, the second dielectric green sheet 72 on which the thickness providing layer 81 is formed is laminated as upper unit layers 921 to 92m and lower unit units 931 to 93m.

  In the production of the sheet laminate, the upper unit layers 921 to 92m are arranged such that the thickness providing layer 81 overlaps the lead portion 302 of the internal electrode layer 30 in relation to the unit layers 911 to 91n. The same applies to the lower unit layers 931 to 93m, and the lower unit layers 931 to 93m are arranged such that the thickness-imparting layer 81 overlaps the lead portion 302 of the internal electrode layer 30 in relation to the unit layers 911 to 91n. The

  Next, the obtained sheet laminate is pressed in the laminating direction T, so that the leading portion 302 of the internal electrode layer 30 is centered in the laminating direction T of the sheet laminate using the thickness of the thickness imparting layer 81. Bring Thereby, the internal structure of the dielectric substrate 1 shown in FIG. 2 is obtained.

  Next, after the pressed sheet laminate is cut into one chip region Q1 along the boundary lines 61 to 64, a process such as binder removal and firing is performed to obtain a laminated chip as shown in FIG. It is done. In FIG. 10, the same reference numerals are given to the components that are the same as those shown in FIG. 2.

  Next, as shown in FIG. 11, base films 41 and 51 are formed on the dielectric substrate 1. Specifically, the base film 41 is formed by attaching and baking a conductive paste on the end surface 11, side surface (not shown), upper surface 15 and lower surface 16 of the dielectric substrate 1 by a dip method or the like. Similarly, the base film 51 is formed by attaching and baking a conductive paste on the end face 12, the side surface (not shown), the upper surface 15 and the lower surface 16 of the dielectric substrate 1.

  Next, as shown in FIG. 12, first plating films 42 and 52 are deposited on the surfaces of the base films 41 and 51 using electroplating. Specifically, the first plating films 42 and 52 can be deposited on the surfaces of the base films 41 and 51 by immersing the dielectric substrate 1 together with the base films 41 and 51 in the plating solution 94 and energizing them.

  Thereafter, the second plating film can be deposited on the first plating film by an electroplating process similar to the electroplating process shown in FIG. Thereby, the multilayer ceramic capacitor shown in FIGS. 1 to 5 is obtained.

  In the above-described method for manufacturing a multilayer ceramic capacitor, the sheet laminate is pressed in the laminating direction T so that the lead-out portion 302 of the internal electrode layer 30 is formed in the laminating direction of the sheet laminate by using the thickness of the thickness imparting layer 81. Since the sheet stack is then cut into one chip region Q1 to produce the end face of the dielectric substrate, the internal electrode is formed on the end face 11 of the dielectric substrate 1 as shown in FIG. 31 to 3n-1 are separated from the corner portions 21 to 24. Therefore, even if the base film 41 is formed on the end face 11 of the dielectric substrate 1 as shown in FIG. 11 and then the dielectric substrate 1 is immersed in the plating solution 94 together with the base film 41 as shown in FIG. It is possible to suppress the plating solution 94 from entering 31 to 3n-1.

  In the manufacturing method of the multilayer ceramic capacitor described above, the lead-out portion 302 of the internal electrode layer 30 formed on the first dielectric green sheet 71 is varied depending on the thickness of the thickness imparting layer 81 formed on the second dielectric green sheet 72. To the center in the stacking direction T (see FIG. 9). At this time, if the lead portion 302 of the internal electrode layer 30 is extremely moved to the center in the stacking direction T, the thickness dimension T1 of the first internal electrode formation region S1 and the outer layer thickness dimension TG1 may not be adjusted. (See FIG. 4).

  Preferably, a step absorption layer is formed in a region excluding the region where the internal electrode layer 30 is formed on the surface of the first dielectric green sheet 71. According to this aspect, it is possible to adjust the degree of bringing the lead-out portion 302 of the internal electrode layer 30 to the center in the stacking direction T of the sheet stack.

  While the present invention has been described with reference to the embodiment, it is needless to say that the present invention is not limited to this embodiment, and various modifications and changes can be made within the scope of the claims.

1 is a perspective view showing an embodiment of a multilayer ceramic capacitor according to the present invention. FIG. 2 is a cross-sectional view taken along line 2-2 in FIG. It is a figure which shows the shape pattern of the internal electrode in the multilayer ceramic capacitor shown by FIG.1 and FIG.2. It is a figure which shows the end surface of a dielectric substrate along the 4-4 line of FIG. It is a figure which shows the cross section in the center part of the dielectric substrate seen in the length direction along the 5-5 line of FIG. It is a figure which shows an example of the 1st dielectric material sheet used for the manufacturing method of a multilayer ceramic capacitor. It is a figure which shows an example of the 2nd dielectric material sheet used for the manufacturing method of a multilayer ceramic capacitor. It is a figure which shows another example of the 2nd dielectric material sheet used for the manufacturing method of a multilayer ceramic capacitor. It is a figure which shows the process of producing a sheet laminated body in the manufacturing method of a multilayer ceramic capacitor. It is a figure which shows a multilayer chip in the manufacturing method of a multilayer ceramic capacitor. It is a figure which shows the process of forming a base film in the manufacturing method of a multilayer ceramic capacitor. It is a figure which shows the process of forming the 1st plating film in the manufacturing method of a multilayer ceramic capacitor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Dielectric base | substrate 31-3n Internal electrode 4, 5 External electrode 41, 51 Base film 42, 52 1st plating film 43, 53 2nd plating film

Claims (3)

  1. A multilayer ceramic capacitor including a dielectric substrate and a plurality of internal electrodes,
    The dielectric substrate has a substantially rectangular parallelepiped shape having a length direction, a width direction, and a thickness direction,
    The internal electrode is embedded in the dielectric substrate in a layered manner in the thickness direction with a space between each other, and one end is formed in such a manner as to be drawn out to the end surface in the length direction of the dielectric substrate,
    Forming a first internal electrode defined as a rectangle having a minimum dimension surrounding the internal electrode on the end face of the dielectric substrate, having two sides facing the width direction and two sides facing the thickness direction Virtualize the area,
    In the cross section parallel to the width direction and the thickness direction of the central portion of the dielectric substrate as viewed in the length direction, there are two sides opposite to the width direction and two sides opposite to the thickness direction. , Assuming a second internal electrode formation region defined as a minimum-sized rectangle surrounding the internal electrode,
    In the first internal electrode formation region and the second internal electrode formation region, the width and thickness of the first internal electrode formation region are set to W1 and T1, respectively. The width dimension and the thickness dimension are W2 and T2, respectively, and are formed to satisfy 0.35 ≦ W1 / W2 ≦ 0.9 and 0.35 ≦ T1 / T2 ≦ 0.9.
    Multilayer ceramic capacitor.
  2. A first dielectric green sheet is prepared in which the internal electrode layer is formed in a mode having a capacitance forming portion and a lead portion narrower than the capacitance forming portion as viewed in one chip region on one surface;
    There is no internal electrode layer on one side, and a thickness-imparting layer is provided in the form of a second dielectric green sheet formed in such a manner that it overlaps the lead portion and does not overlap the capacitance forming portion as seen in one chip region,
    A plurality of the first dielectric green sheets, and a sheet laminate including the second dielectric green sheets in the upper and lower layers of the plurality of first dielectric green sheets,
    By pressing the sheet laminate in the laminating direction, the lead portion of the internal electrode layer is brought to the center in the laminating direction of the sheet laminate using the thickness of the thickness providing layer,
    Then, the manufacturing method of the multilayer ceramic capacitor which cuts the said sheet laminated body into one chip area.
  3. A method for producing a multilayer ceramic capacitor according to claim 2,
    A step absorption layer is formed in a region excluding a region where the internal electrode layer is formed on the one surface of the first dielectric green sheet.
    Manufacturing method of multilayer ceramic capacitor.
JP2006267532A 2006-09-29 2006-09-29 Laminated ceramic capacitor and its manufacturing method Pending JP2008091400A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006267532A JP2008091400A (en) 2006-09-29 2006-09-29 Laminated ceramic capacitor and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006267532A JP2008091400A (en) 2006-09-29 2006-09-29 Laminated ceramic capacitor and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2008091400A true JP2008091400A (en) 2008-04-17

Family

ID=39375293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006267532A Pending JP2008091400A (en) 2006-09-29 2006-09-29 Laminated ceramic capacitor and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2008091400A (en)

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010050390A (en) * 2008-08-25 2010-03-04 Murata Mfg Co Ltd Method for manufacturing stacked coil component
JP2011165935A (en) * 2010-02-10 2011-08-25 Tdk Corp Laminated electronic component
KR101141342B1 (en) 2011-03-09 2012-05-03 삼성전기주식회사 A multilayer ceramic capacitor and a method for manufactuaring the same
JP2012099786A (en) * 2010-10-29 2012-05-24 Samsung Electro-Mechanics Co Ltd Multilayer ceramic capacitor and manufacturing method therefor
US8194390B2 (en) 2009-12-24 2012-06-05 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor and fabricating method thereof
WO2012077585A1 (en) * 2010-12-06 2012-06-14 株式会社村田製作所 Multilayer ceramic electronic component
US8259434B2 (en) 2009-12-23 2012-09-04 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor and method of fabricating the same
CN102810397A (en) * 2011-05-31 2012-12-05 三星电机株式会社 Multilayer ceramic electronic component and multilayer ceramic capacitor
JP2013089944A (en) * 2011-10-18 2013-05-13 Samsung Electro-Mechanics Co Ltd Multilayer ceramic electronic component
US20130141837A1 (en) * 2011-12-06 2013-06-06 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic part
US8465830B2 (en) 2010-06-01 2013-06-18 Murata Manufacturing Co., Ltd. Ceramic electronic component
JP2014027255A (en) * 2012-06-22 2014-02-06 Murata Mfg Co Ltd Ceramic electronic component and ceramic electronic device
US20140177127A1 (en) * 2012-12-20 2014-06-26 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component and manufacturing method thereof
JP2016136561A (en) * 2015-01-23 2016-07-28 Tdk株式会社 Multilayer capacitor
JP2017059633A (en) * 2015-09-15 2017-03-23 Tdk株式会社 Laminate electronic component
JP2018050079A (en) * 2014-01-10 2018-03-29 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic capacitor and mounting substrate for the same
KR101933426B1 (en) * 2017-12-27 2018-12-28 삼성전기 주식회사 Multilayer ceramic electronic component

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010050390A (en) * 2008-08-25 2010-03-04 Murata Mfg Co Ltd Method for manufacturing stacked coil component
US8259434B2 (en) 2009-12-23 2012-09-04 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor and method of fabricating the same
US8194390B2 (en) 2009-12-24 2012-06-05 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor and fabricating method thereof
JP2011165935A (en) * 2010-02-10 2011-08-25 Tdk Corp Laminated electronic component
US8465830B2 (en) 2010-06-01 2013-06-18 Murata Manufacturing Co., Ltd. Ceramic electronic component
JP2012099786A (en) * 2010-10-29 2012-05-24 Samsung Electro-Mechanics Co Ltd Multilayer ceramic capacitor and manufacturing method therefor
WO2012077585A1 (en) * 2010-12-06 2012-06-14 株式会社村田製作所 Multilayer ceramic electronic component
JP5477479B2 (en) * 2010-12-06 2014-04-23 株式会社村田製作所 Multilayer ceramic electronic components
JP2012191163A (en) * 2011-03-09 2012-10-04 Samsung Electro-Mechanics Co Ltd Multilayer ceramic capacitor and manufacturing method for the same
KR101141342B1 (en) 2011-03-09 2012-05-03 삼성전기주식회사 A multilayer ceramic capacitor and a method for manufactuaring the same
US9013858B2 (en) 2011-05-31 2015-04-21 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component
KR101843182B1 (en) * 2011-05-31 2018-03-28 삼성전기주식회사 Multilayer ceramic electronic component
US8422196B2 (en) 2011-05-31 2013-04-16 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component
JP2012253338A (en) * 2011-05-31 2012-12-20 Samsung Electro-Mechanics Co Ltd Multilayer ceramic electronic component
CN102810397A (en) * 2011-05-31 2012-12-05 三星电机株式会社 Multilayer ceramic electronic component and multilayer ceramic capacitor
JP2013089944A (en) * 2011-10-18 2013-05-13 Samsung Electro-Mechanics Co Ltd Multilayer ceramic electronic component
JP2013120927A (en) * 2011-12-06 2013-06-17 Samsung Electro-Mechanics Co Ltd Multilayer ceramic electronic part
US20130141837A1 (en) * 2011-12-06 2013-06-06 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic part
US9646767B2 (en) 2012-06-22 2017-05-09 Murata Manufacturing Co., Ltd. Ceramic electronic component and ceramic electronic apparatus including a split inner electrode
JP2014027255A (en) * 2012-06-22 2014-02-06 Murata Mfg Co Ltd Ceramic electronic component and ceramic electronic device
US9484153B2 (en) * 2012-12-20 2016-11-01 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component having a plurality of internal electrodes and method for manufacturing the same
US20140177127A1 (en) * 2012-12-20 2014-06-26 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component and manufacturing method thereof
JP2018050079A (en) * 2014-01-10 2018-03-29 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic capacitor and mounting substrate for the same
CN105826072A (en) * 2015-01-23 2016-08-03 Tdk株式会社 Multilayer capacitor
JP2016136561A (en) * 2015-01-23 2016-07-28 Tdk株式会社 Multilayer capacitor
US20160217927A1 (en) * 2015-01-23 2016-07-28 Tdk Corporation Multilayer capacitor
US10008329B2 (en) * 2015-01-23 2018-06-26 Tdk Corporation Multilayer capacitor having first internal electrodes and second internal electrodes alternately disposed
CN105826072B (en) * 2015-01-23 2018-11-02 Tdk株式会社 Cascade capacitor
JP2017059633A (en) * 2015-09-15 2017-03-23 Tdk株式会社 Laminate electronic component
KR101933426B1 (en) * 2017-12-27 2018-12-28 삼성전기 주식회사 Multilayer ceramic electronic component

Similar Documents

Publication Publication Date Title
KR101699388B1 (en) Multilayer ceramic capacitor
US8902564B2 (en) Multilayer ceramic electronic component
US10431379B2 (en) Method of manufacturing a multilayer ceramic capacitor
US8654504B2 (en) Monolithic ceramic electronic component
KR102076145B1 (en) Multi-layered ceramic electronic part, board for mounting the same and manufacturing method thereof
US20170103854A1 (en) Multilayer ceramic capacitor and method of manufacturing the same
KR101843190B1 (en) Ceramic electronic component and method for manufacturing the same
US8717738B2 (en) Multilayer ceramic electronic component
KR101014508B1 (en) Multilayer capacitor
JP4134675B2 (en) Multilayer electronic component and manufacturing method thereof
CN102683015B (en) Multilayer ceramic capacitor and manufacture method thereof
KR102029469B1 (en) Multilayered ceramic electronic component and fabricating method thereof
US9214283B2 (en) Multilayer capacitor and method of manufacturing same
JP5672162B2 (en) Electronic components
KR20140040547A (en) Multilayer ceramic capacitor and a method for manufactuaring the same
JP5532027B2 (en) Multilayer ceramic electronic component and manufacturing method thereof
US6829134B2 (en) Laminated ceramic electronic component and method for manufacturing the same
US8508912B2 (en) Capacitor and method for manufacturing the same
US8064187B2 (en) Monolithic ceramic electronic component
US8139342B2 (en) Laminated electronic component and method for manufacturing the same
JP5332475B2 (en) Multilayer ceramic electronic component and manufacturing method thereof
JP5271377B2 (en) Multilayer ceramic capacitor
JP5206440B2 (en) Ceramic electronic components
US8125763B2 (en) Multilayer ceramic electronic component and method for making the same
JP2005347509A (en) Laminated capacitor and its manufacturing method

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20090218

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090423

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090507

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090701

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100303