JP3538308B2 - Manufacturing method of multilayer ceramic electronic component - Google Patents

Manufacturing method of multilayer ceramic electronic component

Info

Publication number
JP3538308B2
JP3538308B2 JP03448498A JP3448498A JP3538308B2 JP 3538308 B2 JP3538308 B2 JP 3538308B2 JP 03448498 A JP03448498 A JP 03448498A JP 3448498 A JP3448498 A JP 3448498A JP 3538308 B2 JP3538308 B2 JP 3538308B2
Authority
JP
Japan
Prior art keywords
ceramic
electronic component
multilayer ceramic
metal
internal electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP03448498A
Other languages
Japanese (ja)
Other versions
JPH11233387A (en
Inventor
佳也 坂口
淳夫 長井
秀紀 倉光
和博 小松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP03448498A priority Critical patent/JP3538308B2/en
Publication of JPH11233387A publication Critical patent/JPH11233387A/en
Application granted granted Critical
Publication of JP3538308B2 publication Critical patent/JP3538308B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、例えば積層セラミ
ックコンデンサ等の積層セラミック電子部品の製造方法
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer ceramic electronic component such as a multilayer ceramic capacitor.

【0002】[0002]

【従来の技術】セラミック電子部品の一つである積層セ
ラミックコンデンサは、セラミックシート11a上に金
属ペースト12aを用いてスクリーン印刷法により内部
電極を形成したものを積層して積層体を形成し、所望の
形状に切断後焼成し、次いで外部電極を形成したもので
あった。
2. Description of the Related Art A multilayer ceramic capacitor, which is one of ceramic electronic components, is formed by laminating a ceramic sheet 11a on which internal electrodes are formed by a screen printing method using a metal paste 12a to form a laminate. After cutting into the shape of, firing was performed, and then an external electrode was formed.

【0003】[0003]

【発明が解決しようとする課題】しかしながらこの方法
によると、図3に示すようにセラミックシート11aの
金属ペースト形成部分14aと金属ペースト非形成部分
15aとで厚みが異なるために、圧着工程において金属
ペースト形成部分14aにのみ圧力が集中し、金属ペー
スト非形成部分15aの成形密度が上がらないために、
焼成するとこの部分でクラックや層間剥離が発生し易い
といった問題点を有していた。
However, according to this method, as shown in FIG. 3, the thickness of the metal paste forming portion 14a and the thickness of the metal paste non-forming portion 15a of the ceramic sheet 11a are different from each other. Since the pressure is concentrated only on the forming portion 14a and the molding density of the metal paste non-forming portion 15a does not increase,
There was a problem that cracking and delamination tended to occur in this portion when firing.

【0004】そこで本発明は、圧着時にセラミックシー
トの金属ペーストの非形成部分にも十分に圧力をかけ
て、セラミックシート間の接着を強固にすることによ
り、クラックや層間剥離のない積層セラミック電子部品
を提供することを目的とするものである。
Accordingly, the present invention provides a multilayer ceramic electronic component free from cracks and delaminations by applying sufficient pressure to a portion of a ceramic sheet where a metal paste is not formed at the time of pressing to strengthen the adhesion between the ceramic sheets. The purpose is to provide.

【0005】[0005]

【課題を解決するための手段】この目的を達成するため
に本発明の積層セラミック電子部品の製造方法は、重量
平均分子量400,000以上のポリエチレンとセラミ
ック原料を含有するセラミックシート上に薄膜形成法に
より金属膜を形成する第1の工程と、次にこの金属膜を
形成したセラミックシートを複数枚積層し、加圧し、続
いて加圧したまま加熱し前記ポリエチレンを融解して前
記セラミックシート同士の接着を強固にして積層体を得
る第2の工程と、次いで前記積層体を焼成する第3の工
程とを備え、前記セラミックシートは多孔度が30%以
上であることを特徴とするものであり、第1の工程にお
ける導電体層が薄膜形成法で形成されていることに加
え、第2の工程でのセラミックシートの多孔度が高いの
で圧着する際、導電体層が形成されている部分のセラミ
ックシートが高い圧縮率を示すため、導電体層の非形成
部分にも十分な圧力が加わるので、上記目的を達成する
ことができる。
Means for Solving the Problems] method of manufacturing a multilayer ceramic electronic component of the present invention to achieve this object, the weight
Polyethylene and ceramic having an average molecular weight of 400,000 or more
A first step of forming a metal film on a ceramic sheet containing a raw material by a thin film forming method, and then laminating a plurality of ceramic sheets on which the metal film is formed , applying pressure, and
And heat it while pressurizing to melt the polyethylene.
A second step of strengthening the adhesion between the ceramic sheets to obtain a laminated body; and a third step of firing the laminated body, wherein the ceramic sheet has a porosity of 30% or more. In addition to the fact that the conductor layer in the first step is formed by a thin film forming method, and the ceramic sheet in the second step has a high porosity, the conductor layer is formed at the time of pressure bonding. The above-mentioned object can be attained because the ceramic sheet in the portion where the conductive layer is formed has a high compression ratio, and a sufficient pressure is applied to the portion where the conductive layer is not formed.

【0006】[0006]

【発明の実施の形態】本発明の請求項1に記載の発明
は、重量平均分子量400,000以上のポリエチレン
とセラミック原料を含有するセラミックシート上に薄膜
形成法により金属膜を形成する第1の工程と、次にこの
金属膜を形成したセラミックシートを複数枚積層し、加
圧し、続いて加圧したまま加熱し前記ポリエチレンを融
解して前記セラミックシート同士の接着を強固にして
層体を得る第2の工程と、次いで前記積層体を焼成する
第3の工程とを備え、前記セラミックシートは多孔度が
30%以上であることを特徴とする積層セラミック電子
部品の製造方法であり、導電体層が薄膜であり、かつセ
ラミックシートの多孔度が高いので、第2の工程におい
て圧着する際、導電体層の非形成部分にも十分な圧力が
加わるので、クラックや層間剥離のない積層セラミック
電子部品を得ることができる。また、この導電体層は、
従来のようにワニスなどの燃焼成分が含まれていないの
で、導電体層が従来の場合と比較して緻密になり等価直
列抵抗の低い、すなわち損失の小さい積層セラミック電
子部品を得ることができる。
DETAILED DESCRIPTION OF THE INVENTION The invention according to claim 1 of the present invention relates to a polyethylene having a weight average molecular weight of 400,000 or more.
And a first step of forming a metal film on a ceramic sheet containing a ceramic raw material by a thin film forming method, and then laminating a plurality of ceramic sheets on which the metal film is formed.
And then heat while pressurizing to melt the polyethylene.
A second step of obtaining a laminated body by strengthening the adhesion between the ceramic sheets and a third step of firing the laminate, wherein the ceramic sheet has a porosity. A method for producing a multilayer ceramic electronic component characterized by being at least 30%, wherein the conductor layer is a thin film and the porosity of the ceramic sheet is high. Since a sufficient pressure is also applied to the non-formed portions, a multilayer ceramic electronic component free of cracks and delamination can be obtained. Also, this conductor layer,
Since a combustion component such as varnish is not contained unlike the conventional case, the conductor layer becomes denser than in the conventional case, and a multilayer ceramic electronic component having a low equivalent series resistance, that is, a small loss can be obtained.

【0007】請求項2に記載の発明は、第1の工程にお
いて導電体層を蒸着、スパッタリング、メッキ、静電塗
着のいずれかの薄膜形成方法を用いて形成する請求項1
に記載の積層セラミック電子部品の製造方法であり、導
電体層が薄膜であり、かつセラミックシートの多孔度が
高いので、第2の工程において圧着する際、導電体層が
形成されていない部分にも十分な圧力が加わるので、ク
ラックや層間剥離のない積層セラミック電子部品を得る
ことができる。
According to a second aspect of the present invention, in the first step, the conductive layer is formed by using any one of a thin film forming method of vapor deposition, sputtering, plating, and electrostatic coating.
Wherein the conductor layer is a thin film and the porosity of the ceramic sheet is high, so that when performing the pressure bonding in the second step, the conductor layer is formed on a portion where the conductor layer is not formed. Since sufficient pressure is applied, a multilayer ceramic electronic component free from cracks and delamination can be obtained.

【0008】[0008]

【0009】以下、本発明の一実施の形態について積層
セラミックコンデンサを例に図面を参照しながら説明す
る。
An embodiment of the present invention will be described below with reference to the drawings, taking a multilayer ceramic capacitor as an example.

【0010】(実施の形態1)図1は本実施の形態にお
ける積層セラミックコンデンサの一工程を示す断面図で
あり、1aはセラミックシート、2aはセラミックシー
ト1a上に形成した内部電極2となる金属膜、4aは金
属膜形成部分、5aは金属膜非形成部分、6は金属上
板、7は金属下板、8は金属上板6と金属下板7の間隔
を示している。また図2は一般的な積層セラミックコン
デンサの一部切欠斜視図であり、1はセラミック誘電体
層、2は内部電極、3は外部電極である。
(Embodiment 1) FIG. 1 is a cross-sectional view showing one step of a monolithic ceramic capacitor according to the present embodiment, wherein 1a is a ceramic sheet, 2a is a metal serving as an internal electrode 2 formed on the ceramic sheet 1a. Reference numeral 4a denotes a metal film forming portion, 5a denotes a metal film non-forming portion, 6 denotes a metal upper plate, 7 denotes a metal lower plate, and 8 denotes a distance between the metal upper plate 6 and the metal lower plate 7. FIG. 2 is a partially cutaway perspective view of a general multilayer ceramic capacitor, wherein 1 is a ceramic dielectric layer, 2 is an internal electrode, and 3 is an external electrode.

【0011】まず、重量平均分子量が400,000の
ポリエチレンとチタン酸バリウムを主成分とする誘電体
粉末からなるとともに多孔度が70%であるセラミック
シート1a上に、内部電極2となるニッケルからなる金
属膜2aを薄膜形成法により形成する。この薄膜形成法
としては、例えばスパッタリングを用いて金属膜2aを
所望の形状に複数形成する。この時のセラミックシート
1aの厚みは15μm、金属膜2aは0.1〜2.5μ
m程度の厚みとする。複数のセラミックシート1aを、
セラミックシート1aを挟んで金属膜2aが交互に対向
するように積重ね、仮積層体を得る。その後、この仮積
層体を金属上板6、金属下板7で挟んで、室温で一軸プ
レス機にてゲージ圧で5〜100WPaの範囲で加圧す
る。ここで金属上板6と金属下板7の仮積層体と接する
面は研磨されており、金属上板6、金属下板7面の間隔
8のばらつきは、40μm以下に制御されている。その
後仮積層体に十分な圧力が加わったことを確認して、仮
積層体の最高温度が150℃〜200℃になるまで昇温
し、積層体を得る。ここで積層体の最高温度を150℃
〜200℃としたのは、150℃程度からポリエチレン
が融解し、セラミックシート同士の接着が強固になるか
らである。200℃以下としたのは、200℃より高く
なるとポリエチレンが分解してしまい、セラミックシー
ト同士の接着に寄与しなくなるからである。その後、縦
3.2mm、横1.6mmのチップ形状に切断して、大気中
350℃でポリエチレンを除去した(脱バイ)。この脱
バイの時の温度は、ポリエチレンが積層体から除去でき
かつ金属膜2a中のニッケルの酸化が進みすぎない程度
にすることが望ましく、具体的には250〜350℃で
行うことが望ましい。その後、窒素ガスおよび水素ガス
を用いて金属膜2aの酸化が進みすぎない雰囲気を保ち
ながら、1300℃で焼成を行う。この焼成によりチタ
ン酸バリウムを主成分とするセラミック誘電体層1とニ
ッケルを主成分とする内部電極2が同時に焼結した焼結
体を得る。次いでこの焼結体の内部電極2の露出した両
端面に銅の外部電極3を焼き付け、メッキを施した後に
完成品に至る。
First, a ceramic sheet 1a having a weight average molecular weight of 400,000 and a dielectric powder containing barium titanate as a main component and having a porosity of 70% is formed of nickel serving as an internal electrode 2 on a ceramic sheet 1a. The metal film 2a is formed by a thin film forming method. In this thin film forming method, a plurality of metal films 2a are formed in a desired shape by using, for example, sputtering. At this time, the thickness of the ceramic sheet 1a is 15 μm, and the thickness of the metal film 2a is 0.1 to 2.5 μm.
m. A plurality of ceramic sheets 1a are
The metal films 2a are stacked so as to alternately face each other with the ceramic sheet 1a interposed therebetween to obtain a temporary laminate. Thereafter, the temporary laminate is sandwiched between the upper metal plate 6 and the lower metal plate 7 and is pressed at room temperature by a uniaxial press at a gauge pressure of 5 to 100 WPa. Here, the surfaces of the metal upper plate 6 and the metal lower plate 7 that are in contact with the temporary laminate are polished, and the variation in the distance 8 between the surfaces of the metal upper plate 6 and the metal lower plate 7 is controlled to 40 μm or less. Then, after confirming that sufficient pressure has been applied to the temporary laminate, the temperature of the temporary laminate is increased until the maximum temperature of the temporary laminate becomes 150 ° C. to 200 ° C. to obtain a laminate. Here, the maximum temperature of the laminated body is 150 ° C.
The reason for setting the temperature to 200 ° C. is that the polyethylene melts at about 150 ° C., and the adhesion between the ceramic sheets becomes strong. The reason why the temperature is set to 200 ° C. or lower is that if the temperature is higher than 200 ° C., the polyethylene is decomposed and does not contribute to the adhesion between the ceramic sheets. Thereafter, the chip was cut into a chip shape having a length of 3.2 mm and a width of 1.6 mm, and the polyethylene was removed at 350 ° C. in the atmosphere (debuying). It is desirable that the temperature at the time of this de-buying be such that the polyethylene can be removed from the laminate and the oxidation of the nickel in the metal film 2a does not proceed too much. Thereafter, baking is performed at 1300 ° C. using a nitrogen gas and a hydrogen gas while maintaining an atmosphere in which the oxidation of the metal film 2a does not proceed excessively. By this firing, a sintered body is obtained in which the ceramic dielectric layer 1 mainly containing barium titanate and the internal electrode 2 mainly containing nickel are sintered simultaneously. Next, copper external electrodes 3 are baked on the exposed end surfaces of the internal electrodes 2 of the sintered body, and after plating, a finished product is obtained.

【0012】(表1)は、セラミックシート1aに内部
電極2をスパッタリングで形成した本発明の積層セラミ
ックコンデンサと、セラミックシート1aに内部電極2
をスクリーン印刷で形成した比較例の積層セラミックコ
ンデンサと、従来のセラミックシートに内部電極2をス
クリーン印刷で形成した従来の積層セラミックコンデン
サの内部電極2の膜厚と静電容量不良および焼結体の構
造欠陥発生との関係について、調べた結果を示す。
Table 1 shows the laminated ceramic capacitor of the present invention in which the internal electrode 2 is formed on the ceramic sheet 1a by sputtering, and the internal electrode 2 is formed on the ceramic sheet 1a.
Is formed by screen printing, and the film thickness and capacitance of the internal electrode 2 of the conventional multilayer ceramic capacitor in which the internal electrode 2 is formed by screen printing on the conventional ceramic sheet and the internal electrode 2 are formed on the conventional ceramic sheet. The results of an investigation on the relationship with the occurrence of structural defects are shown.

【0013】[0013]

【表1】 [Table 1]

【0014】但し、いずれの積層セラミックコンデンサ
も有効層数は100層としそれぞれ100個についてま
ず静電容量不良を調べて、次に静電容量不良のないもの
について、クラックや層間剥離等の構造欠陥個数を示し
た。
However, each of the multilayer ceramic capacitors has an effective number of layers of 100, and each of the 100 capacitors is examined for capacitance failure first. Then, for those having no capacitance failure, structural defects such as cracks and delamination are observed. The number is shown.

【0015】(表1)を見ると、本発明品では内部電極
2の膜厚が0.1μm未満の場合、積層体を焼成する際
に内部電極2となるニッケルが連続した形で焼結せず不
連続になるため、所定の静電容量が得られなかった。ま
た、3.0μm以上ではセラミックシート1a同士の接
着性が十分に得られないために、焼結体に図4に示すよ
うなクラック100や層間剥離が見られた。従って内部
電極2の厚みは0.1〜2.5μmにすることが好まし
い。同様にスクリーン印刷で内部電極2を形成した比較
例品では、内部電極2の膜厚が1.5μm以下の場合、
所定の静電容量を得ることができず、3.0μm以上の
場合、構造欠陥が見られた。また従来のセラミックシー
トにスクリーン印刷で内部電極2を形成した従来品は、
内部電極2の膜厚が1.5μm以下の場合、所定の静電
容量を得ることができず、2.0μm以上の場合クラッ
クや層間剥離等の構造欠陥が見られた。従って、本発明
の積層セラミックコンデンサは、内部電極2の膜厚が
0.1〜2.5μmの広い範囲で、従来多発していたク
ラックなどの構造欠陥の発生や、内部電極の不連続性に
よる静電容量不良を抑制し、歩留まりを大幅に改善する
ことができる。このことは、さらに有効層数を増やし、
高積層化を行った場合、さらに効果がある。
According to Table 1, when the thickness of the internal electrode 2 is less than 0.1 μm in the product of the present invention, when the laminated body is fired, nickel as the internal electrode 2 is sintered in a continuous form. Therefore, a predetermined capacitance could not be obtained. Further, when the thickness is 3.0 μm or more, since the adhesiveness between the ceramic sheets 1a is not sufficiently obtained, cracks 100 and delamination as shown in FIG. 4 were observed in the sintered body. Therefore, it is preferable that the thickness of the internal electrode 2 be 0.1 to 2.5 μm. Similarly, in the comparative example product in which the internal electrode 2 is formed by screen printing, when the film thickness of the internal electrode 2 is 1.5 μm or less,
When a predetermined capacitance could not be obtained and the thickness was 3.0 μm or more, a structural defect was observed. In addition, the conventional product in which the internal electrode 2 is formed by screen printing on a conventional ceramic sheet,
When the film thickness of the internal electrode 2 was 1.5 μm or less, a predetermined capacitance could not be obtained. When the film thickness was 2.0 μm or more, structural defects such as cracks and delamination were observed. Therefore, in the multilayer ceramic capacitor of the present invention, when the film thickness of the internal electrode 2 is in a wide range of 0.1 to 2.5 μm, structural defects such as cracks, which have occurred frequently in the past, and discontinuity of the internal electrode are caused. Capacitance failure can be suppressed, and the yield can be greatly improved. This further increases the number of effective layers,
When higher stacking is performed, there is a further effect.

【0016】なお本発明においてポイントとなることを
以下に記載する。 (1)内部電極2の厚みは0.1〜2.5μmで良好な
結果が得られたが、有効層数が100層を越える場合
は、内部電極2の厚みが1.0μm以下になるようにし
て、仮積層体に一様に加圧できるようにすることが望ま
しい。
The points of the present invention will be described below. (1) Although good results were obtained when the thickness of the internal electrode 2 was 0.1 to 2.5 μm, when the number of effective layers exceeds 100, the thickness of the internal electrode 2 is reduced to 1.0 μm or less. Thus, it is desirable to uniformly press the temporary laminate.

【0017】(2)内部電極2の材料としてニッケルを
用いたが、銅などの卑金属や、またパラジウム、銀−パ
ラジウムなどの貴金属を用いてもかまわない。
(2) Nickel is used as the material of the internal electrode 2, but a base metal such as copper or a noble metal such as palladium or silver-palladium may be used.

【0018】(3)薄膜形成法は、スパッタリングを用
いたが、蒸着、メッキ、静電塗着のいずれの方法を用い
ても構わない。しかしながらメッキにより金属膜2aを
形成する場合は、メッキ液がセラミックシートに影響を
及ぼさないようにするためにも、メッキ液のpHが7付
近の中性のものを用いることが好ましい。
(3) Although the sputtering method is used for forming the thin film, any method of vapor deposition, plating, and electrostatic coating may be used. However, when the metal film 2a is formed by plating, it is preferable to use a neutral plating solution having a pH of around 7, in order to prevent the plating solution from affecting the ceramic sheet.

【0019】(4)実施の形態1においては、積層セラ
ミックコンデンサのみについて示したが、セラミックシ
ート1aを用いて製造するような積層バリスタ、積層サ
ーミスタ、積層フィルタ、フェライト部品、セラミック
多層基板などの積層セラミック電子部品の製造において
同様の効果が得られる。
(4) In the first embodiment, only the multilayer ceramic capacitor has been described. However, a multilayer varistor, a multilayer thermistor, a multilayer filter, a ferrite component, a ceramic multilayer substrate, and the like manufactured by using the ceramic sheet 1a. Similar effects can be obtained in the production of ceramic electronic components.

【0020】[0020]

【発明の効果】以上本発明によると、積層時の圧力の不
均一に起因する焼結体の構造欠陥の発生を抑制するとと
もに、導電体層が従来の場合と比較して緻密になり等価
直列抵抗の低い、すなわち静電容量損失の小さい積層セ
ラミック電子部品を得ることができる。特に高積層が要
求される積層チップコンデンサの歩留まりの向上に対し
て絶大な効果がある。
As described above, according to the present invention, it is possible to suppress the occurrence of structural defects of the sintered body due to uneven pressure during lamination, and to make the conductive layer denser than in the conventional case, and to reduce the equivalent series. A multilayer ceramic electronic component having a low resistance, that is, a small capacitance loss can be obtained. In particular, there is a remarkable effect on the improvement of the yield of the multilayer chip capacitor requiring high lamination.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施の形態における積層セラミック
コンデンサの一製造工程である圧着工程を示す断面図
FIG. 1 is a cross-sectional view showing a crimping step as one manufacturing step of a multilayer ceramic capacitor according to an embodiment of the present invention.

【図2】一般的な積層セラミックコンデンサの一部切欠
斜視図
FIG. 2 is a partially cutaway perspective view of a general multilayer ceramic capacitor.

【図3】従来の積層セラミックコンデンサの一製造工程
である圧着工程を示す断面図
FIG. 3 is a cross-sectional view showing a crimping step as one manufacturing step of a conventional multilayer ceramic capacitor.

【図4】クラックの発生した焼結体の斜視図FIG. 4 is a perspective view of a sintered body having cracks.

【符号の説明】[Explanation of symbols]

1 セラミック誘電体層 1a セラミックシート 2 内部電極 2a 金属膜 3 外部電極 1 ceramic dielectric layer 1a Ceramic sheet 2 Internal electrode 2a Metal film 3 External electrodes

───────────────────────────────────────────────────── フロントページの続き (72)発明者 倉光 秀紀 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (72)発明者 小松 和博 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (56)参考文献 特開 平8−124787(JP,A) 特開 平5−190043(JP,A) 特開 平3−273696(JP,A)   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Kurumitsu Hideki               1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric               Kiki Sangyo Co., Ltd. (72) Inventor Kazuhiro Komatsu               1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric               Kiki Sangyo Co., Ltd.                (56) References JP-A-8-124787 (JP, A)                 JP-A-5-190043 (JP, A)                 JP-A-3-273696 (JP, A)

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 重量平均分子量400,000以上のポ
リエチレンとセラミック原料を含有するセラミックシー
ト上に薄膜形成法により金属膜を形成する第1の工程
と、次にこの金属膜を形成したセラミックシートを複数
枚積層し、加圧し、続いて加圧したまま加熱し前記ポリ
エチレンを融解して前記セラミックシート同士の接着を
強固にして積層体を得る第2の工程と、次いで前記積層
体を焼成する第3の工程とを備え、前記セラミックシー
トは多孔度が30%以上であることを特徴とする積層セ
ラミック電子部品の製造方法。
Claims: 1. A polyester having a weight average molecular weight of 400,000 or more.
A first step of forming a metal film on a ceramic sheet containing ethylene and a ceramic raw material by a thin film forming method, and then laminating a plurality of ceramic sheets on which the metal film has been formed, pressing, and then pressing Heat the poly
Melting ethylene to bond the ceramic sheets together
A second step of obtaining a laminated body in the strong, then a third step of firing the laminate, the ceramic Sea
A method for manufacturing a multilayer ceramic electronic component, wherein the porosity is 30% or more.
【請求項2】 薄膜形成法は、蒸着、スパッタリング、
メッキ、静電塗着のいずれかであることを特徴とする請
求項1に記載の積層セラミック電子部品の製造方法。
2. A method for forming a thin film, comprising: vapor deposition, sputtering,
The method for manufacturing a multilayer ceramic electronic component according to claim 1, wherein the method is one of plating and electrostatic coating.
JP03448498A 1998-02-17 1998-02-17 Manufacturing method of multilayer ceramic electronic component Expired - Fee Related JP3538308B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03448498A JP3538308B2 (en) 1998-02-17 1998-02-17 Manufacturing method of multilayer ceramic electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03448498A JP3538308B2 (en) 1998-02-17 1998-02-17 Manufacturing method of multilayer ceramic electronic component

Publications (2)

Publication Number Publication Date
JPH11233387A JPH11233387A (en) 1999-08-27
JP3538308B2 true JP3538308B2 (en) 2004-06-14

Family

ID=12415531

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3538308B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5629443B2 (en) * 2009-09-04 2014-11-19 住友精密工業株式会社 Manufacturing method of ozone gas generator
JP5603581B2 (en) * 2009-09-28 2014-10-08 住友精密工業株式会社 Ozone gas generator and manufacturing method thereof

Also Published As

Publication number Publication date
JPH11233387A (en) 1999-08-27

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