JPH11338640A - Computer system and data transfer control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate hibernation processing by using a data transfer mode that matches the performance of an operational hard disk drive and executing data transfer with the hard disk drive. SOLUTION: When an event such as power switch off by a user occurs, the kind of a data transfer mode belonging to an HDD 17 is automatically discriminated before processing that saves content of a memory 3 in the HDD 17 and when the HDD 17 has a DMA mode, data transfer for memory data save is carried out in the DMA mode by using a bus master function of a bus master IDE controller 16. Then, it is possible to bring out the performance of the operational HDD 17 as much as possible and to realize the acceleration of hibernation processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system and a data transfer control method used in the computer system, and more particularly to a computer system having a hibernation function for saving the contents of a memory to a hard disk device when the power is turned off, and a high-speed hibernation function. The present invention relates to a data transfer control method for realization.

[0002]

2. Description of the Related Art In recent years, various types of portable notebook-type or sub-note-type personal computers and pocket computers such as portable information terminals have been developed.

Various types of power save modes (sleep modes) for saving power of a computer system are provided in this type of portable computer in order to extend the time during which the battery can be driven. The suspend mode is one of the sleep modes that consume the least power. That is, when the computer system is in the suspend mode, most other devices in the system are powered off, except for the main memory in which system data necessary for restarting such as the operating system and user programs is stored.

The system data saved in the main memory is the status of the CPU and the status of various peripheral LSIs immediately before the computer system is set to the suspend mode. The main memory also stores the execution state of the operating system and application programs and user data created by the application programs. The information saved in the main memory is used for restoring the work state immediately before the suspend mode.

The saving of the system data is performed by the system BI
It is executed by a suspend routine incorporated in an OS (basic input / output program). The system BIOS is for controlling hardware in the system according to a request from the operating system, and includes a device driver group for controlling various hardware devices in the system. The suspend routine of the system BIOS is started when the power of the system is turned off.
After saving the status of the CPU registers and various peripheral LSIs in the memory, the system is powered off.

[0006] Power to the main memory is maintained by a battery throughout the period when the system is powered off. Therefore, the system can be returned to the work state before the suspension at a high speed without losing the status and user data of the system.

However, if the battery capacity is reduced to a low battery state when the system is in the suspend mode, data in the main memory is lost. In this case, not only cannot the system be returned to the state before the suspension, but also the user data developed in the main memory is lost.

Therefore, recently, a hibernation mode has begun to be used as a new sleep mode instead of the suspend mode. The hibernation mode uses the CPU and various peripheral LSIs when the system power is off.
In this mode, almost all devices in the system including the main memory are powered down after the status of the main memory and the contents of the main memory are saved on the hard disk, and the power consumption can be reduced as compared with the suspend mode. Further, even if the battery capacity is reduced, the information saved in the hard disk is not lost, so that the system state can be normally restored to the state immediately before the hibernation mode. Therefore, many portable computers that are frequently used outside the office and cannot use the AC adapter implement the hibernation mode as the sleep mode.

[0009] With the recent improvement in the functions of operating systems and application programs, the memory capacity of a portable computer as a main memory is constantly increasing. As the storage capacity of the main memory increases, the time required to save the contents of the main memory to the hard disk and the time required to restore the contents of the hard disk to the main memory also increase. For this reason, in a system that uses the hibernation mode, the time required for the hibernation process, that is, the time required from the time the user turns off the power switch to the time the system is actually turned off, and the time required after the user turns on the power switch. The time required for the system state to be restored is becoming very large.

[0010] Conventionally, data transfer to and from a hard disk at the time of data saving and restoring for hibernation is always performed by PIO (Program).
(mI / O transfer) mode.

That is, in a portable computer, ATA (Enhanced IDE) is used as an interface used to connect a hard disk drive. A typical transfer mode used in the Enhanced IDE is the above-described PIO mode. In ATA, PIO modes 0 to 4 are defined, and the maximum transfer rates are different from each other. The PIO mode is a transfer mode using handshaking between the CPU and the hard disk drive, and the CPU transfers data by repeatedly accessing the I / O port of the hard disk drive directly. Therefore, the transfer rate is not high, but this transfer method is sufficient in consideration of the data transfer capability of the hard disk drive itself that requires mechanical operations such as seek operation and spindle rotation.

Recently, however, the density of hard disks has been rapidly increased, and the data transfer capability of the hard disks themselves has been greatly improved. Also, hard disk drives compatible with the UltraDMA mode have begun to be commercialized. The hard disk drive is replaceable by the user. For this reason, PI
In the conventional hibernation processing in which data transfer is performed using the O mode, there is a problem that the performance cannot be sufficiently brought out depending on the type of the used hard disk drive.

[0013]

As described above, conventionally, even in a hard disk drive that supports a high-speed transfer mode such as a DMA mode, transfer is performed in a PIO mode, and the hard disk drive in use is In some cases, there is a problem that the performance cannot be sufficiently exhibited. For this reason, especially in the hibernation process that requires large-capacity data transfer, a lot of time is required, and the time required from the time the user turns off the power switch to the time the system is actually powered off, and There is a problem that the time required from when the power switch is turned on until the system state is restored becomes very long.

The present invention has been made in view of the above circumstances, and has been made capable of executing data transfer to and from a hard disk drive using a data transfer mode suitable for the performance of the hard disk drive in use. It is an object of the present invention to provide a computer system capable of realizing high-speed processing and a data transfer control method used in the computer system.

[0015]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a computer system in which a disk drive device can be mounted and which transfers data to and from the disk drive device. Means for determining the type of data transfer mode of the disk drive by reading parameter information of the drive from the device; and one of data transfer modes of the disk drive based on the determination result. Transfer mode selection means for selecting a data transfer mode; and data transfer control means for controlling execution of data transfer to and from the disk drive device using the data transfer mode selected by the transfer mode selection means. It is characterized by doing.

In this computer system, by reading the drive parameter information from the mounted disk drive, the type of data transfer mode of the disk drive is automatically determined, and the type of data transfer mode used is determined based on the determination result. Data transfer mode to be selected. Therefore, no matter what type of disk drive device is used, the performance of the hard disk drive in use can be maximized, and the data transfer speed can be improved. .

Further, according to the present invention, when a disk control device having a bus master function is provided in a computer system, the transfer mode selecting means determines whether or not the disk drive device has a DMA transfer mode. If the disk drive has a DMA transfer mode, the DMA transfer mode is selected, and
When there is no MA transfer mode, a high-speed data transfer mode of the disk drive is selected from other transfer modes other than the DMA transfer mode. Thereby, in a computer system having a disk control device having a bus master function,
When a disk drive device that supports the DMA transfer mode is used, the data transfer mode can be automatically set to the DMA transfer mode.

According to another aspect of the present invention, there is provided a computer system in which a disk drive can be mounted and which has a function of saving the contents of a memory in the disk drive when the power is turned off. Means for determining the type of data transfer mode possessed by the disk drive by reading parameter information from the disk drive in response to the occurrence, and a data transfer mode possessed by the disk drive based on the determination result. And a data transfer mode selected by the transfer mode selecting means, and executing data transfer from the memory of the computer system to the disk drive. The contents of the memory Characterized by comprising the data transfer control means for saving the disk drives device.

In this computer system, when an event such as a power switch off by the user occurs, the type of the data transfer mode of the disk drive is automatically determined prior to the process of saving the contents of the memory to the disk drive. The data transfer for saving the memory data is executed by using the optimum data transfer mode among the data transfer modes of the disk drive device. Therefore, data can be transferred to and from the hard disk drive using a data transfer mode suitable for the performance of the hard disk drive in use, and the hibernation process can be speeded up.

According to the present invention, there is provided a computer system in which a disk drive device is configured to be mountable and executes a data save process for saving the contents of a memory in the disk drive device when the power supply is shifted to an off state.
U, a disk controller having a bus master function and capable of executing a DMA transfer between the disk drive device and the memory, and a CPU controlling the computer system in response to the occurrence of an event causing a power-off of the computer system. In addition, there is provided a parallel control means for executing data save processing by DMA transfer using the disk controller and power down processing of various devices provided in the computer system in parallel.

In this computer system, when an event such as a power switch-off by a user occurs, a CPU executes a data save process by DMA transfer and a power down process of various devices provided in the computer system in parallel. . In this case, during the DMA transfer using the disk controller,
Since the CPU is released from the data transfer processing, the CP
U resources can be allocated to power-down processing such as turning off a display controller or a display, and it is possible to reduce the time required from when a user turns off a power switch to when the system is actually turned off.

In such parallel control, for example, a processing program is prepared for each of a plurality of devices to be processed including a disk drive device, and the time required for transition from the current command processing to the next command processing is reduced. Using a counter value of each of the plurality of counters to be managed, a means is provided for detecting timing at which transition to the next command processing can be performed for each device. Invoke the corresponding control processing program in order to issue the next command for the control processing, and reset the counter value corresponding to the device to which the command was issued each time the command is issued. Can be realized by

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a computer system according to an embodiment of the present invention. This computer system is a portable personal computer of a notebook type or a sub-note type, and is composed of a computer main body and an LCD panel unit which is openably and closably attached to the computer main body. This computer has a built-in battery, and is configured to be operable with power from the built-in battery. Further, power can be supplied from an external power supply such as an AC commercial power supply via an AC adapter. When power is supplied from an external power source, the power from the external power source is used as an operating power source for the computer system. At this time, the built-in battery is automatically charged by the power from the external power supply. When the AC adapter is removed or the breaker of the AC commercial power supply is turned off, the power from the built-in battery is used as the operation power supply of the computer system.

Further, a hard disk drive (HD) having an IDE interface is provided in the computer main body.
D) 17 is detachably mounted. This HDD
Reference numeral 17 is used as secondary storage of a computer.

On the system board of this computer, a CPU 11, a host-PCI bridge 12 connecting the CPU bus 1 and the PCI bus 2, a main memory 13,
GA controller 14, PCI-ISA bridge 15,
Bus master IDE controller 16, BIOS-ROM
18, a real-time clock (RTC) 19, an embedded controller (EC) 20, a power supply controller 21, and the like.

The CPU 11 controls the operation of the entire system and executes data processing. As the CPU 11, a system management interrupt SMI (SMI; System
For example, a microprocessor “Pentium” manufactured and sold by Intel Corporation in the United States is used. In this case, the CPU 11 has the following system management function.

That is, the CPU 11 has a real mode, a protect mode, a virtual 86 mode as operation modes for executing programs such as an application program and an operating system (OS), and a system management mode (SMM; System Ma).
The system has an operation mode for realizing a system management function called a “management mode”.

The real mode is a mode in which a memory space of a maximum of 1 Mbyte can be accessed. The conversion from a logical address to a physical address is performed by an address for determining a physical address by an offset value from a base address represented by a segment register. It is done by calculation format.

On the other hand, the protect mode is a mode in which a memory space of a maximum of 4 GB can be accessed per task, and a linear address is determined by using an address mapping table called a descriptor table.
This linear address is finally converted to a physical address by paging.

As described above, different memory addressing is adopted between the protect mode and the real mode. The system management mode (SMM) is a pseudo-real mode. The address calculation format in this mode is the same as the address calculation format in the real mode, the descriptor table is not referred to, and no paging is performed. However, the SMM can access a memory space exceeding 1 Mbyte as in the protect mode.

System management interrupt (SMI; System)
m Management Interrupt) is C
When issued to the PU 11, the operation mode of the CPU 11 is:
The operation mode is switched from the real mode, the protect mode, or the virtual 86 mode to the SMM. When switching to SMM by SMI, CPU
Numeral 11 denotes a CPU status, which is the content of the CPU register at that time, and is an overlay memory SM
Save to RAM. When a return instruction (RSM instruction) is executed in the SMM, the CPU 11
The CPU status is restored from M to the CPU register, and the operation mode returns to the operation mode before the occurrence of the SMI. In the present embodiment, the SMM executes a system management program for performing a hibernation process and the like.
This hibernation routine is for setting the system state to the suspend state or the hibernation state. When the system state is set to the hibernation state, the state of the CPU 11 and various peripheral LSIs, the contents of the main memory 13 and the VRAM, etc. Is saved in a hibernation area previously secured in the storage area of the HDD 17, and then the entire system is powered off.

This hibernation routine is executed by the SMI caused by turning off the system power, that is, the power switch 2
S, which is generated when the user presses the button 2, the close detection of the LCD panel unit by the panel switch 23, or the press of the suspend button (sleep button).
Executed in response to MI.

The SMI is a kind of the non-maskable interrupt NMI, and is the highest priority interrupt having a higher priority than the normal NMI and the maskable interrupt INTR. This SM
By issuing I, the system management program can be started without depending on the environment of the running application program or the operating system.

The host-PCI bridge 12 has a built-in circuit for controlling the memory and the entire I / O in the system, and also incorporates hardware logic for controlling SMI generation. I have. The hardware logic includes an SMI generation circuit for activating the hibernation process, an SMI generation circuit based on other factors such as software SMI and I / O trap SMI, and a status register holding the SMI generation factor.

The SMI generation circuit includes a power controller 21
And the power switch 22 is turned off via the EC 20, the suspend button is pressed, or the panel open / close detection switch 23
When an event such as the LCD panel close is notified, an SMI signal for activating the hibernation process is generated. Further, the SMI signal from the SMI generating circuit is also used for notification of a wake-up event instructing return from the hibernation state. That is, when a wake-up event occurs due to turning on of the power switch 22 or opening of the LCD panel, a return process from the hibernation state to the operation state is performed.

The main memory 13 is used as a main memory of the system, that is, a system memory, and stores an operating system, an application program to be processed, user data created by the application program, and the like. This main memory 1
Reference numeral 3 is realized by a semiconductor memory such as a DRAM. The above-mentioned SMRAM (System Managerem)
The “ent RAM” is a storage space allocated to a part of the physical memory constituting the main memory 13, and becomes accessible only when an SMI signal is input to the CPU 11 by mapping a memory address. Where SMRAM
Is not fixed, and SM
It is possible to change to any location in the 4 Gbyte space by a register called BASE. SMBASE
The register cannot be accessed unless it is in SMM.

When the CPU 11 shifts to the SMM, C
PU status, ie the CPU when the SMI was generated
Eleven registers and the like are saved in the SMRAM in a stack format. This SMRAM includes a BIOS-ROM 18
For invoking the system management program. This instruction is the first instruction to be executed when the CPU 11 enters the SMM, and the execution of this instruction transfers control to the system management program.

The BIOS-ROM 18 stores the system BIOS.
This is for storing S (Basic I / O System), and is constituted by a flash memory so that a program can be rewritten. System BI
The OS is a systematized function execution routine for accessing various hardware in the system, and is configured to operate in a real mode.

The system BIOS includes an IRT routine executed when the system is powered on, and a group of BIOS drivers for controlling various hardware. Each BIOS driver includes a plurality of function execution routine groups corresponding to the functions for providing a plurality of functions for hardware control to an operating system or an application program.

The BIOS-ROM 18 has an SMI
Such as the handler and the hibernation routine described above
A system management program executed in the SMM is also stored. The SMI handler is for activating various SMI service routines according to the cause of the SMI. When the SMI due to the power-off operation occurs, the SMI handler activates the hibernation routine and the SMI due to other factors occurs. If it is, the SMI corresponding to the factor
Invoke the service routine.

A hibernation area is secured in a part of the storage area of the HDD 17. The hibernation area is secured by the system BIOS when the HDD 17 is initialized and tested by the IRT, and the other storage areas except the hibernation area are released to the OS. A physically continuous area is assigned to the hibernation area.

The RTC 19 is a clock module and has a CMOS memory backed up by a unique battery. Various system configuration information including information designating a power-up mode is set in the CMOS memory.

The EC 20 is a controller for controlling the additional functions of the system. The EC 20 has a heat control function for controlling the rotation of the cooling fan according to the temperature around the CPU and the like. It has an LED / beep sound control function for notifying the user by beep-on, a power supply sequence control function for controlling on / off of the system power supply in cooperation with the power supply controller 21, a power supply status notification function, and the like.
The power status notification function monitors the occurrence of an event that is a trigger for the hibernation process and the resume process of the system BIOS in cooperation with the power controller 21.
When an event occurs, it is sent to system B using SMI, etc.
This is a function of notifying the IOS. Even in the hibernation state, the EC 20 and the power controller 21
Is supplied with operating power, and the functions of the EC 20 are effective.

The EC 20 has an I / O port for communication with the system BIOS. System BIOS
Reads / writes the configuration register in the EC 20 via the I / O port to set the type of an event to be monitored and notified, and to read the status indicating the event that has occurred. be able to. Communication between the EC 20 and the power supply controller 21 is performed via an I ² C bus.

For example, when there is a change in the remaining amount of the battery, the power supply controller 19 controls the EC 18 via the I ² C bus.
Directly rewrite the configuration register of E
When the configuration register is rewritten, the C18 notifies the system BIOS of this as an event.

The VGA controller 14 is for controlling an LCD used as a display monitor of the system, and displays screen data drawn in the VRAM on the LCD in the LCD panel unit.

The bus master IDE controller 16 controls an IDE device (here, the HDD 17) mounted on the computer main body.
It supports a bus master function capable of executing a DMA transfer between the device and the main memory 13. This bus master function executes a bus cycle for data transfer by itself in response to a command from the CPU 11, and performs data transfer between the IDE device and the main memory 13 with the CPU load reduced compared to the PIO mode. Transfer can be performed at high speed.

In this embodiment, the bus master, that is, the DM
When a hard disk drive compatible with the A transfer mode is mounted, data transfer for hibernation processing is performed in the DMA transfer mode by using the bus master function. If a hard disk drive that does not support the DMA transfer mode is installed, the fastest transfer mode among the transfer modes supported by the hard disk drive is automatically selected. A transfer is performed. Which transfer mode the hard disk drive supports is automatically determined by reading parameter information indicating the transfer mode from the hard disk drive.

Next, a series of operations from the occurrence of the SMI to the start of the hibernation routine will be described with reference to FIG. The power switch 22 is turned off by the user during the operation of the system, or
When the panel open / close switch 23 detects that the CD panel unit is closed, the power controller 21
Indicates that a power-off factor has occurred via the EC20.
Notify the I generation circuit. In response to this notification, an SMI signal is generated from the SMI generation circuit and supplied to the CPU 11.

When the SMI signal is input to the CPU 11,
The CPU 11 is switched from the operation mode at that time to the SMM. When entering the SMM, the CPU 11 first sets the SM
A predetermined memory address is mapped to the RAM. This makes the SMRAM accessible.

The SMRAM stores a CPU state storage area and a hardware status (HW status) for storing a status relating to hardware other than the CPU.
A storage area is provided, and the BIOS-RO
A jump code for designating the M18 SMI handler as an interrupt destination is set. As mentioned above, B
The IOS-ROM 18 includes a system B including an IRT routine, an SMI handler, a hibernation routine, a resume routine, and a plurality of BIOS drivers.
The IOS is stored.

Next, the CPU 11 sends the contents of the various registers of the CPU 11 when the SMI is input, the CPU status (or context) to the SMR.
It is saved in a stack format in the CPU state storage area of the AM. Then, the CPU 11 fetches the start address code of the SMM, that is, the jump code set in the SMRAM, and executes the SMI handler of the BIOS-ROM 18 specified by the jump code. The processing so far is performed by the CPU 11 itself, that is, the CPU 1
This is executed by one microprogram.

The SMI handler called by the execution of the jump code checks the cause of the SMI to determine the cause of the SMI. In this process, the SMI status information set in the SMI status register is referred to.
SM caused by power off, etc., which causes a suspend
If I, the SMI handler is the BIOS-ROM 18
Request execution of the hibernation routine.
Thereby, the hibernation routine is executed in the SMM, and the hibernation process is started.

FIG. 3 shows a hibernation processing method according to this embodiment. When the power switch is turned off, the panel is closed, or the suspend button is pressed,
The hibernation routine of the system BIOS is activated, and the following processing is performed for suspending the system.

First, the hibernation routine saves the system status such as the register of the CPU 11 and the status of various peripheral LSIs in the main memory 13 (step S101). Next, an HDD transfer mode determination process for determining a data transfer mode with the HDD 17 is performed (step S102). This H
In the DD transfer mode determination processing, first, the drive parameter information stored therein is read from the HDD 17, and the type of transfer mode supported by the HDD 17 is determined. Then, among the transfer modes supported by the HDD 17, the optimum transfer mode that allows the fastest transfer is selected. Specifically, the transfer mode to be used is determined by the processing in FIG.

As shown in FIG. 4, first, the HDD 17 reads / writes data based on the drive parameter information.
It is determined whether or not the Write Multiple command is supported (step S301). Rea
The d / Write Multiple command is a command capable of collectively specifying read / write for a plurality of sectors. If the Read / Write Multiple command is not supported, read / write is specified in sector units for HDD access. Read / W
A data transfer mode using a write Sector command is used. Next, it is determined whether DMA is supported based on the HDD drive parameters read out earlier (step S302). If not supported, Read / Write M is used for HDD access.
Use the multiple command. Read / Wri
te Sector command, Read / Write
Both of the Multiple commands are commands used in the PIO mode.

Next, it is determined from the previously read HDD drive parameters whether Ultra DMA is supported (step S303). If it is not supported, DMA access is required for HDD access.
Use the Write command. If supported, use the Ultra DMA Read / Write command. In this way, the transfer mode used for HDD access, specifically, the type of command is determined. If the IDE controller is not compatible with the bus master, only step S301 needs to be performed, and the presence or absence of the support of the DMA mode and the processing of detecting the supported DMA mode in steps S302 and S303 are unnecessary.

Thereafter, the hibernation routine is executed by H
The data save process to the DD and the power down process of various devices provided in the computer system are executed in parallel. These processes are executed by a plurality of subroutines prepared for each device, and the main routine in the hibernation routine executes a process of switching the command processing by these subroutines.
That is, in the control processing of each device, commands are sequentially issued, but each time a command is issued, an I / O wait occurs. Therefore, the service routine is switched so that a command issuing process to another device can be performed while waiting for the I / O.

Here, the HDD data saving process (step S201) and the I / O control process 1 (step S20)
2), I / O control processing 2 (step S203),.
A subroutine is prepared corresponding to each of the O control processing N (step S204), and the main routine uses a counter value (timer value) prepared for each device to switch to a device that can shift to the next command processing. The corresponding subroutine is activated to execute the next command processing (step S103). Then, when all the processes including the HDD data transfer process are completed (step S104),
A command to instruct system power off is issued to the EC 20 (step S105). This gives E
All devices (including the main memory) except the C20 and the power supply controller 21 are powered off, and the system state becomes a hibernation state.

As a subroutine for executing the HDD data saving process, as shown in FIG. 5, Read / Write
Read / WriteSector processing routine # 1 for performing data transfer control using Sector command
Read / WriteM for controlling data transfer using a Read / Write Multiple command
multiple processing routine # 2 and DMA Read
D for performing data transfer control using the / Write command
MA Read / Write processing routine # 3 and UL
An UltraDMA processing routine # 4 for performing data transfer control using a tra DMA Read / Write command is prepared, and a processing routine corresponding to the transfer mode determined in step S102 in FIG. 3 is called and executed.

Next, referring to FIGS. 6 and 7, the processing of a plurality of devices for hibernation is performed in parallel using the comparison result between the counter value prepared for each device and the counter value of the system counter. The operation in the case of proceeding will be described.

FIG. 6 is a flowchart showing the relationship between the main routine and the subroutine of the hibernation routine. Here, it is assumed that the hibernation routine includes a main routine and three subroutines A, B, and C. Subroutine A is, for example, V
This is for powering down an I / O device # 1 such as a GA controller or an LCD, and is started in response to a subroutine call from a main routine. The subroutine B is for saving memory data in the HDD 17, and is started in response to a subroutine call from the main routine. The subroutine C is for performing power-down processing of a communication I / O device # 2 such as a USB or a modem, and is started in response to a subroutine call from the main routine.

The main routine includes I / O device # 1,
The counter values of the software counters (I / O counter 1, HDD counter, I / O counter 2) prepared corresponding to the HDD and I / O device # 2 are sequentially compared with the current counter value of the system counter. By comparison, a device that can be shifted to the next command processing is determined. Then, a subroutine corresponding to the device is called.

The time required for the corresponding device to execute the current command processing, that is, the time during which the next command processing can be started is set in each software counter.
For setting the counter value for each software counter,
This is executed by a subroutine for controlling a device corresponding to the software counter. Until the subroutine is started, the counter value for each software counter is 0, that is, the command processing can be started at any time.

First, it is checked whether or not the system current value is equal to or greater than the value of the I / O counter 1 (step S40).
1) If the system current value is equal to or larger than the counter value of the I / O counter 1, the subroutine A is called. If the system current value is smaller than the counter value of the I / O counter 1, check the HDD counter value. Will be migrated.

Immediately after the power is turned on, since the counter value of the I / O counter 1 is the initial value 0, the system current value is larger than the counter value of the I / O counter 1. Therefore, the I / O control processing 1 is executed by the subroutine A.

In subroutine A, first, the status of the command processing for the I / O command issued in the previous subroutine A is checked, and then the next command for powering down the I / O device 1 is issued. Done. Next, the counter value of the I / O counter 1 is updated.

Here, “current system current value”
+ N ”is set in the I / O counter 1. "N"
Indicates the minimum time (interval value) until the I / O device finishes processing corresponding to the command issued this time and can receive the next command. This time is predetermined for each command.

When the updating of the counter value of the I / O counter 1 is completed, the process returns to the main routine. In the main routine, it is checked whether the system current value is equal to or larger than the HDD counter value (step S40).
2) If the system current value is equal to or larger than the HDD counter value, the subroutine B is called to check the status of the previous transfer command processing, issue the next transfer command,
HDD data transfer control processing such as resetting of the DD counter is performed.

When returning from the subroutine B to the main routine, it is checked whether the system current value is equal to or greater than the counter value of the I / O counter 2 (step S4).
03), if the system current value is the counter value of the I / O counter 2, the subroutine C is called to check the status of the previous command processing, issue the next command,
Processing such as resetting of the counter value of the I / O counter 2 is performed.

By using the counter value of each device in this manner, the timing at which the processing can shift to the next command processing is detected for each device, and the processing for each device is advanced accordingly.

As the HDD transfer mode, DMA Rea
d / Write command or Ultra DMA Rea
When the DMA mode using the d / Write command is used, since the DMA transfer itself from the memory 13 to the HDD 17 is controlled by the bus master IDE controller 16, the time required for each command processing of the subroutine B is shortened. Meanwhile, serve routines A and C
C for power down processing of other I / O devices
PU resources can be allocated, and the entire hibernation process can be speeded up.

As described above, in this embodiment, when an event such as a power switch-off by the user occurs, the type of data transfer mode of the HDD 17 is automatically set prior to the process of saving the contents of the memory 13 to the HDD 17. It is determined, and data transfer for memory data save is executed using the most suitable data transfer mode among the data transfer modes of the HDD 17. Therefore, data can be transferred to and from the HDD 17 using a data transfer mode that matches the performance of the HDD 17 in use, and the hibernation process can be speeded up.

The same processing is performed in the return processing from the hibernation processing state, and the data transfer from the HDD 17 to the memory 13 is executed in the optimum transfer mode. Further, when HDD access is performed via the system BIOS, even when an ordinary file is accessed from an application or the OS, the H is set to the optimum transfer mode.
Data transfer to and from the DD 17 can be performed.

[0075]

As described above, according to the present invention,
Using the data transfer mode suitable for the performance of the hard disk drive in use, data can be transferred to and from the hard disk drive, and the performance of the hard disk drive in use can be maximized. Particularly, the hibernation process can be speeded up by automatically using the DMA mode.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is an exemplary view for explaining a hibernation routine activation processing operation according to the embodiment;

FIG. 3 is a flowchart illustrating a procedure of a hibernation process according to the embodiment.

FIG. 4 is an exemplary flowchart showing the procedure of an HDD transfer mode determination process executed in the hibernation process of the embodiment.

FIG. 5 is an exemplary view showing a configuration of an HDD data save processing routine included in a hibernation routine used in the embodiment.

FIG. 6 is a flowchart illustrating an example of a parallel control process according to a hibernation routine used in the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... CPU 12 ... Host-PCI bridge 13 ... Main memory 16 ... Bus master IDE controller 17 ... HDD 18 ... BIOS-ROM 20 ... EC

Claims (7)

[Claims] 1. A computer system in which a disk drive device is configured to be mountable and transfers data to and from the disk drive device, wherein by reading parameter information of the drive device from the disk drive device, the disk drive Means for determining the type of data transfer mode possessed by the device; transfer mode selecting means for selecting one data transfer mode from the data transfer modes possessed by the disk drive device based on the determination result; A computer system comprising: a data transfer control unit that controls execution of data transfer with the disk drive device using a data transfer mode selected by the unit. 2. When a disk control device having a bus master function is provided in the computer system, the transfer mode selecting means determines whether the disk drive device has a DMA transfer mode, and Drive device is DMA
If it has a transfer mode, it selects that DMA transfer mode.
2. The computer system according to claim 1, wherein a high-speed data transfer mode of said disk drive device is selected from among other transfer modes other than the A transfer mode. 3. The data transfer control means includes: first data transfer control means for controlling execution of data transfer between the disk drive device and a memory of the computer system using a DMA transfer mode; And a second data transfer control means for controlling execution of data transfer to and from the disk drive device using a data transfer mode other than the first data transfer mode. The data transfer control means corresponding to the data transfer mode selected by the transfer mode selection means is configured to be used for executing the data transfer. Or the computer system according to 2. 4. A computer system in which a disk drive device is configured to be mountable and has a function of saving the contents of a memory in the disk drive device when the power supply is turned off, responds to the occurrence of an event causing a power off. Means for determining the type of data transfer mode of the disk drive by reading parameter information of the drive from the disk drive, and a data transfer mode of the disk drive based on the determination result. Transfer mode selecting means for selecting one data transfer mode from among the following; and executing data transfer from the memory of the computer system to the disk drive device using the data transfer mode selected by the transfer mode selecting means. The contents of the memory A computer system comprising: data transfer control means for saving data in the disk drive device. 5. A data transfer control method for use in a computer system in which a disk drive device is configured to be mountable and transfers data to and from the disk drive device, the method comprising: By reading the parameter information, the type of the data transfer mode of the disk drive is determined, and one data transfer mode is selected from the data transfer modes of the disk drive based on the determination result. A data transfer control method comprising controlling execution of data transfer with the disk drive device using a selected data transfer mode. 6. A disk control device having a bus master function is provided in the computer system, and it is determined whether or not the disk drive device has a DMA transfer mode. In this case, the execution of data transfer with the disk drive device is controlled using the DMA mode,
When there is no transfer mode, execution of data transfer with the disk drive device is controlled using a high-speed data transfer mode among other transfer modes other than the DMA transfer mode. The data transfer control method according to claim 5. 7. A data transfer control method used to save the contents of a memory of a computer system to a disk drive device when the power of the computer system is turned off, wherein the data transfer control method responds to occurrence of an event causing a power off. By reading the parameter information of the disk drive from the disk drive, the type of the data transfer mode of the disk drive is determined, and the data transfer mode of the disk drive is determined based on the determination result. One data transfer mode is selected, and data is transferred from the memory of the computer system to the disk drive using the selected data transfer mode, and the contents of the memory are saved in the disk drive. Data transfer characterized by the following: Your way.