JPH11194846A - Computer system and its system state control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To carry out a dynamic transition between sleep states such as a suspend state and a hibernation state according to changes of the power supply state of a computer. SOLUTION: A built-in controller EC 18 detects the low-battery state of an internal battery 20 or the stop of supply from an external power source 21 if such state occurs in a suspend period and informs a system BIOS of that as a wake-up event. After the contents of a main memory 13 are saved in a hibernation area on an HDD 15, th system power source is turned off and the system state is shifted from the suspend state to the hibernation state. Consequently, new system state control is actualized which never loses information even in the low-battery state and restorer the system state speedily.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system and a system state control method thereof, and more particularly to a computer system having an operating state, an off state, and a sleep state in between as operating states, and a system for switching the system state. It relates to a state control method.

[0002]

2. Description of the Related Art In recent years, various types of portable notebook-type or sub-note-type personal computers and pocket computers such as portable information terminals have been developed.

Such a portable computer is provided with various sleep modes for saving the power of the computer system in order to extend the time during which the battery can be driven. The suspend mode is one of the sleep modes that consume the least power. That is, when the computer system is in the suspend mode, except for the main memory in which system data necessary for restarting the operating system and user programs are stored,
Most other devices in the system are powered off.

The system data saved in the main memory is the status of the CPU and the status of various peripheral LSIs immediately before the computer system is set to the suspend mode. The main memory also stores the execution state of the operating system and application programs and user data created by the application programs. The information saved in the main memory is used for restoring the work state immediately before the suspend mode.

The saving of the system data is performed by the system BI
It is executed by a suspend routine incorporated in an OS (basic input / output program). The system BIOS is for controlling hardware in the system according to a request from the operating system, and includes a device driver group for controlling various hardware devices in the system. The suspend routine of the system BIOS is started when the power of the system is turned off.
After saving the PU registers and the status of various peripheral LSIs in the memory, the system is powered off.

[0006] Power to the main memory is maintained by a battery throughout the period when the system is powered off. Therefore, the system can be returned to the work state before the suspension at a high speed without losing the status and user data of the system.

However, if the battery capacity is reduced to a low battery state when the system is in the suspend mode, data in the main memory is lost. In this case, not only cannot the system be returned to the state before the suspension, but also the user data developed in the main memory is lost.

Therefore, recently, a hibernation mode has begun to be used as a new sleep mode instead of the suspend mode. The hibernation mode uses the CPU and various peripheral LSIs when the system power is off.
This is a mode in which all devices in the system are powered down after saving the status of the main memory and the contents of the main memory on the hard disk, and can reduce power consumption compared to the suspend mode. Further, even if the battery capacity is reduced, the information saved in the hard disk is not lost, so that the system state can be normally restored to the state immediately before the hibernation mode. Therefore, many portable computers that are frequently used outside the office and cannot use the AC adapter implement the hibernation mode as the sleep mode.

[0009] With the recent improvement in the functions of operating systems and application programs, the memory capacity of a portable computer as a main memory is constantly increasing. As the storage capacity of the main memory increases, the time required to save the contents of the main memory to the hard disk and the time required to restore the contents of the hard disk to the main memory also increase. For this reason, in a system that uses the hibernation mode, the time required for the hibernation process, that is, the time required from the time the user turns off the power switch to the time the system is actually turned off, and the time required after the user turns on the power switch. The time required for the system state to be restored is becoming very large.

Therefore, recently, a new power saving function has been demanded in which information is not lost even by a low battery and a system state can be restored at a high speed.

On the other hand, recently, an ACPI specification (Advanced Coding) for centrally managing power management of a computer by an operating system has been proposed.
nfiguration and Power Int
(surface specification) is attracting attention.

In the ACPI specification, a plurality of sleep states are specified as an intermediate system state in addition to an operation state and a stop state.

[0013] That is, the ACPI specifications are S0 to S5.
Up to the system state. S0 is an operating state (that is, a state in which the system is turned on and software is running), S5 is an off state (that is, a state in which execution of all software is finished and the system is turned off), S1 to S4 are intermediate states (called a sleep state, that is, a state in which the operation is stopped while the execution state of the software up to immediately before is held).

At S1, the contents (context) of the entire system (CPU, system memory, each chipset, etc.)
In addition, their power sources are maintained, and the power consumption during sleep is maximum, but it is possible to return to S0 at high speed. In other words, it is the "shallowest" sleep state. However, in a battery-powered state of a notebook-type personal computer or the like, a shallow sleep state cannot be naturally maintained for a long time.

S2 is different from S1 in that the CPU and the system cache are turned off (the contents thereof are lost). The required power consumption is reduced accordingly.

In S3, only the power supply of the system memory (and some chipsets) is held. That is, only the contents of the system memory (and some chip sets) are held. The required power consumption is further reduced, and the sleep state can be maintained for a long time in the battery driven state.

In S4, all contents of the system memory and the like are stored in a non-volatile storage device such as a hard disk, and the power of the system is all turned off. Power consumption during sleep is minimum (equivalent to the state of S5), but it takes the longest time to return to S0. That is, it is the deepest sleep state.

When returning from S2 to S4 to S0,
The lost contents in the system are stored before transition to each sleep state in advance, and are restored based on them, so that the software can continuously operate after returning from S0.

The magnitude relation of the power consumption of each system state and the magnitude of the return time to S0 are as follows.

Power consumption; S0>S1>S2>S3>S4> S5 Return time: S1 <S2 <S3 <S4 <S5 However, in the current ACPI specification, the sleep state (S1
To S4) and the operation state (S0),
No transition between sleep states, for example from S1 to S3, is planned. Also, no consideration is given to a mechanism for changing the depth of the sleep state according to a change in the power supply state during the sleep state. Therefore, even in the system of the ACPI specification,
External power supply status (for example, AC adapter insertion / removal)
It is not possible to take an appropriate sleep state that minimizes the consumption of the battery in response to a change in the battery power. Alternatively, when the battery enters a low battery state (a state in which the current sleep state cannot be continued) in the light sleep state, it is not possible to make a transition to a deeper sleep state.

For an ACPI user, S1
To S4 are collectively the state of one G1. When moving from G0 to G1, a request such as "I want to reduce power consumption as much as possible" can be expressed to the operating system in an abstract form called a user policy. On the other hand, ACP
When shifting from G0 to G1, the I-OS determines which state (S1 to S4) in G1 to shift with reference to the user policy. After once moving to any one of S1 to S4, other than moving to S0 is not allowed.

That is, even a skilled user who has sufficient knowledge of the plurality of sleep states defined in the ACPI specification and is familiar with the advantages and disadvantages of each of the plurality of sleep states, It is not possible to make detailed settings for the transition conditions that cause the transition of.

[0023]

As described above, conventionally, one of the suspend mode and the hibernation mode is implemented in a system as a sleep mode. When the suspend mode is used, the system state is restored. Although it can be performed at high speed, there is a problem that it causes problems such as information loss due to a low battery, and there is a problem that using the hibernation mode does not cause information loss due to a low battery, but it takes time to recover the system state. Was.

Also, in a system of the ACPI specification, dynamic transition between sleep states cannot be performed.
In addition, there is no function provided for a user to set or change a transition condition between sleep states.

The present invention has been made in view of the above circumstances, and a computer capable of realizing a new system state control capable of restoring a system state at high speed without losing information even by a low battery. It is an object to provide a system and a system state control method thereof.

Another object of the present invention is to enable the depth of the sleep state to be dynamically switched according to a change in the power supply state during the sleep state, and to always set the system state to the optimum sleep state. It is to provide a computer system and a system state control method that can be set.

Still another object of the present invention is to provide a computer system and a system state control method capable of setting a transition condition between a plurality of sleep states in detail and easily.

[0028]

In order to solve the above-mentioned problems, the present invention provides an operation state, an off state, and a sleep state intermediate between the operation state and the off state. In a computer system having a suspend state in which information is saved in a memory and a minimum power supply required for backing up the contents of the memory is required, a transition to a sleep state with lower power consumption than the suspend state is required. An event occurrence detecting means for detecting whether or not an event has occurred; and, when the occurrence of the event is detected during a period in which the computer system is in the suspend state, the content of the memory in the suspend state is stored in a secondary storage device. And means for turning off the system power supply.

In this computer system, as a sleep mode which is an intermediate system state between the operation state and the off state, a suspend mode capable of returning to the operation state at a high speed is used. Is performed, the state is shifted from the operation state to the suspend state. Further, during the suspend state, for example, detection of a low battery, removal of an AC adapter, a stop of the supply of external power due to a power failure, and the like,
When an event such as the occurrence of an alarm indicating the elapse of a certain period of time occurs, the entire system is powered off after the contents of the memory in the suspended state are saved to a nonvolatile secondary storage device such as a hard disk, The system state automatically transitions from the suspend state to the hibernation state. Therefore, unless such an event is generated during the suspended state, the system state can be returned to the operating state at high speed, and even if a low battery or the like occurs during the suspended state, loss of information is prevented. It becomes possible.

Further, according to the present invention, information necessary for restoring a working state is saved in a memory and the contents of the memory are backed up as an operating state, an off state, and a sleep state intermediate between the operating state and the off state. A computer system having a suspend state in which a minimum power supply required for performing the operation is performed, and a hibernation state in which the contents of the memory are saved in a secondary storage device and a system power is turned off. Upon transition to the sleep state, the system state of the computer system is set to one of the suspend state and the hibernation state based on environment setting information indicating which of the suspend state and the hibernation state is used as the sleep state. Means for setting the An event occurrence detection means for detecting the occurrence of an event requiring a transition to Nation state, when the computer system is the occurrence of the event is detected in a period which is the suspend state,
Means for saving the contents of the memory in the suspend state to the secondary storage device and transitioning a system state of the computer system from the suspend state to the hibernation state.

In this computer system, both the suspend mode and the hibernation mode are prepared as the sleep mode, and the user can freely select which to use in the sleep mode according to the use environment of the computer. Can be. When the suspend mode is selected as the sleep mode, the system state is automatically shifted from the suspend state to the hibernation state on condition that an event such as a low battery occurs, as described above. Therefore, the suspend mode and the hibernation mode can be selectively used as needed, and even when the suspend mode is used, it is possible to prevent inadvertent loss of information.

Further, according to the present invention, in a computer system having an operating state, an off state, and a plurality of sleep states intermediate between them, a means for detecting a change in a power supply state to the computer system, and When a change in the power supply state is detected during a period of any one of the plurality of sleep states, the sleep state of the computer system is changed according to the change in the power supply state. And sleep state transition means for transitioning between the two.

According to this computer system, when a change in the power supply state occurs while the computer system is in the sleep state, the sleep state is dynamically switched based on the changed power supply state, and the sleep state is changed. The depth of the state is changed.

Therefore, for example, it is assumed that a user who uses an ACPI notebook PC in an office (that is, drives an AC adapter) returns the PC to the S1 state when returning to the office. Thereafter, assuming that the last returnee drops the office power breaker and returns, the user's PC will be maintained in the S1 state by battery operation. However, it may not have battery power until the next morning. Also, the user may want to carry his PC with him the next day, so he wants to minimize battery power consumption. Therefore, when the system detects that the external power supply from the AC adapter has stopped, the state automatically transitions from the S1 state to the S3 state. Thereby, the power consumption of the battery is suppressed. Then, the next morning, when the first employee turns on the power breaker, the system detects that the external power supply from the AC adapter has been restarted, and returns to the S1 state again. The user can simply resume use from S1 state (return to S0) without knowing that he was in S3 state at night. In other words, it takes a considerable time to return from the S3 state, but without making the user aware of it,
It is available to the user in the shortest time.

As described above, by realizing a mechanism for automatically performing the transition between the sleep states according to the change in the power supply state, a trade-off between the reduction of the system startup time from the sleep state and the power saving during the sleep. Can be optimized.

The transition between the sleep states can be performed in both directions, that is, the transition from the light sleep state to the deep sleep state and the transition from the deep sleep state to the light sleep state.

Furthermore, not only the transition between the two sleep states, but also the sleep state can be transitioned stepwise according to a change in the power supply state between a plurality of sleep states.

Further, instead of immediately switching the sleep state when a change in the power supply state is detected,
It is preferable that the sleep state is switched after a certain period has elapsed, and that the sleep state is not switched when the power supply state returns to the original state before the change until the certain period elapses. .

The present invention also relates to a computer system having an operating state, an off state, and a plurality of sleep states between the operating state and the off state. State control means for controlling any one of the states, and a program for operating the CPU so as to cause a state of a system controlled by the state control means to transition between the plurality of sleep states. It is characterized by doing.

With such a configuration, transition between a plurality of sleep states can be realized by software without complicating hardware or the like.

The present invention is also a computer system having an operating state, an off state, and a plurality of sleep states between the operating state and the off state, wherein a transition causing a transition between the plurality of sleep states is provided. It is characterized by comprising selecting means for selecting a condition, and state transition controlling means for executing transition between the plurality of sleep states according to the transition condition selected by the selecting means.

According to the present invention, since the user can arbitrarily select a transition condition for causing a transition between a plurality of sleep states, sufficient knowledge of the plurality of sleep states defined in the ACPI specification can be obtained. The skilled user can make a desired setting in detail according to the use or the like.

[0043]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
1 shows a configuration of a computer system according to the embodiment. This computer system is a portable personal computer of a notebook type or a sub-note type, and is composed of a computer main body and an LCD panel unit which is openably and closably attached to the computer main body. This computer has a built-in battery 20, and is configured to be operable with power from the built-in battery 20. AC
Power can also be supplied from an external power supply 21 such as an AC commercial power supply via an adapter. When power is supplied from the external power supply 21, the power from the external power supply 21 is used as an operation power supply of the computer system.
At this time, charging of the built-in battery 20 is automatically performed by the electric power from the external power supply 21. When the AC adapter is removed or the breaker of the AC commercial power supply is turned off, the power from the built-in battery 20 is used as the operation power supply of the computer system.

On the system board of this computer, a system bus 10, a CPU 11, a system controller 12, a main memory 13, a BIOS-ROM 14, a magnetic disk device (HDD) 15, a real-time clock (RTC) 16, a keyboard controller (KBC) 1
7. Embedded controller (EC; Embedded)
Controller 18, a power supply controller 19,
VGA controller 22, video RAM (VRAM) 2
3 and so on.

The CPU 11 controls the operation of the entire system and executes data processing. As the CPU 11, a system management interrupt SMI (SMI; System
For example, a Pentium microprocessor manufactured and sold by Intel Corporation in the United States is used. In this case, the CPU 11 has the following system management function.

That is, the CPU 11 has a real mode, a protect mode, a virtual 86 mode as operation modes for executing programs such as an application program and an operating system (OS), and a system management mode (SMM; System Ma).
The system has an operation mode for realizing a system management function called a “management mode”.

The real mode is a mode in which a memory space of a maximum of 1 Mbyte can be accessed. The conversion from a logical address to a physical address is performed by an address for determining a physical address by an offset value from a base address represented by a segment register. This is done according to the calculation format.

On the other hand, the protect mode is a mode in which a maximum of 4 GB of memory space can be accessed per task, and a linear address is determined using an address mapping table called a descriptor table.
This linear address is finally converted to a physical address by paging.

As described above, different memory addressing is adopted between the protect mode and the real mode.

The system management mode (SMM) is a pseudo-real mode. The address calculation format in this mode is the same as the address calculation format in the real mode. The descriptor table is not referred to and no paging is performed. However, the SMM can access a memory space exceeding 1 Mbyte as in the protect mode.

System management interrupt (SMI; System)
m Management Interrupt) is C
When issued to the PU 11, the operation mode of the CPU 11 is:
The operation mode is switched from the real mode, the protect mode, or the virtual 86 mode to the SMM. When switching to SMM by SMI, CPU
Numeral 11 saves the CPU status, which is the content of the CPU register at that time, in the SMRAM 13A. Also, SMM
When a return instruction (RSM instruction) is executed in
U11 is CPU from SMRAM13A to CPU register
The status is restored, and the operation mode returns to the operation mode before the occurrence of the SMI. In the present embodiment, a system management program for performing a suspend / hibernation routine or the like is executed in the SMM. This suspend / hibernation routine is for setting the system state to the suspend state or the hibernation state. When the system state is set to the suspend state, the state of the CPU 11 and various peripheral LSIs and the contents of the VRAM 23 are mainly used. After saving in the memory 13, most of the devices other than the main memory 13 are powered off. When the system state is set to the hibernation state, the states of the CPU 11 and various peripheral LSIs, the main memory 13 and the VR
After the contents of the AM 23 are saved in the hibernation area secured in advance in the storage area of the HDD 15, the entire system is powered off.

This suspend / hibernation routine is caused by the SMI caused by turning off the system power, that is, the depression of the power switch 181 or the detection that the LCD panel unit is closed, or the depression of the suspend button (sleep button). S generated
Executed in response to MI.

The SMI is a kind of the non-maskable interrupt NMI, and is the highest priority interrupt having a higher priority than the normal NMI and the maskable interrupt INTR. This SM
By issuing I, the system management program can be started without depending on the environment of the running application program or the operating system.

The system controller 12 controls the entire memory and I / O in the system, and incorporates hardware logic for controlling SMI generation. The hardware logic includes an SMI generation circuit 121 for activating a suspend / hibernation process as shown in FIG.
Generation circuits 122 and 123, SMI status register 1
24, and an OR circuit 125.

The SMI generation circuit 121 turns off the power switch 18 via the power controller 19 and EC 18,
When an event such as pressing of the suspend button or closing of the LCD panel by the panel open / close detection switch 182 is notified, an SMI signal for activating a suspend / hibernation process is generated. Further, the SMI signal from the SMI generating circuit 121 is also used for notification of a wake-up event instructing return from the suspended state. The wake-up event includes turning on the power switch 181, opening the LCD panel, detecting the low battery state of the built-in battery 20, stopping the supply of power from the external power supply 21 due to disconnection or power failure of the AC adapter or turning off the breaker, and suspend state. , There is an alarm by the RTC 16 indicating that a predetermined time has elapsed. The wake-up event starts the resume processing routine of the system BIOS. The cause of the wake-up event is one of detection of a low battery state, stop of power supply from the external power supply 21, and an alarm by the RTC 16. In this case, the system BIOS saves the entire contents of the main memory 13 in the hibernation area of the HDD during the resume processing, and changes the system state from the suspend state to the hibernation state. As described above, among the causes of the wake-up event, regarding the detection of the low battery state, the stop of the power supply from the external power supply 21 and the alarm by the RTC 16, the sleep mode automatic transition processing for transitioning the system state from the suspend state to the hibernation state Is used as an event for activating. Also, the wake-up event occurs when the power switch 18
If it is ON or the LCD panel is open, the process of returning from the current sleep state set to either the suspend state or the hibernation state to the operating state is performed as usual.

SMI generating circuits 122, 1 due to other factors
23 is a software SMI, a global standby SMI, a local standby SMI, an external input S
MI or the like is generated.

The OR circuit 125 is connected to the SMI generation circuit 12
When any of 1, 122 and 123 generates an SMI signal, the SMI signal is supplied to the CPU 11. These S
Each of the MI generation circuits 121, 122, and 123 has a CPU
Keep the SMI signal in the active state until 11 leaves the SMM. For this reason, when another SMI signal is generated during the SMI processing for a certain SMI signal, C
After leaving the SMM corresponding to the first SMI signal, the PU 11 shifts to the SMM again by the SMI signal generated during the SMI processing.

The SMI status register 124 stores the SM
This is for holding status data indicating the cause of I generation, and holds the output of each of the SMI generation circuits 121, 122, and 123.

The main memory 13 is used as a main memory of the system, that is, a system memory, and stores an operating system, an application program to be processed, user data created by the application program, and the like. This main memory 1
Reference numeral 3 is realized by a semiconductor memory such as a DRAM. SMRAM (System Management)
The RAM (RAM) 13A is a storage space allocated to a part of the physical memory constituting the main memory 13, and can be accessed by mapping a memory address only when an SMI signal is input to the CPU 11. Where SMRAM
Is not fixed, and SM
It is possible to change to any location in the 4 Gbyte space by a register called BASE. SMBASE
The register cannot be accessed unless it is in SMM.

When the CPU 11 shifts to the SMM, C
PU status, ie the CPU when the SMI was generated
Eleven registers and the like are saved in the SMRAM 13A in a stack format. The SMRAM 13A has a BIOS
-Instructions for calling the system management program in the ROM 14 are stored. This instruction is sent by the CPU 11
This is the first instruction executed when entering the MM, and the execution of this instruction transfers control to the system management program.

The BIOS-ROM 14 stores the system BIOS.
This is for storing S (Basic I / O System), and is constituted by a flash memory so that a program can be rewritten. System BI
The OS is a systematized function execution routine for accessing various hardware in the system, and is configured to operate in a real mode.

The system BIOS includes an IRT routine executed when the system is powered on, and a group of BIOS drivers for controlling various hardware. Each BIOS driver includes a plurality of function execution routine groups corresponding to the functions for providing a plurality of functions for hardware control to an operating system or an application program.

The BIOS-ROM 14 has an SMI
A system management program executed in the SMM, such as a handler and the above-described suspend / hibernation routine, is also stored. The SMI handler is for activating various SMI service routines according to the cause of the SMI. When an SMI due to a power-off operation occurs, the SMI handler activates a suspend / hibernation routine, and the SMI due to other factors is activated. When an error occurs, an SMI service routine corresponding to the cause is activated.

The HDD 15 is used as a secondary storage device of the system, and a hibernation area is secured in a part of the storage area as shown in the figure. Hibernation area is HDD15 by IRT
Is initialized and tested by the system BIOS, and other storage areas except the hibernation area are released to the OS. A physically continuous area is assigned to the hibernation area.

The RTC 16 is a clock module, and a CMOS memory 161 backed up by a unique battery.
have. In the CMOS memory 161, system configuration information including information for selecting a boot mode, a resume mode, and a hibernation mode as a power-up mode, a resume / hibernation status flag, and the like are set.

Here, the boot mode is a mode in which a bootstrap process for starting an operating system is started when the system is powered on. The resume mode is a mode in which a suspend process is executed when the system is suspended due to power-off or the like, the system status is saved in the main memory 13, the system state is set to the suspended state, and the main memory 13 is reset when the system is powered on. In this mode, the contents are restored to the CPU or the like.

In the hibernation mode, the hibernation process is executed at the time of suspending due to power-off or the like, the contents of the main memory 13 are saved in the HDD, the system state is set to the hibernation state, and
This mode restores the contents of the HDD to the original memory and CPU when the system is powered on.

As described above, in the system of this embodiment,
Two sleep modes, a suspend state and a hibernation state, are provided as an intermediate system state between the operating state and the off state, and the user can freely select which sleep mode to use by setting or changing the system configuration information. Can be selected.

The resume / hibernation status flag indicates whether the current system state is the suspend state or the hibernation state. When the suspend process is completed, the resume / hibernation status flag has a value indicating the completion of the suspend. When the hibernation process is completed and when the sleep mode automatic transition process from the suspend mode to the hibernation mode is completed, the resume / hibernation status flag is set to a value indicating the completion of the hibernation.

The keyboard controller 17 controls the keyboard 171 and a pointing device 172 such as a pointing stick or a mouse. The keyboard controller 17 has a key code corresponding to a pressed key, relative coordinate data pointed to, and a click operation of a mouse button. To the CPU 11.

The EC 18 is a controller for controlling the additional functions of the system. The EC 18 is a heat control function for controlling the rotation of the cooling fan in accordance with the temperature around the CPU and the like. It has an LED / beep sound control function for notifying the user by beep-on, a power supply sequence control function for controlling on / off of the system power supply in cooperation with the power supply controller 19, and a power supply status notification function. The power status notification function monitors the occurrence of an event that causes a suspend / hibernation process or a resume process of the system BIOS to occur in cooperation with the power controller 19, and notifies the system BIOS of the occurrence of the event using an SMI or the like. That is the function. EC18 in both suspend / hibernation state
The operating power is supplied to the power controller 19 and the power controller 19, and each function of the EC 18 is effective.

The EC 18 has an I / O port for communication with the system BIOS. System BIOS
Reads / writes the configuration register in the EC 18 via the I / O port to set the type of event to be monitored and notified, and to read the status indicating the event that has occurred. be able to.

Communication between the EC 18 and the power supply controller 19 is performed via an I ² C bus. For example, if there is a remaining battery capacity change, the power supply controller 19 is I ² C
The configuration register of the EC 18 is directly rewritten via the bus. When the configuration register is rewritten, the EC 18 notifies the system BIOS of this as an event.

The power supply controller 19 controls a power supply circuit to supply power to each unit in the system, and has a built-in one-chip microcomputer. The power supply controller 19 controls the supply and cutoff of power in response to an on / off operation of the power switch 191, a panel opening / closing operation, and the like, and detects a state change such as a remaining battery capacity and an AC adapter connection. To the EC 18 via the I ² C bus.

The VGA controller 22 controls the LCD 24 used as a display monitor of the system, and displays the screen data drawn on the VRAM 23 on the LCD 24 in the LCD panel unit.

Hereinafter, the suspend / characteristic of the present invention will be described.
The hibernation process will be specifically described.

First, a series of operations from the occurrence of the SMI to the start of the suspend / hibernation routine will be described with reference to FIG.

The power switch 181 is turned off by the user during the operation of the system, or
When the panel open / close switch 182 detects that the CD panel unit is closed, the power controller 1
8 indicates that the power-off factor has occurred,
Notify 1. In response to this notification, the SMI generation circuit 1
21 generates an SMI signal, which is supplied to the CPU 11.

When the SMI signal is input to the CPU 11,
The CPU 11 is switched from the operation mode at that time to the SMM. When entering the SMM, the CPU 11 first sets the SM
A predetermined memory address is mapped to the RAM 13A. Thereby, the SMRAM 13A becomes accessible.

The SMRAM 13A has a CPU state storage area, a hardware status (HW status) storage area for storing a status relating to hardware other than the CPU, and the like.
-A jump code that specifies the SMI handler of the ROM 14 as an interrupt destination is set. As described above, the BIOS-ROM 14 stores the IRT routine and the SM
I handler, suspend / hibernation routine,
A resume BIOS and a system BIOS including a plurality of BIOS driver groups are stored.

Next, the CPU 11 sends the contents of the various registers of the CPU 11 when the SMI is input, to the CPU status (or context).
It is saved in a stack state in the CPU state storage area of the AM 13A. Then, the CPU 11 fetches the code of the start address of the SMM, that is, the jump code set in the SMRAM 13A, and executes the SMI handler of the BIOS-ROM 14 specified by the jump code. The processing so far is executed by the CPU 11 itself, that is, by a microprogram of the CPU 11.

The SMI handler called by the execution of the jump code checks the cause of the SMI occurrence to determine the cause of the SMI. In this process, the SMI status information set in the SMI status register 124 is referred to.
SM caused by power off, etc., which causes a suspend
If I, the SMI handler is the BIOS-ROM 14
Request to execute the suspend / hibernation routine. Accordingly, the suspend / hibernation routine is executed in the SMM, and either the suspend process or the hibernation process is started depending on whether the setting of the power-up mode by the user is the suspend mode or the hibernation mode.

Also, when the system state is in the suspended state, the SM caused by the occurrence of the wake-up event
When I is generated, a resume processing routine of the system BIOS is executed, and a return from the suspended state to the operating state or an automatic transition from the suspended state to the hibernation state is performed. As described above, the automatic transition from the suspend state to the hibernation state is performed because the wake-up event
This is the case of detecting a low battery, detecting removal of an AC adapter, or generating an RTC alarm indicating that a certain period of time has elapsed since shifting to the suspend mode.

FIG. 3A shows a state transition of the system according to the present embodiment.

As described above, in the system according to the present embodiment, power is supplied to all devices, an operation state in which various programs can be executed, execution of all software is completed, and the power of the entire system is turned off. The power-off state includes a suspended state and a hibernation state, which are intermediate system states between the operation state and the off state.

The transition from the operating state to the suspend state or the hibernation state is performed by turning off the power switch,
This is performed by closing the D panel, pressing the suspend button, or the like. Whether to transition to the suspend state or the hibernation state is determined by whether the setting of the power-up mode is the resume mode or the hibernation mode, and if the resume mode, the transition from the operation state to the suspend state,
In the case of the hibernation mode, the state shifts from the operation state to the suspend state.

Further, during the suspend state, events such as detection of a low battery state, stop of power supply from the external power supply 21, and an RTC alarm indicating that a predetermined time has elapsed since the transition to the suspend state are issued. Then, the system state automatically transitions from the suspend state to the hibernation state. In this transition, the system state is actually returned from the suspended state to the operating state once the system is powered on by the power supply controller 19. Then, after passing through this operation state, the state transits to the hibernation state. However, in the operation state in the process of the automatic transition, only the system BIOS is executed, and no OS or application program is executed.

FIG. 3B is an example of a setup screen for setting the operating environment of the computer system. On the setup screen, an item (Power) for allowing the user to select the power-up mode is described.
upMode) is provided, and when this is selected,
A selection window as shown is displayed, and one of a boot mode (Boot), a resume mode (Resume), and a hibernation mode (Hibernation) can be selected. The selected power-up mode information is stored in the CMOS memory.

FIG. 4 shows a state transition of the system state when a low battery is detected during the period in which the system state is set to the suspend state when the resume mode is selected as the power-up mode. It is specifically shown.

(1) When the power switch is turned off, the panel is closed, and the suspend button is turned on, the system state is changed from the operating state to the suspend state.

(2) If a low battery is detected during the suspend state, the system is temporarily woken up from the suspend state to the operating state.

(3) If the cause of the wake-up event is a low battery, the system state is transited to the hibernation state.

(4) Thereafter, when the system is powered on by a power switch on, panel open, or the like, the system returns from the hibernation state to the operation state. In this case, by restoring the contents of the HDD to the CPU or main memory, the work state immediately before the transition to the suspend state (1) is restored.

Next, with reference to the flowcharts of FIGS. 5 to 7, a process of shifting from the operating state to the suspend / hibernation state, an automatic transition process from the suspend state to the hibernation state, and a suspending process executed by the system BIOS. The process of returning from the / hibernation state will be described.

FIG. 5 is a flowchart showing a procedure of a transition process from the operation state to the suspend / hibernation state executed by the system BIOS.

When the power switch is turned off, the panel is closed, and the suspend button is pressed, the system BIO
The suspend / hibernation routine of S is started, and the suspend process is started (step S11).
Then, first, the suspend / hibernation routine saves the system status such as the register of the CPU 11 and the status of various peripheral LSIs in the main memory 13 (step S12). Next, it is checked with reference to the CMOS whether the current power-up mode setting is the resume mode or the hibernation mode (step S13).

In the hibernation mode, the suspend / hibernation routine saves the contents of the main memory 13 in the hibernation area of the HDD 15 (step S14), while in the resume mode, the processing in step S14 is skipped.

Thereafter, depending on whether the setting of the power-up mode is the resume mode or the hibernation mode (step S15), the processing branches as follows.

That is, in the case of the resume mode,
In the suspend / hibernation routine, first, wake-up factors (low battery, RTC alarm, AC adapter off, etc.) that require automatic transition from the suspend state to the hibernation state are set in the configuration register of the EC 18 (step S1).
6) A command for instructing the EC 18 to shift to the suspend state is issued (step S17). As a result, all devices other than the main memory 13 (E
The power is turned off except for the C18 and the power supply controller 19, and the system state becomes a suspend state. In the process of shifting to the suspend state, the resume / hibernation flag of the CMOS is set to indicate "suspend process completed".

On the other hand, if the setting of the power-up mode is the hibernation mode, the suspend / hibernation routine does not set the wake-up factor for the automatic transition such as the low battery or the AC adapter off. A command to instruct system power off is issued (step S18). This gives E
All the devices (including the main memory) except the C18 and the power supply controller 19 are powered off, and the system state is in the hibernation state. In the process of shifting to the hibernation state, the resume / hibernation flag of the CMOS is set to a value indicating “hibernation complete”.

FIG. 6 is a flowchart showing a procedure of an automatic transition process from the suspend state to the hibernation state executed by the system BIOS.

When the system is woken up (system power-on) by an event from the EC 18 during the suspend period, the resume process of the system BIOS is started (step S21). In this resume process,
A process of restoring the contents of the register of the CPU 11 from the contents of the main memory 13 is performed (step S22). After this, EC
The cause of the wake-up event is checked by referring to the 18 configuration registers.
Wake-up factors that require automatic transition from the suspend state to the hibernation state (low battery, RT
It is determined whether the wake-up is due to a C alarm, AC adapter off, etc. (steps S23, S2)
4).

If the system is powered on due to a factor other than a wake-up factor that requires an automatic transition from the suspend state to the hibernation state, the system returns to the work state immediately before the suspend by a normal resume process (step S25). ).

On the other hand, if the power is turned on due to a factor set as a wake-up factor that requires an automatic transition from the suspend state to the hibernation state, the hibernation process is started and the main memory 13 in which the system state is saved. Is saved in the HDD 15, the system is powered off (step S26). As a result, the system state changes from the suspend state to the hibernation state. In the transition processing to the hibernation state, the resume / hibernation flag of the CMOS is set to a value indicating “hibernation complete”.

FIG. 7 is a flowchart showing a process of returning from the suspend / hibernation state executed by the system BIOS.

In the resume recovery process executed when the system is powered on by turning on the power or opening the panel, first, the current power-up mode setting is checked, and if the system is in the boot mode, the OS is started. Is started (YES in step S31). If it is not the boot mode, it is checked whether the current state is the suspend state or the hibernation state based on the suspend / hibernation flag.

If it is in the suspend state (step S32)
NO), a resume process for restoring the contents of the main memory and restoring the system status to the original state is performed.

On the other hand, if it is in the hibernation state (YES in step S32), the contents of the HDD are restored to the memory and various registers after the initialization of each device (steps S33 and S34), and the state before the sleep, that is, the sleep state is restored. The work state before the transition to the state is restored (step S35).

As described above, in the first embodiment, when an event such as a low battery, a supply stop of the external power supply, or an alarm indicating the elapse of a predetermined time occurs during the suspend state, the event is automatically performed. A transition is made from the suspend state to the hibernation state. Therefore,
Even in the case of using the suspend mode in which the return to the operation state is fast, it is possible to prevent the loss of information due to a low battery or the like.

Here, the cause of the wake-up event for the automatic transition from the suspend state to the hibernation state has been described in terms of the low battery, the stop of the supply of the external power, and the occurrence of an alarm indicating the elapse of a predetermined time. It is also possible to use a dedicated button for instructing the automatic transition, a specific key combination on the keyboard, or the like as a wake-up factor.

Further, when the cause of the automatic transition is canceled by connecting the AC adapter after the transition from the suspend state to the hibernation state, it is possible to return from the hibernation state to the suspend state again. is there. This can be realized in the same procedure as in the transition process from the suspend state to the hibernation state by setting the wake-up factor for automatically returning from the hibernation state to the suspend state in the EC 18.

When returning from the hibernation state or the suspend state, it is not always necessary to restore the display screen before shifting to the suspend state, and the display may be switched to an initial screen such as a menu screen at the time of return. good. In this case, VRAM backup or H
Saving to the DD is not particularly necessary.

(Second Embodiment) FIG. 8 shows a second embodiment of the present invention.
2 illustrates a relationship between software and hardware of the computer system according to the embodiment. This computer system is a notebook-type personal computer that can be driven by a battery. In this computer system, ACPI, an architecture for power management defined by three companies, Toshiba, Intel, and Microsoft, is mounted. In ACPI, power management of various hardware on the motherboard is all directly managed and controlled by an operating system (ACPI-OS) 320.

The ACPI-OS 320, as shown in FIG.
Kernel 321, device driver 322, ACPI driver 323 and power management system software 32
4 is provided. The device driver 322 is a standard interface for power management, and includes a driver (class driver) for managing each device, a driver (bus driver) for managing a bus (such as a PCI bus or USB), and a WDM (Windows Driver). M
odel), and a device driver compliant with the device. The ACPI driver 323 is an ACPI compatible B
IOS 350, ACPI table 360 and ACPI
The power of hardware is controlled by using the register 37. In the ACPI table 360, an interface to hardware is defined, and an ASL (ACPI control met) which can be executed by the operating system.
The characteristics of each piece of hardware are described using a language called a “source source language”. That is, the ACPI-OS 320 uses the ACPI machine language (AML; ACPI control method M).
ASL has an interpreter, and ASL is compiled into AML code and ACP
It is stored in the I table 360. Actual hardware power management is performed using the ACPI register 37 corresponding to the device. The power management system software 324 is configured from the system code of the ACPI-OS 320 and executes a task for power management.

FIG. 9 is a diagram showing a hardware configuration of a computer system according to the second embodiment.

This computer system has a built-in battery 37, and is operable by power from the built-in battery 37. Also, power can be supplied from an external power supply 38 such as an AC commercial power supply via an AC adapter. When power is supplied from the external power supply 38, the power from the external power supply 38 is used as an operation power supply of the computer system. At this time, the power from the external power
Charging is also performed automatically. When the AC adapter is removed or the breaker of the AC commercial power supply is turned off, the power from the built-in battery 37 is used as the operating power supply for the computer system.

The system shown in FIG. 9 comprises a CPU 31, a system controller 32, a system memory 33, a BIOS-R
The OM 34 includes a hard disk drive 35, an embedded controller (EC) 36, and the like.

The CPU 31 controls the operation of the entire system.
ACPI-OS320 and ACPI compatible BIOS3
Execute a program such as 50.

The system controller 32 is a gate array for controlling a memory and I / O in the system. In this case, a power management event (Power Management Event) is transmitted to the ACPI-OS 320.
t: An interrupt signal SCI (System Control I) used to notify the PME.
event / status register (GP_REG) 321 that controls the occurrence of
ACP used for power management by OS 320
An I register 322 is provided.

The system memory 33 stores the ACPI-OS3
20, an application program 330 to be processed;
And a main memory for storing user data created by the application program 330 including utilities.

The BIOS-ROM 34 stores the system BIOS.
S is stored in the flash memory so that the program can be rewritten. The system BIOS is configured to operate in the real mode. The system BIOS includes a BIOS-IRT routine executed at the time of system boot, a BIOS driver for controlling various I / O devices, and an SM-BIOS for performing ACPI-compliant power management in the SMM.

The hard disk drive 35 is
The PI-OS 320, application programs 330 including utilities, and data and files processed by the CPU 31 are stored.

Embedded Controller (EC; Embedded)
The ded controller 36 has a function of controlling a power supply circuit to supply power to each unit in the system, monitoring a change in power supply state, and notifying the change as a power management event.

Embedded Controller (EC; Embedded)
The function of monitoring the power supply state by the dedicated controller 36 is also performed during the sleep state.

The power management event includes the low battery state of the battery 37 and recovery from the low battery state, and the external power supply 38 includes a change in the state of starting / stopping the supply.

That is, power-related events such as start / stop of power supply from the external power supply 38 (AC adapter ON / OFF) and a warning (low battery) indicating that the remaining capacity of the built-in battery 37 is low are as follows. The embedded controller 36 detects the signal, collects it into a POWER_PME signal, and notifies the system controller 32 of the occurrence of a power-related event. As described above, the system controller 32 has an event / status register called GP_REG 321. One bit in the event / status register is set by POWER_PME.

GP_REG 321 is ACPI-OS 32
0 to SCI (System Control Inte
(rrupt) A register that collects the factors that transmit an interrupt. When any of these bits is set, the system controller 32 generates an SCI interrupt signal. Further, the SCI signal is mapped to one of the IRQ interrupt signals, and finally the CPU requests the interrupt request as an interrupt request.
31 (that is, the ACPI-OS 320). G
The function and structure of P_REG 321 and the SCI signal
Since the method of allocating to the Q channel and how the ACPI-OS 320 receives an event due to the occurrence of an interrupt, that is, the means of transmitting the event occurrence to the ACPI-OS 320 is a technique known in the ACPI specification, a detailed description will be given here. Omitted.

FIG. 10 shows hardware logic for detecting and notifying a power management event in the system according to the present embodiment.

FIG. 10 is drawn based on a notation widely used for notation of logic required by the ACPI specification. That is, an X mark enclosed by a square indicates a flip-flop (register) that is set to “1” by hardware due to the occurrence of an event cause and is reset (“0”) by writing “1” by the ACPI-OS 320. The ACPI-OS 320 can read the value (status) of the flip-flop. This is used by the ACPI-OS 320 to obtain information on event occurrence. The circled X indicates an enable register that controls the valid / invalid of the corresponding event. A
When the CPI-OS writes “1” into the enable register and the flip-flop is set by the occurrence of the corresponding event factor, the corresponding AND gate (41)
Or 42) becomes "1" (that is, an event occurs). The plurality of events are combined into one event (here, described as a POWER_PME signal) by an OR gate (43), and input to an upper event / status register. In this example, only the external power state event and the battery state event which are targets of the present embodiment are described as event causes, but other event causes may be included.

GP_REG is the uppermost event / status register as described above, and is directly connected to ACPI-O.
Accessed from S320. A plurality of events in GP_REG are combined into one event by an OR gate (45), and the SCI # signal (generally active Lo)
(w is written in negative polarity). That is, the SCI interrupt is sent to the ACPI-OS 320
Will receive. Note that, in this example, a signal combined into one event as POWER_PME is input to GP_REG, but each event factor may be directly input directly to GP_REG. Or POW
The ER_PME may enter the GP_REG via further multi-stage event / status registers.

For reference, the logic (the logic up to the generation of POWER_PME) written on the left side of GP_REG may be actually realized by hardware or realized by software (for example, a program in an embedded controller). May be described). These registers are not directly accessed from the ACPI_OS 320, but are AML (ACPI control met).
The access is made indirectly via an interpreted language called "hod Machine Language" code. Since the AML code is described in detail in the ACPI specification, the description is omitted here. Note that, in the present embodiment, until the POWER_PME signal is created, it is realized by software in the embedded controller 36. The process from generation of the POWER_PME signal to generation of the SCI signal is realized by the system controller 32.

In FIG. 10, as described above, an event caused by a change in the state of the external power supply 38 and an event caused by a change in the state of the battery 37 are described above. The current state can be known from a status register provided in the system controller 32, for example. For example, regarding an event resulting from a state change of the external power supply 38,
When the power supply from the AC adapter is started (ON) or stopped (OFF), the same event cause is reported to the upper level. Apart from this, the current power supply state from the AC adapter can be read. It has become. Of course, in this case, the ON event and the OFF event may be transmitted to the higher order using two independent sets of event / status registers, or the polarity of the event factor signal may be selected, and the polarity may be set each time an event occurs. May be realized by inverting (toggle). Since there are a plurality of known techniques, they may be appropriately selected. The same applies to an event resulting from a change in the state of the battery.

The mechanism of transmitting an event to the ACPI-OS 320 as an SCI interrupt upon occurrence of an event is as described above. However, when the PC is partially or entirely turned off in the sleep state, the event is generated. Is detected by the embedded controller 36, the power is first turned on at a minimum required for the operation of the ACPI-OS 320, and then the ACPI-OS 320 is transmitted to the ACPI-OS 320 via the system controller 32. However, when the event is disabled by the enable register of the corresponding event, nothing happens even if the event factor occurs. That is, in that state, the sleep state is maintained.

FIG. 11 shows a state transition diagram of the system state used in this embodiment.

From the user's point of view, the global system states (G0, G1, G
Only 2) is the only known state of the system. G0
Is equal to S0 and G2 is equal to S5. All sleep states (S1 to S4) appear to the user as one G1 state. However, in the present embodiment, S2 is not implemented to simplify the description. According to the ACPI specification, the system only needs to support any one or more sleep states. Which sleep state is supported / not supported is at the discretion of the system designer.

In G1, the sleep state to be actually taken is determined by the ACPI-OS 320 based on the user policy and the OS policy. The user policy is represented by an abstract expression such as “I want to shorten the sleep recovery time” or “I want to make the battery last longer”, and conveys the user's desire to the ACPI-OS 320. O
The S policy is a policy determined by the ACPI-OS 320 itself. For example, a user such as "it seems to be infrequently used by the user", "often driven by a battery", "device xx is in an idle state", etc. Can be determined based on the usage status of the device and the status of the device. ACPI-OS32
0 means that these policies are comprehensively determined and one sleep state is finally selected. Note that the methods of giving, expressing, and determining each policy described above are merely examples, and other methods may be used.

The transition condition between G0 and G1, which is described as "sleep button or the like" in this state transition diagram, is known in the ACPI specification. That is, for example, when the user presses the sleep button (replacement with the power button or request by software, for example, clicking on the sleep icon in the screen with the mouse is also permitted),
Alternatively, a case is shown in which the ACPI-OS 320 transitions to the sleep state by detecting that the PC is in the idle state for a certain period of time. Which sleep state to transition to is determined by the above policy. Although not shown, for example, in the S1 state, after the idle state has passed for a certain period of time, a lower sleep state (for example, S3)
You can also transition to Similarly, the transition condition between G0 and G2, which is described as "power button etc." in this state transition diagram, is also known in the ACPI specification. Although not shown, a transition from G1 to G2 (generally called a shutdown) may occur. This is because, for example, a policy is set to automatically shut down after the sleep state has continued for a certain period of time, or S1 when the battery is operated in a system that does not support S4.
The shutdown is performed when it becomes difficult to continue the G1 state, for example, when the battery becomes low in the third to third states.

The transition between the sleep states (S1 to S4) is actually performed once via S0.

An example of the state transition control in this embodiment will be described.

It is assumed that the user sets the PC to the sleep state (G1 for the user) when returning home or leaving the seat. A
The CPI-OS 320 determines based on various policies, for example, “Currently, external power is supplied by an AC adapter (that is, power consumption during sleep is not so noticeable), and the user expects that the next startup is early. It is assumed that the PC is shifted to the S1 state by the determination of "Yes."

By the way, in the state S1, the external power supply is cut off (shown as "AC adapter OFF" in the figure), and
If the generation of the SCI interrupt due to the event cause is enabled in advance, the embedded controller 36
Is ACPI-OS32 via POWER_PME
Send an SCI interrupt request to 0. ACPI-OS32
0 knows that this has cut off the external power supply,
The next operation is determined based on the policy, and in this example, S3
Transition to. That is, the power to unnecessary parts is turned off by the embedded controller 36. As a result, power consumption for maintaining the sleep state is reduced. In this case, it is described that the transition to the next sleep state after the external power supply is cut off is performed immediately,
The transition may be made after a certain period of time has elapsed (in the figure, “AC adapter OFF (D)”). This could be, for example, a short AC
This is to prevent the transition of the sleep state from occurring when the power supply is shut off for a short time, such as when the adapter is disconnected.
Since the transition of the sleep state takes a certain amount of time, for example, when the user sets the AC of the PC in the light sleep state,
Disconnect the adapter once and reconnect AC at the (nearby) destination.
If you try to use the PC immediately after connecting the adapter, if you fall into a deep sleep state while moving, it takes time to start up (return) and the waiting time becomes longer. The transition delay time can be given by a policy as with other conditions, so that the setting may be made in accordance with the usage environment of the user. As a method of realizing the delay, for example, the embedded controller 36 has a timer, measures the time by triggering an event occurrence (while maintaining the original sleep state), and after a predetermined time elapses, the ACP
The event is transmitted to the I-OS 320. Alternatively, the ACPI-OS 320 itself may have a timer to delay the transition to the next sleep state. The former is desirable in consideration of power consumption, but the latter allows advanced judgment and processing. If the original event cause disappears during the delay (in this example, the power supply is restarted)
Suspends all processing and returns to the original sleep state.

If the external power supply is resumed in the S3 state (indicated as “AC adapter ON” in the figure) and if the generation of the SCI interrupt due to the event cause is enabled in advance, the embedded controller 36
The power to the minimum necessary part where the PI-OS 320 can operate is turned on again, and then the AC power is supplied via POWER_PME.
The SCI interrupt request is transmitted to the PI-OS 320. AC
The PI-OS 320 thus knows that the external power supply has been restarted, determines the next operation based on the policy, and transitions to S1 in this example.

If the S1 or S3 state falls into a low battery state and if the occurrence of an SCI interrupt due to the event cause is enabled in advance,
The embedded controller 36 turns on the power to the minimum necessary parts where the ACPI-OS 320 can operate, and
S to ACPI-OS320 via OWER_PME
Signals a CI interrupt request. ACPI-OS320 is
As a result, it is known that the battery has fallen into the low battery state, the next operation is determined based on the policy, and in this example, the process transits to S4. That is, the embedded controller 36 finally turns off the system. Although indicated by a dotted line in the figure, when the low battery state is resolved (for example, when the external power supply is restarted), the sleep state becomes shallower (S1 or S3).
It is also free to make the transition to again depending on the policy.

FIG. 12 shows a state transition based on a specific example.

[0146] For example, a note P of the ACPI specification in the office
C is used (that is, AC adapter is driven)
It is assumed that the user returns the PC by returning the PC to the S1 state. Thereafter, assuming that the last return person returns after dropping the power supply breaker in the office, the state automatically transitions from the S1 state to the S3 state by detecting that the external power supply from the AC adapter has stopped. In S3 state,
The contents of the system memory 33 are backed up by the battery 37. In this state, if it is detected that the remaining capacity of the battery 37 has decreased and the battery 37 has entered the low battery state, the state automatically shifts from the state S3 to the state S4. In the S4 state, the contents of the system memory 33 are saved in the hard disk drive 35, and the system power is all turned off.

Then, the next morning, when the first employee turns on the power breaker, the system detects that the external power supply from the AC adapter has resumed, and returns to the S1 state again. Then, the battery is charged. The user is S3 at night
Or, simply without knowing that it was in S4 state,
Use can be resumed from the state (return to S0). In other words, it takes a considerable time to return from the S3 or S4 state, but the user can use it in the shortest time without making the user aware of it.

Therefore, in the office where the AC power of the office is cut off at night, even if the PC is returned to S1 when returning home, the PC is automatically turned on at night (that is, while the AC power of the office is cut off). State S3 is reached to reduce battery consumption. Even if the battery is almost exhausted, the flow goes to S4 to continue the sleep state. The next morning, the supply of AC power to the office is started, and the PC returns to S1 (charging of the battery is restarted). When the user comes to work, the PC returns to the original state, and the user returns to the night. The PC can be used again without worrying about the state.

It is to be noted that the system state to which the power state changes to which system state is determined based on the user policy.

FIG. 13 shows an example of the correspondence between user policies and transition conditions.

Here, the user policy “A”,
A state transition to be executed and its transition condition are defined for each of "B" and "C". The transition condition is defined by a combination of a condition related to the battery (low battery, recovery from the low battery) and a condition related to the external power supply (supply start, stop).

Next, the procedure of the system state control method used in this embodiment will be described with reference to the flowchart of FIG.

When the low battery state, the recovery from the low battery state, the external power off, or the external power on is detected during the state of the system G1 (steps S101 to S104), the occurrence event is set to POWER.
It is transmitted to the host system by the R_PME signal, and finally the current power state is notified to the ACPI-OS 320 by the SCI (step S105). Thereafter, the system state of the transition destination is determined from the changed power supply state and the user policy (step S106), whereby the system state is dynamically switched to one of S1, S3, and S4 (step S107).

FIG. 15 shows an example of a specific procedure of the system state switching process.

The system state switching process of FIG. 15 corresponds to the state transition diagram of FIG.

That is, when an event related to the power supply occurs, it is first determined whether or not the current system state is S1 (step S201). When the system state is S1, it is determined whether the event related to the power is due to the external power off or the low battery (steps S202 and S204).
If the external power is off, switching from S1 to S3 is performed (step S203), and if the battery is low, switching from S1 to S4 is performed (step S205).

If the current system state is not S1, it is determined whether or not it is S3 (step S20).
6). In the case of S3, it is determined whether the event related to the power is due to the external power-on or the low battery (steps S207 and S20).
9) If the external power is on, switching from S3 to S1 is performed (step S208); if the battery is low, switching from S3 to S4 is performed (step S21).
0).

If the current system state is neither S1 nor S3, it is determined that the state is S4. In this case, first, it is determined whether or not the event related to the power supply is recovery from the low battery. (Step S21
1). If the recovery is from a low battery, it is determined whether to transition to S1 or S3 based on the system state before transition to S4 or the user policy (step S212). (Step S213), and when returning to S3, switching from S4 to S3 is performed (Step S214).

According to such a system state switching process, when a system state is transited when a certain transition condition is satisfied, the original system state before the transition can be returned by resolving the transition condition. Thus, bi-directional transitions, and further, step-by-step transitions between multi-stage system states are possible.

In the second embodiment, only the transition between S1 and S3 due to the external power supply state and the transition between S4 due to the low battery state are shown. And delays in various transitions depend on the design policy of the system designer and the ACPI-OS policy.

In the second embodiment, the ACPI-OS
Although the above case is shown, the present invention can be easily applied to other OSs having the same kind of structure. Furthermore, even when the OS itself does not have a power management function, for example, the system state in the sleep state can be dynamically switched according to a change in the power supply state under the control of the system BIOS.

As described above, according to the second embodiment,
It is possible to dynamically change the depth of the sleep state according to changes in the power supply state, and to make bidirectional transitions between multiple sleep states, shortening the system startup time from the sleep state and during sleep Trade-off with power savings can be optimized.

(Third Embodiment) FIG. 16 shows a third embodiment of the present invention.
2 shows a hardware configuration of a computer system according to the embodiment. This computer system is also based on the same ACPI-OS as the second embodiment. As shown in the figure, the hardware of the computer system includes a CPU 51, a system controller 52, a system memory 53, a BIOS-ROM 54, a real-time clock (RTC) 55, a power supply controller 56, an embedded controller (EC) 58, a hard disk drive 61, and a display. A controller 62 and a keyboard controller 63 are provided.

As the CPU 51, for example, a microprocessor “pe” manufactured and sold by Intel Corporation in the United States.
ntium ”, etc. The CPU 51 uses the above-described system management mode (SMM: System Ma).
An operation mode for executing by a system management program dedicated to power management, which is referred to as “nagement mode”.

In this computer system, ACPI
It is assumed that there is no hardware for performing the power management function due to the dedicated register added in the specification (ACPI dedicated register 37 in FIG. 8).
I is issued, and hardware emulation for pre-setting and post-setting of the ACPI dedicated register 37 is executed in the SMM.

The system controller 52 is a gate array for controlling memories and I / O in the system.
SCI used for notifying the MI generation circuit and the ACPI-OS of a power management event (Power Management Event: hereinafter referred to as PME)
(System Control Interrup
t: a system interrupt) signal for supplying a signal. Since this SCI signal is mapped to the IRQ 13 according to the ACPI specification, the PME is finally transmitted to the ACPI-OS as an interrupt request.
Further, as shown in FIG. 17, the system controller 52 includes a plurality of ACPI registers (PM1a_STS, PM1a) for realizing power control by the ACPI-OS.
_CNT, GP_STS) 57.

The PM1a_STS register (FIG. 17)
(A)) are PWRBTN_STS, RTC_STS,
It is configured to include SLT_STS and WAK_STS.

PWRBTN_STS is a register set when the power switch is pressed. PWRBTN_EN when the computer system is in the normal state
When both (not shown) and PWRBTN_STS are set, SCI is issued by the SCI generation circuit. When the power switch is pressed while the computer system is in the sleep state or the off state, PW
Regardless of the setting of RBTN_EN, the EC 58 generates a wake-up event. This PWRBTN_S
The TS bit is normally set only by hardware and reset only by software writing "1" to this bit. However, in the computer system of this embodiment, the PWRBTN_S
The pre-setting process of the TS is performed by the SM-BI that performs ACPI-compliant power management, which is one module of the ACPI-compliant BIOS
The OS is executed in response to an instruction from the EC 58. SM-
When this bit is set by the BIOS, an SCI is issued, so that the ACPI-OS is notified of the PME.

The RTC_STS is a register set when the RTC 55 asserts an alarm, that is, the RTC IRQ signal. If the RTC_EN (not shown) is set and the RTC_STS bit is set, the system controller 52
The PME is notified to the OS in the above-described procedure. This RT
The C_STS bit is typically set only by hardware and is only reset by software writing a "1" to this bit. If the computer system is asleep, the RTC_STS bit shall be set to ACPI-O if the RTC is causing wake-up.
Must be set before control is returned to S. In the computer system of this embodiment,
The SM-BIOS performs the pre-setting of the RTC_STS by the E-
It is executed according to the instruction from C58. When this bit is set by the SM-BIOS, an SCI is issued, so that the ACPI-OS is notified of the PME.

SLT_STS is a register in which a value indicating the cause is set when the state of the computer system transitions between sleep states. SLT_ST
With the S bit set, the computer system transitions between sleep states using SLP_EN and SLP_TYPx in the PM1a_CNT register described below. Although the SLT_STS is normally set only by hardware and reset only by writing “1” to this bit by the software, in the computer system of this embodiment, SLT_STS is used.
The SM-BIOS executes pre-setting processing of the STS in accordance with an instruction from the EC 58. When this bit is set by the SM-BIOS, an SCI is issued.
The PME is notified to the CPI-OS.

WAK_STS is a register set when a wake-up event such as a power switch or RTC occurs while the computer system is in a sleep state. With the WAK_STS bit set, the computer system transitions to a normal operating state. WAK
The _STS bit is normally set only by hardware and is reset only by software writing "1" to this bit. However, in the computer system of this embodiment, the WAK_STS bit is set.
The SM-BIOS executes pre-setting of S in response to an instruction from the EC 58. When this bit is set by the SM-BIOS, an SCI is issued.
The PME is notified to the I-OS.

The PM1a_CNT register (FIG. 17)
(B)) is configured to include SLP_TYPx and SLP_EN.

SLP_TYPx defines the sleep state types S1 to S5 to which the computer system transitions when the SLP_EN bit is set to "1". DSDT held in ACPI table described later
(Differentiated System De
The _Sx object described in the P code in the description table (script table: information describing characteristics of various systems) has a 3-bit binary value associated with each sleep state defined in the object. The ACPI driver 123 determines the target _S
Taking two values from the x object, SLP_T
It is programmed to set each of the above values in the YP bit.

SLP_EN is a write-only bit. By setting this bit, it is possible to cause the computer system to transition to a sleep state according to the value of SLP_TYPx.

In the computer system of this embodiment, when the system enters a sleep state or transitions between sleep states, the ACPI driver (323 in FIG. 8) sets the SLP_EN bit and SLP_TY
Since Px is set, SM-BIOS sets SLP_
A sleep process according to TYPx is executed.

Further, the GP_STS register (FIG. 17)
(C)) is composed of GP_STS5, GP-ACON and the like.

GP_STS5 is a register set in response to a battery status event.
ACON is a register set in response to an event of a power supply state from the outside (AC adapter). These bits are set by the SM-BIOS in response to an instruction from the EC 58 that has received the notification from the power supply controller 56, and the SCI is issued by this setting, thereby notifying the ACPI-OS of the PME. .

The system memory 53 includes an ACPI-OS,
It is a main memory that stores application programs to be processed, user data created by application programs including utilities, and the like.

The SM-RAM 100 is a memory mapped in the address space from FFFE0000H of the system memory 53 to 64 KB.
The address range to which the RAM is mapped is not fixed, but can be changed to any location in the 4 Gbyte CPU memory address space by a register called SMBASE. The SMBASE register cannot be accessed unless it is in SMM.

When the CPU 51 shifts to the SMM, the SMI
In addition to the status of the register in the CPU 51 at the time of issuance, in the computer system of this embodiment, battery information and the like are saved in the SM-RAM 100. Further, the SM-RAM 100 includes a BIOS.
-A command for calling the sleep control program in the ROM 14 is also stored.

The BIOS-ROM 54 stores the BIOS and is constituted by a flash memory so that a program can be rewritten. The BIOS is configured to operate in the real mode. The BIOS includes a BIOS-IRT routine executed at the time of system boot, and a BIOS for controlling various I / O devices.
S-RUN and SM-B for managing ACPI-compliant power
IOS and ACPI tables are included. SM-BIOS
Is a program executed in the SMM, and includes an SMI program including a sleep control of a computer system and a routine for setting an event factor in the SM-RAM, an SMI handler for determining an SMI routine to be executed, and the like. The SMI handler is the first BIOS called by the CPU 11 when an SMI occurs.
This checks the cause of the SMI occurrence and calls the SMI routine corresponding to the cause.

The ACPI table stores 64 bytes of the CPU address space of 8 Mbytes or more from the flash ROM in the IRT.
Transferred to KB block. The ACPI table has four tables, RSDT, FACP, DSDT and FA.
It is composed of CS.

RSDT (Root System De)
The “scription table” refers to another table stored in the main memory, and as the first table, always uses FACP (Fixed ACPI D).
description table). FACP
The purpose of this is to define a wide variety of static system information for power management. That is, the data in the FACP includes a wide variety of fixed length entries that describe the fixed hardware ACPI features. FACP always includes DSDT (Diffe) that describes information for various system features.
retented System Description
ion Table). The ACPI driver controls the power of the hardware of the computer system according to a hardware definition block (an object for processing power management of each device) described in P code stored in the DSDT. FACS (Firmw
are ACPI Control Structure
e) S from the S3 state of the computer system
A wakeup vector or the like for executing a state transition to the 0 state is defined.

The RTC 55 is a clock module having a unique operation battery, and has a CMOS memory to which power is constantly supplied from the battery. In this CMOS memory, the system operating environment is used for storing setup information and alarm time of year, month and day.

The power controller 56 controls a power circuit to supply power to each unit in the system, and includes a one-chip microcomputer. The power controller 56 reports status changes such as the remaining battery capacity and the presence or absence of the AC adapter connection to the EC 58.

The hard disk drive 61 uses ACPI
-Store an OS, application programs including utilities, and data and files processed by the CPU 51.

The EC 58 includes a power supply sequence control, a power supply status change factor monitoring, a battery information service,
It has functions such as heat control of PU and LED control.

The power supply sequence control is a sequence control relating to the on / off of the power switch and the power suspend process. The monitoring of the cause of the change in the power supply state includes a power switch, panel open / close, wake-up monitoring from the RTC 55 and a modem ring, low battery state monitoring, and power supply abnormality monitoring. The battery information service performs monitoring of battery attachment / detachment, reading of battery information (capacity / state change), and transfer to the ACPI-OS. Battery attachment / detachment is monitored by the power supply controller 56,
The EC 58 receives the change in the state of attachment / detachment of the battery via the I ² C bus. The EC 58 notifies the system of the event using the SCI after determining the change in the battery attachment / detachment state.

In the computer system of this embodiment, when a battery is loaded in the system body, EC 58
Before notifying the system of the battery insertion / removal event with the CI, the battery information is received via the I ² C bus, and the SM-
The BIOS stores the battery information in the SM-RAM and transfers the PME to the system.

Since the battery information is periodically transmitted from the power supply controller 56, the information is read by the EC 58, and if a change in the information value of the battery is recognized, the EC 58 reads the battery information by the SM-BIOS. Store in SM-RAM and transfer PME to system.

The LED control is an LED lighting control in accordance with the sleep state (Sx) of the system.

Since the EC 58 operates even when the system is suspended or powered down, the EC 58 operates with a low-speed clock in order to aim for low power of the EC 58 itself. In the computer system of this embodiment, the ACPI-OS
The battery information to be read in response to a request from
Information is transferred to the M-RAM in advance, and a request from the ACPI-OS is read from the SM-RAM.

The display controller 62 is an LCD or CRT.
It is for controlling the display of the display such as
By writing the display data received from the CPU 51 into the video memory, display processing on an LCD, a CRT, or the like is executed.

The keyboard controller 63 monitors the operation of the keyboard and the mouse, and takes in the user's instruction operation into the system.

As described above, with such a configuration, various transitions of the system state including the sleep state can be executed by software without complicating the hardware. Here, the transition of the system state of the computer system of this embodiment is shown in FIG.

From the user's point of view, the global system states (G0, G1, G
Only 2) is the only known system state. G0 is equal to S0 and G2 is equal to S5. All sleep states (S1 to S4) appear to the user as one G1 state. However, in the computer system of this embodiment, S2 is not implemented to simplify the description. Now, in G1, which sleep state is actually taken depends on the ACPI-O based on the user policy and the OS policy.
S120 is determined. The user policy is represented by an abstract expression such as "I want to shorten the sleep recovery time" or "I want to make the battery last longer", and informs the ACPI-OS of the user's desire. On the other hand, the OS policy is a policy defined by the ACPI-OS itself, such as "it seems to be infrequently used by the user", "often driven by a battery", and "device xx is in an idle state". It can be determined based on the use state of the user, the state of the device, and the like. ACPI-OS
Judge these policies comprehensively, and finally select one sleep state.

Next, referring to FIG. 19, the computer system of this embodiment first transitions to S1, and further proceeds to S1.
The operation procedure at the time of transition from the state to the other sleep state (S3, S4) will be described.

Upon determining the transition to S1, the ACPI-OS first executes the following AML code. That is, 1 is set to SLP_TYP, and SLP_EN is set. When SLP_EN is set, an SMI interrupt occurs, and as a result, execution of the SM-BIOS is started.

In the SM-BIOS, the transition to S1 is
Upon knowing that the instruction has been given from the PI-OS, the display is turned off, and a message indicating that an attempt is made to shift to S1 is made to EC5.
8, the CPU clock is stopped.

On the other hand, in response to the notification, the EC 58 turns on the S1 indicator (for example, one of the externally displayed lamps) and waits for a wake-up event.
Then, for example, when the AC adapter is turned off or the low battery state is detected, it is a wake-up event and the processing is started. The EC 58 determines the cause of the wake-up and stores it in its own memory as a wake-up cause flag. And EC58 is S
Issue MI and restart CPU.

When the CPU clock is restarted upon issuance of the SMI, the CPU 51 restarts execution of the SM-BIOS. The resumed SM-BIOS reads the memory in the EC 58 to know the cause of the wake-up, and when the cause is the AC adapter off or the low battery, sets the value corresponding to the cause in the SLT_STS. Then, the interrupt mask is changed so as to enable the SCI interrupt, and the processing of the SMI interrupt, that is, the SM-BIOS ends. On the other hand, if the cause is other than the above, for example, pressing of the power switch, WAK_STS is set and return to S0 is performed as in the related art.

The ACPI-OS reads the wake-up factor flag (this is because the SM-BIOS does not directly access the memory in the EC 58,
The user policy is read using a flag prepared separately by the AML code), and if the transition corresponding to the factor is permitted, the transition corresponding to the factor is performed. That is, if the AC adapter is off, SLP_T
The transition to S3 is performed by setting YP to 3 and setting SLP_EN. Similarly, if the battery is a low battery, SLP_TYP is set to 4 and SLP_EN is set to execute the transition to S4.

Next, referring to FIG. 20, the computer system of this embodiment first transitions to S3,
The operation procedure at the time of transition to the other sleep state (S1, S4) from will be described.

When the ACPI-OS determines the transition to S3, it first executes the following AML code. That is, SLP_TYP is set to 3, and SLP_EN is set. When SLP_EN is set, an SMI interrupt occurs, and as a result, execution of the SM-BIOS is started.

In the SMI-OS, the transition to S3 is ACP
When the I-OS receives the instruction, it executes a general suspend process, notifies the EC 58 that the process is going to shift to S3, and stops the CPU clock.

On the other hand, in response to the notification, the EC 58 turns off the power of the CPU and various devices, and waits for a wake-up event. When a wake-up event occurs, the EC 58 determines the cause of the wake-up and stores the wake-up event in its own memory as a wake-up cause flag. Then, the EC 58 issues an SMI and restarts the CPU.

When the CPU clock is restarted upon issuance of the SMI, the CPU 51 restarts execution of the SM-BIOS. The resumed SM-BIOS reads the memory in the EC 58 to know the cause of the wake-up, and when the cause is the AC adapter on or the low battery, sets the value corresponding to the cause in the SLT_STS. Then, the interrupt mask is changed so as to enable the SCI interrupt, and the processing of the SMI interrupt, that is, the SM-BIOS ends. On the other hand, if the cause is other than the above, for example, pressing of the power switch, WAK_STS is set and return to S0 is performed as in the related art.

The ACPI-OS reads the wake-up factor flag, checks the user policy, and if the transition corresponding to the factor is permitted, performs the transition corresponding to the factor. That is, if the AC adapter is on, SL
The transition to S1 is performed by setting P_TYP to 1 and setting SLP_EN. Similarly, if the battery is a low battery, SLP_TYP is set to 4 and SLP_TYP is set.
The transition to S4 is executed by setting EN.

As described above, according to the computer system of the third embodiment, the transition between the sleep states such as the transition from the light sleep state to the deep sleep state, and the transition from the deep sleep state to the light sleep state, This can be realized by software without complicating the hardware.

It is preferable that the user can arbitrarily determine under what conditions the transition between the sleep states is permitted. The so-called user policy mentioned above,
Since it is an abstract expression independent of hardware, it is ambiguous expression for a user familiar with a personal computer. For this reason, there is a strong demand from the user to make an optimal setting depending on the hardware. Therefore, a method for satisfying the demand will be described below. Before that, the transition between sleep states as viewed from the user of the personal computer will be further described.

As described above, in ACPI, the system states that the user should be aware of are summarized as G states such as G0, G1, and G2. Sleep state S
1, S3, and S4 are substates of G1 as shown in FIG. 18, and are originally defined on the assumption that the user is not conscious. However, the characteristics of the personal computer that are important to the user, such as how long the sleep state can be maintained only by the battery and the time required to transition from the sleep state to the operation state, are S1 and (S
2) It changes greatly depending on which of the states S3 and S4 are in. Therefore, for a user who is familiar with a personal computer, it is highly preferable that the transition between the sleep states is automatically performed as described above, and that a desired condition can be set therewith. .

On the other hand, automatic transition between sleep states may have a bad side effect depending on how it is used. Therefore, for a user who is not familiar with a personal computer,
In some cases, the automatic transition itself is not desirable. For example, when the computer is connected to a network or transits to S1 while a certain program is being executed, the process of the personal computer can be continued from the previous state when returning to the operation state.
After the transition to S3 or S4 and the power of the device is once turned off, the processing may not be continued in the same manner. In such a state, a user who is not familiar with the personal computer may be confused, and for such a user, the automatic transition between the sleep states should not be performed as in the related art. Is preferred.

In order to solve such conflicting demands, the computer system of this embodiment employs the following method. That is, (1) Initially set to a state in which automatic transition between sleep states is prohibited so that a beginner of a personal computer can use the apparatus easily.

(2) A condition selection utility (configured as an application program whose execution is controlled by the CPU 51) for changing the initial settings is prepared by a user who is not familiar with the personal computer and ACPI at the initial stage when the utility is started. Display a screen warning you not to change the settings.

(3) The user responds A to the displayed warning.
When the user has declared that he / she knows CPI well, a screen for actual condition selection is displayed.

FIG. 21 shows an example of the main part of the above-mentioned warning screen. If you accidentally invoke the condition selection utility, clearly indicate how to cancel it.
Also, be aware that the user is familiar with the personal computer and the software he is using, that the user is familiar with ACPI, and that the user is actually intended to run this condition selection utility. A response input for individually confirming three points is requested, and a condition selection utility is constructed so that when all three responses are “YES”, the process proceeds to a substantial condition selection process.

FIG. 22 shows that all the response inputs of FIG.
This is an example of a screen displayed by the condition selection utility when “ES” is set. The system states and their transitions are shown in a valid graph. The system state (S2 here) that cannot be used in the system is indicated by a broken line, so that the user can immediately understand that fact. Currently enabled state transitions are shown by solid lines, while those that are not enabled are shown by dashed lines. State transitions that cannot be realized by the system irrespective of the user's request are not shown on the screen. Therefore,
In the case of FIG. 22, for example, it is not possible to make a direct transition in either direction between S4 and S5, and the transition between the sleep states of S1 to S4 is not currently enabled.

In this state, when the dashed arrow from S3 to S1 is pointed with, for example, a mouse cursor and the mouse is clicked, the condition selection utility causes
As shown in FIG. 23, a window for displaying a list of events that can be selected as the condition of the state transition is displayed. Then, in this window, for example, an event of AC adapter ON is selected as a transition condition, and when the OK button is clicked, this transition is enabled, and the condition selection utility changes the arrow from S3 to S1 to a solid line.

On the other hand, when the arrow indicated by the solid line is clicked, the condition selection utility displays a window for displaying a list of conditions that can cause the state transition and checks the currently selected one. Add a mark. Then, when all the checks are removed, the state transition is disabled.

If it is assumed that the condition of the power switch cannot be deleted from the conditions for transitioning from S0 to S5, when this arrow is clicked, the condition selection utility makes the power switch as shown in FIG. By fixedly turning on the check mark of,
Let the user know that there are such restrictions.

The transition conditions set / changed in this way are registered as a user policy in the table described with reference to FIG.
The transition between the sleep states in S4 is automatically performed.

As described above, according to the computer system of the third embodiment, the user can arbitrarily select a transition condition that causes a transition between a plurality of sleep states. An experienced user who has sufficient knowledge of a plurality of sleep states can make desired settings in detail according to the application and the like.

In the above-described embodiment, ACPI-
Although the case where the control is performed by the OS has been described, the present invention is not limited to this, and can be easily applied to various operating systems.

It is also effective to apply the present invention to a pen input type personal computer having a handwriting interface. In this case, instead of clicking the arrow of the directed graph with the mouse as in the above-described embodiment, for example, as illustrated in FIG. In this way, it is possible to select a desired transition between sleep states.

The first to third embodiments described above can be used in appropriate combinations. For example, it is possible to allow the user to set / change the transition condition from suspend to hibernation in the first embodiment. It is possible.

[0226]

As described above, according to the present invention,
By realizing the mechanism of automatic transition from the suspend state to the hibernation state, new system state control is possible in which information is not lost even by a low battery and the system state can be restored at high speed.

Further, the depth of the sleep state can be dynamically switched in both directions according to a change in the power supply state during the sleep state, and the system state is always automatically set to the optimum sleep state. Becomes possible. Therefore, it is possible to optimize the trade-off between the reduction of the system startup time from the sleep state and the power saving during the sleep.

Further, the transition between the sleep states such as the transition from the light sleep state to the deep sleep state and the transition from the deep sleep state to the light sleep state can be performed without complicating the hardware. This can be realized by software.

Further, since the user can arbitrarily set and change the transition condition for causing a transition between a plurality of sleep states, a skilled person having sufficient knowledge of the plurality of sleep states defined in the ACPI specification is provided. The user can make a desired setting in detail according to the use or the like.

[Brief description of the drawings]

FIG. 1 is an exemplary block diagram showing the configuration of an entire computer system according to a first embodiment of the present invention;

FIG. 2 is an exemplary view for explaining a series of operations from generation of an SMI to activation of a suspend / hibernation routine in the system according to the first embodiment;

FIGS. 3A and 3B are a state transition diagram showing a transition of a system state and an example of a setup screen for setting a power-up mode in the system according to the first embodiment; FIGS.

FIG. 4 is an exemplary view showing a state transition of a system state when a low battery is detected at the time of suspending in the system of the first embodiment.

FIG. 5 is an exemplary flowchart showing a procedure of a transition process from an operation state to a suspend / hibernation state in the system according to the first embodiment;

FIG. 6 is an exemplary flowchart showing the procedure of automatic transition processing from a suspend state to a hibernation state in the system according to the first embodiment;

FIG. 7 is an exemplary flowchart showing the procedure of a return process from a suspend / hibernation state in the system according to the first embodiment;

FIG. 8 is a diagram showing a configuration of a computer system according to a second embodiment of the present invention.

FIG. 9 is an exemplary view showing a hardware configuration of a computer system according to the second embodiment.

FIG. 10 is an exemplary view showing hardware logic for detecting and notifying a power management event in the system according to the second embodiment.

FIG. 11 is a state transition diagram showing transition of a system state in the system of the second embodiment.

FIG. 12 is a state transition diagram illustrating a specific state of a system state transition in the system according to the second embodiment.

FIG. 13 is an exemplary view showing a relationship between a user policy and a transition condition used in the system according to the second embodiment;

FIG. 14 is an exemplary flowchart showing the procedure of a system state control method applied to the system of the second embodiment;

FIG. 15 is an exemplary flowchart illustrating an example of the procedure of a system state switching process applied to the system of the second embodiment.

FIG. 16 is a diagram showing a hardware configuration of a computer system according to a third embodiment of the present invention.

FIG. 17 is a view showing an ACPI register of a system controller provided in the system according to the third embodiment;

FIG. 18 is a diagram showing a state transition of the system according to the third embodiment.

FIG. 19 is an exemplary view for explaining an operation procedure when the computer system of the third embodiment transitions first to S1, and further transitions from S1 to another sleep state (S3, S4);

FIG. 20 is an exemplary view for explaining an operation procedure when the computer system of the third embodiment transitions first to S3 and further transitions from S3 to other sleep states (S1, S4);

FIG. 21 is an exemplary view showing an example of a main part of a warning screen displayed by a condition selection utility applied to the system of the third embodiment.

FIG. 22 is a diagram showing an example of a screen displayed by the condition selection utility when all of the response inputs in FIG. 20 are set to “YES”.

FIG. 23 is a view showing an example of a screen displayed by the condition selection utility when a transition of a disabled state is clicked on the screen of FIG. 22;

FIG. 24 is a view showing an example of a screen on which a condition selection utility displays transition conditions that cannot be deleted by the user.

FIG. 25 is a diagram illustrating a state in which a desired transition between sleep states is selected by writing with an input pen.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... CPU 12 ... System controller 13 ... Main memory 13A ... SMRAM 14 ... BIOS-ROM 15 ... HDD 16 ... RTC 17 ... Keyboard controller 18 ... Embedded controller (EC) 19 ... Power supply controller 20 ... Built-in battery 21 ... External power supply 22 ... VGA controller 23 VRAM 31 CPU 32 System controller 33 Main memory 34 BIOS-ROM 35 Hard disk device 36 Embedded controller (EC) 37 Built-in battery 38 External power supply 320 ACPI-OS 321 Event / status Register (GP_RE
G) 321 Kernel 322 Device driver 323 ACPI driver 324 Power management system software 330 Application program 350 BIOS compatible with ACPI 360 ACPI table 51 CPU 52 System controller 53 System memory 54 BIOS- ROM 55 RTC 56 Power supply controller 57 ACPI register 58 EC 61 Hard disk drive 62 Display controller 63 Keyboard controller

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Makoto Sakai 2-9-9 Suehirocho, Ome-shi, Tokyo Inside the Toshiba Ome Plant (72) Inventor Mayumi Maeda 2-9-9 Suehirocho, Ome-shi, Tokyo Stock Association (72) Inventor Fumitaka Sato 1381 Shinmachi, Ome-shi, Tokyo Toshiba Computer Engineering Co., Ltd.

Claims (36)

[Claims] 1. An operation state, an off state, and a sleep state intermediate between the operation state and the off state, for saving information necessary for restoring a work state to a memory and backing up the contents of the memory. In a computer system having a suspend state that supplies a necessary minimum power supply, an event occurrence detecting unit that detects whether an event that requires a transition to a sleep state with lower power consumption than the suspend state has occurred, Means for, when the occurrence of the event is detected during a period in which the computer system is in the suspend state, saving the contents of the memory in the suspend state to a secondary storage device and turning off a system power supply. A computer system characterized by the following: 2. The computer system according to claim 1, wherein the event occurrence detecting means detects a low battery state of a battery provided in the computer system as the occurrence of the event. 3. The computer system according to claim 1, wherein said event occurrence detecting means detects a stop of power supply from an external power supply to said computer system as occurrence of said event. 4. The event occurrence detecting means detects as an occurrence of the event an alarm indicating that a time elapsed from a transition from the operation state to the suspend state has reached a predetermined time. The computer system according to claim 1. 5. The computer system according to claim 1, wherein the event occurrence detecting means detects a predetermined button operation provided on the computer system by a user as occurrence of the event. 6. An operation state, an off state, and a sleep state intermediate between the operation state and the off state, for saving information necessary for restoring a work state to a memory and backing up the contents of the memory. Computer system having a suspend state in which a minimum power supply is provided, and a hibernation state in which the contents of the memory are saved in a secondary storage device and the system power is turned off. Means for setting a system state of the computer system to one of the suspend state and the hibernation state based on environment setting information indicating which of the suspend state and the hibernation state is to be used as the sleep state during the transition From the suspend state to the hibernation state Event occurrence detecting means for detecting the presence or absence of an event requiring a transition to, when the occurrence of the event is detected while the computer system is in the suspended state, the contents of the memory in the suspended state Means for saving the system state to the secondary storage device and changing a system state of the computer system from the suspend state to the hibernation state. 7. When returning from the suspend state to the operating state, it is determined whether or not a transition from the suspend state to the hibernation state has been performed during the suspend state, and the transition to the hibernation state is performed. 7. The computer system according to claim 6, wherein when the operation is performed, the work state is restored using the contents of the secondary storage device. 8. An operation state, an off state, and a sleep state intermediate between the operation state and the off state, information necessary for restoring the work state is saved in a memory, and the contents of the memory are backed up. A system state control method for a computer system having a suspend state for supplying a minimum power supply, wherein the computer system transitions to a sleep state with lower power consumption than the suspend state during the suspend state. Monitoring for the occurrence of an event requiring, and when the occurrence of the event is detected while the computer system is in the suspended state, the contents of the memory in the suspended state are backed up to a secondary storage device. And turning off the system power supply. 9. An operation state, an off state, and a sleep state intermediate between the operation state and the off state, for saving information necessary for restoring a working state to a memory and backing up the contents of the memory. A system state control method for a computer system having a suspend state in which a minimum power supply is provided and a hibernation state in which the contents of the memory are saved to a secondary storage device and the system power is turned off. At the time of transition to a state, the system state of the computer system is changed to one of the suspend state and the hibernation state based on environment setting information indicating which of the suspend state and the hibernation state is used as the sleep state. Setting, the computer system During the suspended state, it is monitored whether or not an event that requires a transition to a sleep state with lower power consumption than the suspended state has occurred, and the occurrence of the event during the period when the computer system is in the suspended state is monitored. Detecting the state of the computer, saves the contents of the memory in the suspended state to the secondary storage device, and changes the system state of the computer system from the suspended state to the hibernation state. Method. 10. A computer system having an operating state, an off state, and a plurality of sleep states in between, a means for detecting a change in a power supply state to the computer system, and the computer system including the plurality of sleep states. When a change in the power supply state is detected during a sleep state of any of the above, the computer system transitions between the plurality of sleep states according to the change in the power supply state. And a sleep state transition unit for causing the computer to sleep. 11. The means for detecting a change in the power supply state includes means for detecting the presence or absence of a low battery state of a battery provided in the computer system as the change in the power supply state, and the sleep state. 11. The computer system according to claim 10, wherein the transition unit switches the sleep state of the computer system according to the detection of the low battery state and the detection of the recovery from the low battery state. 12. The means for detecting a change in the power supply state includes means for detecting the presence or absence of power supply from an external power supply to the computer system as a change in the power supply state. The computer system according to claim 10, wherein a sleep state of the computer system is switched according to a change in a power supply state from the external power supply. 13. The computer system according to claim 1, wherein the return time to the operation state and the power consumption are different from each other.
And a second sleep state, wherein the sleep state transition means includes a state transition condition from the first sleep state to the second sleep state during a period in which the computer system is in the first sleep state. Switching the computer system from the first sleep state to a second sleep state when a corresponding change in the power supply state is detected, wherein the computer system is in the second sleep state during the first sleep state; 11. The computer system according to claim 10, wherein when the state transition condition from the sleep state to the second sleep state is resolved, the computer system is returned to the first sleep state. 14. A means for detecting a change in the power supply state, means for detecting whether or not a battery provided in the computer system has a low battery state, and whether or not power is supplied to the computer system from an external power supply. The sleep state transition means, based on a combination of the state of the battery detected by the means for detecting a change in the power supply state and a power supply state from the external power supply, 11. The computer system according to claim 10, wherein a sleep state of the computer system is dynamically changed among the plurality of sleep states. 15. A computer further comprising means for waiting for a sleep state switching process by the sleep state switching means until a predetermined period elapses after a change in a power supply state to the computer system is detected, and 11. The computer system according to claim 10, wherein when the power supply state is restored to the original state, the sleep state switching processing by the sleep state switching unit is stopped. 16. A computer system having an operating state, an off state, and a plurality of sleep states intermediate therebetween, a means for detecting occurrence of an event corresponding to a state transition condition between the plurality of sleep states, Means for, when the occurrence of the event is detected during a period in which the computer system is in any one of the plurality of sleep states, performing a state transition between the sleep states in accordance with the generated event. A computer system characterized by: 17. A system state control method for a computer system having an operation state, an off state, and a plurality of sleep states intermediate therebetween as a system state, wherein a change in a power supply state to the computer system is detected. When the change in the power supply state is detected during a period in which the computer system is in any one of the plurality of sleep states, the computer system switches the sleep state according to a result of the detection, and the power supply state Changing the sleep state of the computer system among the plurality of sleep states according to a change in the system state. 18. When a stop of power supply from an external power supply to the computer system is detected during a period in which the computer system is in the first sleep state, the computer system is moved out of the first sleep state. Switching to a second sleep state with low power consumption, and when the resumption of power supply of the external power supply is detected, returning the computer system from the second sleep state to the first sleep state. The system state control method according to claim 17, wherein 19. When a low battery state of a battery provided in the computer system is detected while the computer system is in the first sleep state, the computer system is moved from the first sleep state to a lower state. Switching to a second sleep state with low power consumption, and when the recovery from the low battery state of the battery is detected, returning the computer system from the second sleep state to the first sleep state. The system state control method according to claim 17, wherein 20. A system state control method for a computer system having an operation state, an off state, and a plurality of intermediate sleep states as a system state, wherein the method corresponds to a state transition condition between the plurality of sleep states. Detecting the occurrence of an event, when the occurrence of the event is detected during a period in which the computer system is in any one of the plurality of sleep states, the state during the sleep state according to the generated event; A system state control method characterized by executing a transition. 21. A computer system having an operation state, an off state, and a plurality of sleep states between the operation state and the off state, wherein a CPU and a state of the system are selected from among the plurality of sleep states. State control means for controlling the state to be in one of the plurality of sleep states; and
A computer system comprising: a program for operating U. 22. When the state of the system is in the first state of the plurality of sleep states, the operation state of the system is changed from the first state to the second state of the plurality of sleep states. Detecting means for detecting that a predetermined transition condition for causing a transition is met; and, when the detecting means detects that the transition condition is met,
22. The computer system according to claim 21, further comprising: a notifying unit that notifies the CPU to that effect. 23. The computer system according to claim 22, further comprising a controller consuming less power than said CPU, wherein said detecting means is controlled by said controller. 24. A computer system having an operation state, an off state, and a plurality of sleep states between the operation state and the off state, wherein a transition condition for causing a transition between the plurality of sleep states is selected. A computer system, comprising: a selection unit for causing a transition between the plurality of sleep states according to a transition condition selected by the selection unit. 25. The computer system according to claim 24, wherein said selection means causes a transition condition to be individually selected for all transitions between said plurality of sleep states. 26. The selecting means sets a specifying means for specifying any one of all the transitions between the plurality of sleep states, and a transition condition for causing the transition specified by the specifying means. 26. The computer system according to claim 25, further comprising a setting unit. 27. The setting means displays a list of all transition conditions that can be set for the transition specified by the specifying means, and selects any one of the transition conditions from the list. 27. The computer system according to claim 26, wherein the selection is performed. 28. A directed graph display means for displaying a directed graph, in which each of the plurality of sleep states is a vertex and transition between the sleep states is an edge connecting these vertices, wherein the directed graph display means displays the directed graph. 27. The computer system according to claim 26, further comprising: selection instructing means for selecting and instructing any one of the selected sides. 29. The computer system according to claim 28, wherein said directed graph display means does not display an edge corresponding to a transition between sleep states for which transition conditions cannot be set. 30. The directed graph display means displays sides corresponding to transitions between sleep states for which transition conditions have been set and sides corresponding to transitions between sleep states for which transition conditions have not been set, in different shapes from each other. The computer system according to claim 28, wherein 31. The setting means displays a list of all transition conditions that can be set for a transition between sleep states corresponding to the side selected and instructed by the selection instructing means, and displays all the transitions displayed in the list. 29. The computer system according to claim 28, further comprising window display means for displaying a window screen for selecting one of the transition conditions from the conditions. 32. Handwritten data input means for inputting data written on a display screen, wherein the selection instruction means is provided on any one of all sides displayed by the display means. 29. The computer system according to claim 28, wherein the user is caused to write a predetermined mark to make a selection instruction. 33. The method according to claim 24, wherein the selection unit holds a transition prohibition as a default value of the transition condition.
Or the computer system of 32. 34. A computer system that operates under the control of an operating system that manages an operating state, an off state, and a plurality of sleep states between the operating state and the off state. State control means for controlling to any one of a plurality of sleep states; and the CP so as to transition a state of a system controlled by the state control means between the plurality of sleep states.
A computer system comprising: a program for operating U. 35. A computer system having an operating state, an off state, and a plurality of sleep states between the operating state and the off state, wherein a CPU and a state of the system are any one of the plurality of sleep states. And a state control means for controlling the state of the computer system to be in the first state among the plurality of sleep states. Detecting a match with a predetermined transition condition that causes a transition from the first state to the second state among the plurality of sleep states; and Operating the CPU to transition the state of the system controlled by the state control means between the plurality of sleep states. State transition control method according to symptoms. 36. A state transition control method for a computer system having an operating state, an off state, and a plurality of sleep states between the operating state and the off state, wherein a transition condition for causing a transition between the plurality of sleep states is provided. And a step of performing a transition between the plurality of sleep states according to the selected transition condition.