JPH11330697A - Manufacture of glass ceramic multilayer wiring circuit board, glass ceramic multilayer wiring circuit laminate and its manufacture - Google Patents

Manufacture of glass ceramic multilayer wiring circuit board, glass ceramic multilayer wiring circuit laminate and its manufacture

Info

Publication number
JPH11330697A
JPH11330697A JP10136299A JP13629998A JPH11330697A JP H11330697 A JPH11330697 A JP H11330697A JP 10136299 A JP10136299 A JP 10136299A JP 13629998 A JP13629998 A JP 13629998A JP H11330697 A JPH11330697 A JP H11330697A
Authority
JP
Japan
Prior art keywords
copper foil
ceramic multilayer
multilayer wiring
wiring circuit
glass ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10136299A
Other languages
Japanese (ja)
Inventor
Masato Nakamura
真人 中村
Shosaku Ishihara
昌作 石原
Yoichi Abe
洋一 阿部
Norihiro Ami
徳宏 阿美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10136299A priority Critical patent/JPH11330697A/en
Publication of JPH11330697A publication Critical patent/JPH11330697A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Abstract

PROBLEM TO BE SOLVED: To provided a manufacturing method of a circuit board having surface copper metallizing which has high bonding strength and no voids in a surface. SOLUTION: An electrolytic copper foil 2 or a rolled copper foil in which either one of a mat surface or a drum surface is worked to have surface roughness Rt greater than or equal to 3 μm is subjected to pattern formation. Lamination compression bonding is so performed that the surface worked to have surface roughness Rt greater than or equal to 3 μm turns to a bonding surface to a green sheet. After the lamination compression bonding is so performed that the surface worked to have surface roughness Rt greater than or equal to 3 μm turns to the bonding surface to the green sheet, a glass ceramic multilayer wiring circuit laminate 1 obtained by pattern formation is baked. As a result, the bonding area of a Cu/glass ceramic interface is increased, and anchor junctions are formed, so that a circuit board having surface copper metallizing exhibiting high bonding strength is provided.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体部品を取り
付けたり、電気入出力のためのピンを取り付けて機能モ
ジュールを構成するのに好適な多層回路基板およびその
製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board suitable for mounting a semiconductor component or mounting a pin for electrical input / output to form a functional module and a method of manufacturing the same.

【0002】[0002]

【従来の技術】ガラスセラミック多層配線基板は低抵抗
導体である銅と銅の融点以下の温度で焼結可能なガラス
を主成分とするセラミック絶縁部からなる。ガラスセラ
ミック多層配線基板はガラスセラミック粉末とバイン
ダ、溶剤、その他の助剤からなるグリーンシートを製造
し、該グリーンシートに所用の穴をあけた後、導体ペー
スト組成物を穴埋め印刷及びパターン印刷し、該グリー
ンシートを位置合わせして複数枚積層圧着してなるガラ
スセラミック多層配線回路積層体を焼結することによっ
て製造する方法がIBM.J.RES.DEVELO
P.VOL36 NO.5 P889〜904等に示さ
れている。
2. Description of the Related Art A glass-ceramic multilayer wiring board comprises a low-resistance conductor copper and a ceramic insulating portion mainly composed of glass which can be sintered at a temperature lower than the melting point of copper. The glass ceramic multilayer wiring board is a glass ceramic powder and a binder, a solvent, a green sheet comprising a solvent and other auxiliaries is manufactured, after drilling necessary holes in the green sheet, a conductive paste composition is filled and printed with a pattern, A method of manufacturing by sintering a glass ceramic multilayer wiring circuit laminate obtained by aligning the green sheets and laminating and pressing a plurality of the sheets is disclosed in IBM. J. RES. DEVELO
P. VOL36 NO. 5 P889-904.

【0003】通常、回路基板は表面にLSI等の機能性
素子を半田で接合するための導体パッド及び封止フレー
ムを半田で接合するための封止部メタライズを持ち、内
部には配線層、電源層等を持ち、裏面には他の電子部品
の端子あるいは他の電子部品を接続するための入出力用
ピンを半田で接合するための導体パッドを持つ。表裏面
の導体パッド及び封止部メタライズには多くの場合、L
SI等の機能性素子、電子部品の端子、封止フレームあ
るいは他の電子部品を接続するための入出力用ピンを接
合する前に該導体パッド及び該封止部メタライズ表面に
Au、Ni等のめっきが施される。
Normally, a circuit board has, on its surface, conductive pads for bonding functional elements such as LSIs by solder, and a sealing metallization for bonding a sealing frame with solder, and a wiring layer and a power supply inside. It has a layer and the like, and has a conductor pad on the back surface for joining terminals of other electronic components or input / output pins for connecting other electronic components by soldering. In many cases, the metallization on the front and back surfaces of the conductive pad and the sealing portion
Before joining input / output pins for connecting functional elements such as SI, terminals of electronic components, sealing frames or other electronic components, Au, Ni, etc. Plating is applied.

【0004】[0004]

【発明が解決しようとする課題】しかしながら上記従来
技術を用いて製造された回路基板において、銅メタライ
ズとガラスセラミックの界面の接着強度は非常に低い。
そのためLSI等の機能性素子、電子部品の端子、封止
フレームあるいは他の電子部品を接続するための入出力
用ピンを半田接合した場合、わずかな外力によって銅と
ガラスセラミックの界面が容易に剥離し、これらの部材
がはずれてしまう。
However, in a circuit board manufactured by using the above-mentioned prior art, the bonding strength at the interface between the copper metallization and the glass ceramic is very low.
Therefore, when the input / output pins for connecting functional elements such as LSIs, terminals of electronic components, sealing frames or other electronic components are soldered, the interface between copper and glass ceramic is easily peeled off by a slight external force. Then, these members come off.

【0005】また上記従来技術を用いて製造された回路
基板において銅メタライズは、銅金属粉末の焼結の結果
得られるものであるため、表面及び内部に無数の粒界ボ
イドを有する。そのため、めっき工程、洗浄工程等の湿
式プロセスにおいて、回路基板表面銅メタライズの表面
のボイド中に薬液が残留し、回路基板表面銅メタライズ
の腐食の原因となる。また、めっき後の熱処理によって
ボイド中に残留した薬液が気化し、めっき膜の膨れや破
れの原因となる。
[0005] In addition, since copper metallization in a circuit board manufactured by using the above-mentioned prior art is obtained as a result of sintering of copper metal powder, it has countless grain boundary voids on the surface and inside. Therefore, in a wet process such as a plating step and a cleaning step, a chemical solution remains in voids on the surface of the copper metallized surface of the circuit board, causing corrosion of the copper metallized surface of the circuit board. In addition, the chemical solution remaining in the voids due to the heat treatment after plating is vaporized, which causes the plating film to swell or break.

【0006】そこで本発明の目的は高接着強度を有し、
かつ表面にボイドを有さない表面銅メタライズを有する
回路基板の製造方法を提供することにある。
Accordingly, an object of the present invention is to have a high adhesive strength,
Another object of the present invention is to provide a method for manufacturing a circuit board having a surface copper metallization having no voids on the surface.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に、本発明では、銅を主成分とする導体部と、銅の融点
以下の温度で焼結可能なガラスを主成分とする絶縁部か
らなるガラスセラミック多層回路基板を、導体部がマッ
ト面もしくはドラム面のいずれか一方を表面粗さRtを3
μm以上に加工した電解銅箔もしくは圧延銅箔を所望の
パターンに成形後、銅箔の表面粗さRtを3μm以上に加
工した面をグリーンシートとの接着面となるように積層
圧着する、もしくは銅箔の表面粗さRtを3μm以上に加
工した面をグリーンシートとの接着面となるように積層
圧着した後、銅箔を所望のパターンに形成して得られる
ガラスセラミック多層配線回路積層体を焼結することに
よって形成するようにした。
In order to achieve the above object, according to the present invention, a conductor portion mainly composed of copper and an insulating portion mainly composed of glass which can be sintered at a temperature lower than the melting point of copper. A glass-ceramic multi-layer circuit board made of a conductor having a matt surface or a drum surface with a surface roughness Rt of 3
After forming an electrolytic copper foil or rolled copper foil processed into a desired pattern into a desired pattern, the copper foil surface roughness Rt is laminated and pressure-bonded so that the surface processed into a surface of 3 μm or more becomes an adhesive surface with a green sheet, or After laminating and pressing the surface of the copper foil having a surface roughness Rt of 3 μm or more so as to be an adhesive surface with the green sheet, a glass ceramic multilayer wiring circuit laminate obtained by forming the copper foil into a desired pattern is obtained. It was formed by sintering.

【0008】また、本発明では、上記方法で製造された
ガラスセラミック多層配線回路基板とこのガラスセラミ
ック多層配線回路基板に搭載された半導体素子とを含ん
で電子デバイス実装体を構成した。
Further, in the present invention, an electronic device package is constituted including the glass ceramic multilayer wiring circuit board manufactured by the above method and the semiconductor element mounted on the glass ceramic multilayer wiring circuit board.

【0009】また、本発明では、マット面もしくはドラ
ム面のいずれか一方を表面粗さRtを3μm以上に加工し
た電解銅箔もしくは圧延銅箔をパターン形成後、銅箔の
表面粗さRtを3μm以上に加工した面をグリーンシート
との接着面となるように積層圧着して得られるガラスセ
ラミック多層配線回路積層体である。
In the present invention, after forming a pattern on an electrolytic copper foil or a rolled copper foil in which either the mat surface or the drum surface is processed to have a surface roughness Rt of 3 μm or more, the surface roughness Rt of the copper foil is reduced to 3 μm. This is a glass-ceramic multilayer wiring circuit laminate obtained by laminating and pressing the surface processed as described above to be an adhesive surface with a green sheet.

【0010】更に、本発明は、マット面もしくはドラム
面のいずれか一方を表面粗さRtが3μm以上に加工した
電解銅箔もしくは圧延銅箔を該銅箔の表面粗さRtを3μ
m以上に加工した面がグリーンシートとの接着面となる
ように積層圧着した後、銅箔を所望のパターンに形成し
て得られるガラスセラミック多層配線回路積層体であ
る。
Further, the present invention provides an electrolytic copper foil or a rolled copper foil in which either the mat surface or the drum surface is processed to have a surface roughness Rt of 3 μm or more, the surface roughness Rt of the copper foil is 3 μm.
This is a glass ceramic multilayer wiring circuit laminate obtained by laminating and pressing so that a surface processed to m or more becomes an adhesive surface with a green sheet, and then forming a copper foil in a desired pattern.

【0011】また、本発明は、上記ガラスセラミック多
層配線回路積層体を焼結することを特徴とするガラスセ
ラミック多層配線回路積層体の製造方法である。
Further, the present invention is a method for producing a glass ceramic multilayer wiring circuit laminate, which comprises sintering the above glass ceramic multilayer wiring circuit laminate.

【0012】即ち、本発明は、上記2つの課題を同時に
解決するために、マット面もしくはドラム面のいずれか
一方を表面粗さRtを3μm以上に加工した電解銅箔もし
くは圧延銅箔をパターン形成後、該銅箔の表面粗さRtを
3μm以上に加工した面をグリーンシートとの接着面と
なるように積層圧着して得られるセラミック多層配線回
路積層体、もしくは表面粗さRtを3μm以上に加工した
面をグリーンシートとの接着面となるように積層圧着し
た後、該銅箔を所望のパターンに形成して得られるガラ
スセラミック多層配線回路積層体を焼結することを特徴
とする。
That is, in order to simultaneously solve the above two problems, the present invention provides a method of forming an electrolytic copper foil or a rolled copper foil in which one of a mat surface and a drum surface is processed to have a surface roughness Rt of 3 μm or more. After that, the copper foil is processed to have a surface roughness Rt of 3 μm or more by laminating and pressing so as to be an adhesive surface with a green sheet, or a ceramic multilayer wiring circuit laminate or a surface roughness Rt of 3 μm or more. After laminating and pressing the processed surface so as to be an adhesive surface to the green sheet, a glass ceramic multilayer wiring circuit laminate obtained by forming the copper foil into a desired pattern is sintered.

【0013】本発明では銅箔を表面粗さRtを3μm以上
に加工し、該銅箔の加工面を接着界面とする事によりC
u/ガラスセラミック界面の接着面積が増大し、かつア
ンカー接合が形成される事によって高接着強度を得るこ
とが出来る。同時に電解銅箔もしくは圧延銅箔はボイド
を有さないので、焼結後の表面銅メタライズはボイドを
有さない。
In the present invention, the copper foil is processed to have a surface roughness Rt of 3 μm or more, and the processed surface of the copper foil is used as an adhesive interface, whereby C
A high bonding strength can be obtained by increasing the bonding area at the u / glass-ceramic interface and forming the anchor joint. At the same time, since the electrolytic copper foil or the rolled copper foil has no voids, the surface copper metallization after sintering has no voids.

【0014】[0014]

【発明の実施の形態】以下、本発明の実施例により具体
的に説明するが、本発明はこれら実施例に限定されな
い。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail with reference to Examples, but the present invention is not limited to these Examples.

【0015】ガラスセラミック多層配線基板の製造方法
は、まずグリーンシートを作成するためのスラリーをつ
くる。
In a method for manufacturing a glass ceramic multilayer wiring board, first, a slurry for forming a green sheet is prepared.

【0016】スラリーの製造方法は平均粒径3μmの軟
化温度820℃のホウケイ酸ガラス粉末63重量部に平
均粒径3μmのムライト粒子37重量部、アクリル系バ
インダ17重量部を加えボールミルで24h湿式混合し
て作製する。
The slurry is produced by adding 37 parts by weight of mullite particles having an average particle diameter of 3 μm and 17 parts by weight of an acrylic binder to 63 parts by weight of borosilicate glass powder having an average particle diameter of 3 μm and a softening temperature of 820 ° C., and wet-mixing with a ball mill for 24 hours. To make.

【0017】次に真空脱泡して適度に粘度を調節する。
次にこのスラリーをドクターブレードを用いて、ポリエ
ステルフィルム上に0.5μmの厚さに塗布しその後乾燥
してグリーンシートを作製した。
Next, the viscosity is adjusted appropriately by vacuum degassing.
Next, this slurry was applied on a polyester film to a thickness of 0.5 μm using a doctor blade and then dried to produce a green sheet.

【0018】次にこのグリーンシートにポンチで直径1
60μmの穴を450μm間隔で明け、銅ペーストを印
刷充填し、さらに銅ペーストの印刷により表面層、電源
層、配線層を形成した。
Next, the green sheet is punched with a diameter of 1 mm.
Holes of 60 μm were drilled at 450 μm intervals, copper paste was printed and filled, and a surface layer, a power supply layer, and a wiring layer were formed by printing the copper paste.

【0019】銅ペーストは平均粒径3μmの還元銅粉1
00重量部にバインダとしてエチルセルロース10重量
部と溶剤90重量部を混合し作製したビヒクル10重量
部加えたものを、らいかい機で30分混合し、さらに3
本ロールを数回通して混練し適当な粘度に調節し、穴埋
め印刷及びスクリーン印刷した。
The copper paste is reduced copper powder 1 having an average particle size of 3 μm.
10 parts by weight of ethyl cellulose as a binder and 90 parts by weight of a solvent were added to 00 parts by weight, and 10 parts by weight of a vehicle prepared was added thereto.
The roll was kneaded several times, kneaded and adjusted to an appropriate viscosity, and then filled and printed.

【0020】次にマット面に亜鉛合金化処理を施し、表
面粗さRtを3μmとしたゲージ厚さ18μmの電解銅箔
の両面にポリイミドテープを貼り硝酸により不要部をエ
ッチング除去した後、両面のポリイミドテープを剥離し
てパターン形成し、グリーンシート50枚と位置合わせ
した後、熱間プレスにより圧着した。圧着は、温度13
0℃、圧力150kgf/cm2とした。
Next, the matte surface is subjected to a zinc alloying treatment, and a polyimide tape is applied to both surfaces of an electrolytic copper foil having a surface roughness Rt of 3 μm and a gauge thickness of 18 μm, and unnecessary portions are removed by etching with nitric acid. The polyimide tape was peeled off to form a pattern, aligned with 50 green sheets, and pressed by a hot press. Crimping, temperature 13
0 ° C. and pressure 150 kgf / cm 2.

【0021】圧着したグリーンシートは脱脂のため、1
00℃/h以下の昇温速度で昇温し、850℃で10時
間保持した。雰囲気はバインダカーボンの除去が可能
で、かつ銅が酸化しないN2+H2O+H2雰囲気で行
った。その後雰囲気をN2に切り替え1000℃で2h
保持し、焼結緻密化させた。焼結中は、基板の反りを抑
え、また基板のXY方向の収縮率を制御するために2k
gf/cm2で加圧した。
The pressed green sheet is degreased to obtain 1
The temperature was raised at a temperature rising rate of 00 ° C./h or less and maintained at 850 ° C. for 10 hours. The atmosphere was an N2 + H2O + H2 atmosphere in which binder carbon could be removed and copper was not oxidized. After that, the atmosphere was switched to N2 at 1000 ° C for 2 hours.
Hold and sinter densify. During sintering, 2k is used to control the warpage of the substrate and to control the shrinkage of the substrate in the X and Y directions.
Pressure was applied at gf / cm2.

【0022】作製したセラミック基板の接着強度を調べ
たところ、ピール強度で1000gf/cmと良好であ
った。また基板表面の銅メタライズ表面からボイドを発
見することは出来なかった。
When the adhesive strength of the produced ceramic substrate was examined, the peel strength was as good as 1000 gf / cm. No void could be found on the copper metallized surface of the substrate surface.

【0023】実施例2 実施例1で作製したセラミック多層回路基板の裏面導体
パッドに無電解Niメッキした後600℃でシンターし
たところ、めっきの膨れ及び破れは全く見られなかっ
た。ついでAuSnはんだを用い、CuZr製の電気信
号入出力用ピンを1.6mm径の導体パッドにろう付け
したところ、、引っ張り強度が4kgf以上と良好であ
った(図2)。
Example 2 Electroless Ni plating was performed on the back surface conductive pads of the ceramic multilayer circuit board produced in Example 1 and then sintered at 600 ° C. As a result, no swelling or tearing of the plating was observed. Then, using an AuSn solder, a CuZr electric signal input / output pin was brazed to a 1.6 mm-diameter conductive pad. As a result, the tensile strength was as good as 4 kgf or more (FIG. 2).

【0024】実施例3 実施例1〜2で作製したガラスセラミック多層配線基板
1にはスルーホール3およびライン配線7が形成され
る。さらにこのガラスセラミック多層回路基板1の上面
に銅およびポリイミドを用いて薄膜多層回路8を形成
し、LSIチップ10をはんだ9により装着後、実施例
2の手順でピン付けを行う。このようにしてLSIチッ
プ10と接続を図ったモジュールの概略図を図3に示
す。
Embodiment 3 Through-holes 3 and line wirings 7 are formed in the glass ceramic multilayer wiring board 1 manufactured in Embodiments 1 and 2. Further, a thin-film multilayer circuit 8 is formed on the upper surface of the glass-ceramic multilayer circuit board 1 using copper and polyimide, and an LSI chip 10 is mounted by soldering 9 and then pinned according to the procedure of the second embodiment. FIG. 3 is a schematic diagram of a module connected to the LSI chip 10 in this manner.

【0025】[0025]

【発明の効果】本発明は以上説明したように構成されて
いるので以下に記載されるような効果を奏する。
Since the present invention is configured as described above, the following effects can be obtained.

【0026】すなわち、導体部と、導体部融点以下の温
度で焼結可能なガラスを主成分とする絶縁部からなるガ
ラスセラミック多層回路基板において、マット面もしく
はドラム面のいずれか一方を表面粗さRtを3μm以上に
加工した電解銅箔もしくは圧延銅箔をパターン形成後、
該銅箔の表面粗さRtを3μm以上に加工した面をグリー
ンシートとの接着面となるように積層圧着する、もしく
は表面粗さRtを3μm以上に加工した面をグリーンシー
トとの接着面となるように積層圧着して得られるセラミ
ック多層配線回路積層体表面の銅箔をパターン形成して
得られるガラスセラミック多層配線回路積層体を焼結さ
せた結果、Cu/ガラスセラミック界面の接触面積が増
大し、かつアンカー接合が形成されることにより高接着
強度を有し、ボイドを有さない表面銅メタライズを得る
事が出来る。
That is, in a glass-ceramic multilayer circuit board composed of a conductor portion and an insulating portion mainly composed of glass sinterable at a temperature equal to or lower than the melting point of the conductor portion, either the mat surface or the drum surface has a surface roughness. After forming a pattern of electrolytic copper foil or rolled copper foil with Rt processed to 3 μm or more,
The copper foil has a surface processed to a surface roughness Rt of 3 μm or more, and is laminated and pressed so as to be an adhesive surface with a green sheet, or a surface processed to a surface roughness Rt of 3 μm or more is an adhesive surface with a green sheet. As a result of sintering a glass-ceramic multilayer wiring circuit laminate obtained by patterning a copper foil on the surface of a ceramic multilayer wiring circuit laminate obtained by laminating and crimping, the contact area at the Cu / glass-ceramic interface increases. In addition, by forming the anchor joint, it is possible to obtain a surface copper metallized having high adhesive strength and having no void.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示す銅導体とガラスセラミ
ックの界面の拡大断面概要図である。
FIG. 1 is an enlarged schematic cross-sectional view of an interface between a copper conductor and a glass ceramic according to an embodiment of the present invention.

【図2】本発明の一実施例を示す電気信号入出力用ピン
を接合したガラスセラミック多層回路基板の断面概要図
である。
FIG. 2 is a schematic cross-sectional view of a glass-ceramic multilayer circuit board to which an electric signal input / output pin according to an embodiment of the present invention is joined.

【図3】本発明の一実施例を示すガラスセラミック多層
回路基板の断面概要図である。
FIG. 3 is a schematic cross-sectional view of a glass ceramic multilayer circuit board showing one embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1…ガラスセラミック基板、 2…銅導体、 3…スル
ーホール、 4…表面導体パッド、 5…AuSnろう
材、 6…電気信号入出力ピン、 7…ライン配線、
8…薄膜多層回路、 9…はんだ、 10…LSIチッ
プ。
DESCRIPTION OF SYMBOLS 1 ... Glass ceramic board, 2 ... Copper conductor, 3 ... Through-hole, 4 ... Surface conductive pad, 5 ... AuSn brazing material, 6 ... Electric signal input / output pin, 7 ... Line wiring,
8 ... Thin film multilayer circuit 9 ... Solder 10 ... LSI chip

フロントページの続き (72)発明者 阿美 徳宏 神奈川県横浜市戸塚区吉田町292番地株式 会社日立製作所生産技術研究所内Continuation of the front page (72) Inventor Norihiro Ami 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture, Hitachi, Ltd.

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】銅を主成分とする導体部と、銅の融点以下
の温度で焼結可能なガラスを主成分とする絶縁部からな
るガラスセラミック多層回路基板において、該導体部が
マット面もしくはドラム面のいずれか一方を表面粗さRt
を3μm以上に加工した電解銅箔もしくは圧延銅箔を所
望のパターンに成形後、該銅箔の表面粗さRtを3μm以
上に加工した面をグリーンシートとの接着面となるよう
に積層圧着する、もしくは該銅箔の表面粗さRtを3μm
以上に加工した面をグリーンシートとの接着面となるよ
うに積層圧着した後、該銅箔を所望のパターンに形成し
て得られるガラスセラミック多層配線回路積層体を焼結
することによって形成することを特徴とするガラスセラ
ミック多層配線回路基板の製造方法。
1. A glass ceramic multilayer circuit board comprising a conductor portion mainly composed of copper and an insulating portion mainly composed of glass which can be sintered at a temperature equal to or lower than the melting point of copper. Either of the drum surfaces has a surface roughness Rt
After forming into a desired pattern an electrolytic copper foil or a rolled copper foil processed to 3 μm or more, the copper foil is subjected to lamination pressing so that the surface processed to a surface roughness Rt of 3 μm or more becomes an adhesive surface with a green sheet. Or the surface roughness Rt of the copper foil is 3 μm
After the above-processed surface is laminated and pressed so as to be an adhesive surface with a green sheet, the glass ceramic multilayer wiring circuit laminate obtained by forming the copper foil into a desired pattern is formed by sintering. A method for manufacturing a glass-ceramic multilayer wiring circuit board, comprising:
【請求項2】請求項1記載の方法で製造されたガラスセ
ラミック多層配線回路基板と該ガラスセラミック多層配
線回路基板に搭載された半導体素子とを含んで構成され
る電子デバイス実装体。
2. An electronic device package comprising a glass ceramic multilayer wiring circuit board manufactured by the method according to claim 1 and a semiconductor element mounted on the glass ceramic multilayer wiring circuit board.
【請求項3】マット面もしくはドラム面のいずれか一方
を表面粗さRtを3μm以上に加工した電解銅箔もしくは
圧延銅箔をパターン形成後、該銅箔の表面粗さRtを3μ
m以上に加工した面をグリーンシートとの接着面となる
ように積層圧着して得られるガラスセラミック多層配線
回路積層体。
3. After forming a pattern on an electrolytic copper foil or a rolled copper foil having a surface roughness Rt of at least 3 μm on one of a mat surface and a drum surface, the surface roughness Rt of the copper foil is reduced by 3 μm.
A glass-ceramic multilayer wiring circuit laminate obtained by laminating and press-bonding a surface processed to m or more to be an adhesive surface with a green sheet.
【請求項4】マット面もしくはドラム面のいずれか一方
を表面粗さRtが3μm以上に加工した電解銅箔もしくは
圧延銅箔を該銅箔の表面粗さRtを3μm以上に加工した
面がグリーンシートとの接着面となるように積層圧着し
た後、該銅箔を所望のパターンに形成して得られるガラ
スセラミック多層配線回路積層体。
4. An electro-deposited copper foil or a rolled copper foil in which either the matte surface or the drum surface is processed to have a surface roughness Rt of 3 μm or more, the surface in which the surface roughness Rt of the copper foil is processed to be 3 μm or more is green. A glass-ceramic multilayer wiring circuit laminate obtained by laminating and pressing to form an adhesive surface with a sheet and then forming the copper foil into a desired pattern.
【請求項5】請求項3または4記載のガラスセラミック
多層配線回路積層体を焼結することを特徴とするガラス
セラミック多層配線回路積層体の製造方法。
5. A method for manufacturing a glass ceramic multilayer wiring circuit laminate, comprising sintering the glass ceramic multilayer wiring circuit laminate according to claim 3.
JP10136299A 1998-05-19 1998-05-19 Manufacture of glass ceramic multilayer wiring circuit board, glass ceramic multilayer wiring circuit laminate and its manufacture Pending JPH11330697A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10136299A JPH11330697A (en) 1998-05-19 1998-05-19 Manufacture of glass ceramic multilayer wiring circuit board, glass ceramic multilayer wiring circuit laminate and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10136299A JPH11330697A (en) 1998-05-19 1998-05-19 Manufacture of glass ceramic multilayer wiring circuit board, glass ceramic multilayer wiring circuit laminate and its manufacture

Publications (1)

Publication Number Publication Date
JPH11330697A true JPH11330697A (en) 1999-11-30

Family

ID=15171945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10136299A Pending JPH11330697A (en) 1998-05-19 1998-05-19 Manufacture of glass ceramic multilayer wiring circuit board, glass ceramic multilayer wiring circuit laminate and its manufacture

Country Status (1)

Country Link
JP (1) JPH11330697A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140322520A1 (en) * 2011-12-29 2014-10-30 Minshe Su Circuit substrate and manufacturing method thereof
EP3621418A1 (en) * 2018-08-30 2020-03-11 Nichia Corporation Wiring board manufacturing method and wiring board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140322520A1 (en) * 2011-12-29 2014-10-30 Minshe Su Circuit substrate and manufacturing method thereof
US9744745B2 (en) * 2011-12-29 2017-08-29 Shengyi Technology Co., Ltd. Circuit substrate and manufacturing method thereof
EP3621418A1 (en) * 2018-08-30 2020-03-11 Nichia Corporation Wiring board manufacturing method and wiring board

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