JPH11317456A - Fpga - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily enable FPGA to be replaceable with an ASIC by making the arrangement and wiring of the internal logic of the EFGA easy through making a terminal arrangement containing a power source and a ground freely programmable. SOLUTION: An FPGA is composed of an internal logic section 10 and an input-output section 20. The internal logic section 10 is composed of a programmable gate array using a SRAM technology by which processes can be divided minutely relatively easily and can be integrated highly/reprogrammed. The input-output section 20 has a programmable wiring region, an input-output buffer, and an input-output pad formed by the use of the anti-fuse technology. Consequently, the wiring of a power source, ground, etc., can be selected freely in the FPGA, and since the wiring of the input-output section 20 becomes hard wires after the programming and is becomes much like the timing characteristic of an ASIC, the FPGA can be replaced easily with the ASIC from the aspect of timing design. Therefore, the operating stability of a chip can be made to improve.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an FPGA.

[0002]

2. Description of the Related Art Conventionally, an application-specific integrated circuit A
SIC (Application Specific)
(Integrated Circuit) is used. However, in developing such an ASIC, an integrated circuit that realizes a function desired by a user is designed, an ASIC for evaluation is manufactured through various processes, and an evaluation result and a function change are reflected. Then, the ASIC will be manufactured again through various processes. If such a process is adopted, the development period is lengthened, which is not practical.

Therefore, in reality, an FPGA (Field) that allows a user to easily program a functional configuration is proposed.
d Programmable Gate Arra
y) is often used. Using this FPGA,
For example, by performing trial manufacture of an ASIC or the like, it is possible to shorten a development period and the like, and to achieve early introduction of a product to the market.

[0004] When an FPGA is used as described above, the FPGA is replaced with an ASIC when the operation verification on the FPGA is completed, or when the product goes on track.

[0005]

The conventional FP
In the GA, the arrangement of the power supply and the ground pin is fixed. However, the arrangement of the standard power supply and the ground pin of the ASIC is different for each manufacturer or device. For this reason, the arrangement of the power supply and ground pins of the FPGA
Often, the arrangement of the standard power supply and ground pins does not match. Therefore, replacing an FPGA with an ASIC involves redesigning the board. In this case, there is a problem that the development period is prolonged due to the redesign period and the like, which leads to an increase in cost.

Further, in the conventional FPGA, since the arrangement of the power supply and the ground pin is fixed, it is not possible to add a power supply and the ground pin and take a means for stabilizing the operation.
Also from this point, there is a problem that the FPGA cannot be easily replaced with the ASIC.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has been made in consideration of the above circumstances.
A is intended to be provided.

[0008]

SUMMARY OF THE INVENTION The present invention provides an ASIC (A
application Specific Integra
FPGA (Field Program) that allows the standard power supply and the position of the ground pin and the like to be programmable in order to enable physical replacement with a rate circuit (rate circuit).
mmable Gate Array).

As will be described later with reference to FIG. 1, after programming, the wiring becomes low impedance, and an antifuse or fuse technology that is advantageous for power supply and ground supply is used for the input / output section, and reprogramming is possible and the logic can be changed freely. SRAM or EEPROM technology is used for internal logic.

According to the present invention, since the standard power supply and the ground pin arrangement are programmable, the power supply and the ground in the FPGA can be strengthened, and a bypass capacitor can be built in. Further, since physical migration to the ASIC is possible, redesign of the board is not required when replacing the ASIC.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic top view of an embodiment of an FPGA according to the present invention.

As shown in FIG. 1, the FPGA of this embodiment is roughly composed of an internal logic unit 10 and an input / output unit 20.

The internal logic unit 10 is a programmable gate array using SRAM technology, which is relatively easy to miniaturize the process and is highly integrated / reprogrammable.
The advantage of the conventional FPGA is not lost.

The input / output unit 20 has a programmable wiring area using an antifuse technology, an input / output buffer, and an input / output pad. The wiring impedance after programming is low, sufficient for power supply and the like, and has good timing characteristics.

The wiring of the input / output unit 20 becomes a hard wire after programming, and is very similar to the timing characteristics of the ASIC. Therefore, the transition to the ASIC is easy from the viewpoint of the timing design.

Next, the operation of this embodiment will be described.

FIG. 2 is a diagram showing an example of the configuration of an input / output pad provided in the input / output unit 20 shown in FIG.

Reference numerals 1, 2, 3 and 4 denote antifuse type wiring program elements (hereinafter, referred to as antifuse elements) as switching means. The antifuse elements 1, 2, 3, and 4 are in an insulated state by amorphous Si or the like before programming, and are rendered conductive by applying an overvoltage according to the program. As a result, it is possible to program the connection and non-connection of the wires connected to both ends of the antifuse elements 1, 2, 3 and 4.

As shown in FIG. 2, the input / output pad 5 is connected to the power supply layer via the anti-fuse element 1, connected to the ground layer via the anti-fuse element 2, and provided with the input / output buffer and the anti-fuse element 3. , 4 via an internal logic SRAM element.

Accordingly, when an overvoltage is applied only to the antifuse element 1, the input / output pad 5 becomes a power supply pad. When an overvoltage is applied, the input / output pad 5 becomes an input pad, and when an overvoltage is applied only to the antifuse element 4, the input / output pad 5 becomes an output pad, and the antifuse element 3
When an overvoltage is applied only to the input and output pads 4, the input / output pad 5 becomes a bidirectional pad.

The internal logic and wiring program elements are SRAMs and can be reprogrammed.

According to the present embodiment, by arranging the input / output pads 5 as shown in FIG. 2 everywhere in the input / output section 20 as shown in FIG. You will be able to choose freely.

FIG. 3 is a diagram showing another example of the configuration of the input / output pads provided in the input / output unit 20 shown in FIG.

This example is an example in which measures are taken to further stabilize the supply of power and ground.
And the power supply layer are connected by a plurality of wirings and antifuse elements, and the input / output pad 5 and the ground layer are connected by a plurality of wirings and antifuse elements.

For example, when the minute resistance of the program element cannot be tolerated, as shown in FIG. 3, it can be dealt with by developing wirings in parallel from the program element near the pads. That is, for example, the input pad 5 can be a stable power supply pad by applying an overvoltage to only a plurality of antifuse elements provided on a plurality of wirings between the input / output pad 5 and the power supply layer.

FIG. 4 shows an example in which a bypass capacitor arranged on a conventional board is incorporated in a chip, and a required number of bypass capacitors can be added as required according to logic and terminal arrangement, thereby improving the operation stability. It is a figure and shows the added value and possibility of making a power supply and a ground programmable.

The input / output programming method may be, for example, a fuse technology in addition to the antifuse technology.

Further, a method of programming the internal logic is as follows.
In addition to those using SRAM, for example, EEPRO
M, an antifuse, a fuse or the like may be used.

The antifuse element does not use amorphous Si but may use an ONO film.

[0031]

As described above, according to the present invention,
Since the terminal arrangement including power supply and ground can be freely set, FP
The arrangement and wiring of the GA internal logic becomes easy.

Further, since the terminals including the power supply and the ground can be freely arranged, the power supply and the ground of the FPGA can be strengthened, and the operation stability of the chip can be improved.

Further, since the terminal arrangement including the power supply and the ground can be freely arranged, the terminal arrangement can be the same as that of the ASIC to be replaced in the future, and it is not necessary to redesign the board at the time of replacement.

Further, the wiring of the input / output unit becomes a hard wire after programming, and is very similar to the timing characteristics of the ASIC. Therefore, the transition to the ASIC is easy from the viewpoint of timing design.

An SRAM which can be reprogrammed into the internal logic and can be easily used in a general semiconductor process.
By using the element, fine, high integration and flexible logic change can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic top view of an embodiment of an FPGA according to the present invention.

FIG. 2 is a diagram illustrating an example of a configuration of an input / output pad provided in the input / output unit illustrated in FIG. 1;

FIG. 3 is a diagram showing another example of the configuration of the input / output pad provided in the input / output unit shown in FIG.

FIG. 4 is a diagram showing an example in which a bypass capacitor arranged on a conventional board is incorporated in a chip, and a required number of bypass capacitors can be appropriately added according to logic and terminal arrangement to improve operation stability. .

[Explanation of symbols]

 Reference Signs List 10 internal logic section 20 input / output section 1, 2, 3, 4 antifuse element 5 input / output pad

Claims (8)

[Claims] An FPGA wherein the arrangement of power supply terminals is freely programmable. 2. The FPGA according to claim 1, wherein the arrangement of the ground terminals is freely programmable. 3. An FPGA characterized in that physical and logical input / output timing characteristics are compatible with the ASIC. 4. A semiconductor device having a built-in bypass capacitor. 5. An electronic apparatus comprising: an internal logic unit and an input / output unit;
An FPG comprising a plurality of pads connected to a power supply via a first switch means and connected to a ground via a second switch means at various places of the input / output unit.
A. 6. The pad and the power supply are connected by a plurality of wirings connecting a plurality of switch means in parallel, and the pad and the ground are connected by a plurality of wirings connecting a plurality of switch means in parallel. The FPGA according to claim 5, wherein: 7. The FP according to claim 5, wherein said switch means is an anti-fuse element.
GA. 8. The FPGA according to claim 7, wherein the antifuse element is an element using amorphous Si.