JP2004007017A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily provide an system LSI by employing a semiconductor device in which a plurality of LSI chips are sealed in a resin. <P>SOLUTION: A pad electrode 15 for connection to a lead 9 and a pad electrode 125 for an internal interface are provided on the main surfaces of an LSI chip 103.The pad electrodes 115 and 125 of the LSI chips 113 arranged on the main surface are electrically connected together with a wire 117. Thus part of such circuit as required as an system LSI, which is not provided by the LSI chip 103, is mounted on the LSI chip 113, to realize a wanted function as a system LSI using two LSI chips. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to a semiconductor device in which a plurality of semiconductor elements are sealed with a resin.

2. Description of the Related Art Conventionally, a semiconductor device is generally formed by sealing a semiconductor element (hereinafter, referred to as an LSI chip) containing a large-scale integrated circuit (hereinafter, referred to as an LSI) in which a plurality of circuits are integrated with a resin. is there.

FIG. 16 is a cross-sectional view showing the internal structure of the conventional semiconductor device 1. As shown in FIG. 16, the LSI chip 3 is fixedly arranged on the die 8 with an adhesive. The plurality of pad electrodes 5 arranged on the main surface of the LSI chip 3 are electrically connected to leads 9 made of a conductive material to be terminals for connection to the outside by wires 7 which are thin metal wires. Part of the LSI chip 3, the pad electrode 5, the die 8, the wire 7, and the part including the connection part with the wire 7 (the part called the inner lead) is sealed with an insulating resin 10. A part of the lead 9 derived from the resin 10 (a part referred to as an outer lead) is electrically connected to another device via a printed circuit board, for example, to transmit and receive signals.

The LSI chip 3 realizes a composite function of, for example, a core of a central processing unit (hereinafter, referred to as a CPU) such as a microcomputer, a memory, and a circuit for other peripheral functions. In the case of a system LSI that performs these functions, these functions are mixedly mounted on the same semiconductor substrate. Therefore, when a DRAM (Dynamic Random Access Memory) or a batch erasable EEPROM (Electrically Erasable Read Only Memory) is mounted as a memory in the system LSI, a circuit for a CPU core and peripheral functions is provided. A specific manufacturing process that is not included in a manufacturing process for realizing the process (hereinafter, referred to as a Logic process) is required. As a result, in order to realize such a system LSI, a unique manufacturing process (a process for mixing a Logic and a memory) is applied to develop a product.

In recent years, a semiconductor device in which a plurality of LSI chips are encapsulated with a resin and commercialized (that is, a plurality of semiconductor elements are housed in one package) has appeared. Such a semiconductor device is called an MCP (Multiple Chip Package) type. The MCP type semiconductor device is applied as a memory LSI. For example, by storing the same type of memory in one package, the memory capacity can be increased, or a type of memory having a different function can be stored in one package. It is applied to realize space saving by storing in one package.

FIG. 17 is a cross-sectional view showing the internal structure of the MCP type semiconductor device 11, and FIG. 18 is a plan view showing the internal structure of the MCP type semiconductor device 11. 17 and 18, structural elements similar to those in FIG. 16 are denoted by the same reference numerals.

、 As shown in FIGS. 17 and 18, on the die 8, the LSI chip 3 fixed and arranged by the adhesive is mounted. On the main surface of the LSI chip 3, a plurality of pad electrodes 5 electrically connected to the leads 9 by wires 7 are arranged. Further, the LSI chip 13 is fixedly arranged on the main surface of the LSI chip 3 via an insulating adhesive. A plurality of pad electrodes 15 are arranged on the main surface of the LSI chip 13, and each of the pad electrodes 15 is electrically connected to a corresponding one of the leads 9 by a wire 17. The die 8 and a part of these two LSI chips 3 and 13, including the connection portions of the leads 9 with the wires 7 and 17, are sealed with a resin 10.

As described above, the MCP type semiconductor device 11 has a configuration in which the plurality of LSI chips 3 and 13 are housed in one package, and each of the LSI chips 3 and 13 has a lead 9 for connection to the outside.

Ｍ As such a semiconductor device 11 compatible with MCP, for example, there is a device such as BGA (Ball Grid Array). That is, different types of memories such as an SRAM (static random access memory) and an erasable EEPROM can be housed in one package, and the input / output terminals of each memory are individually set so that the memories operate independently. The structure is such that it is connected to the lead 9. With such a configuration, the functions of two LSI chips can be realized in the space of one LSI chip.

As described above, in an LSI built in a semiconductor device, particularly a system LSI, product development is performed by applying a mixed mounting process. In a memory LSI, an MCP type semiconductor device is used to reduce a memory capacity. Product development is being performed by increasing the number of different types of memories and by combining different types of memories.

However, a semiconductor device on which a system LSI is mounted is manufactured on a single semiconductor substrate by a specific process incorporating a memory-specific manufacturing process and a Logic process, and thus has the following problems.

(1) First, the number of masks is increased as compared with a manufacturing process using Logic alone or a manufacturing process using only memory, so that the yield is reduced. Second, since it is a unique process, it cannot easily cope with an improvement in the performance of the circuit in the Logic part and an improvement in the performance of the memory part. Third, the TAT is lengthened due to the complexity of the manufacturing process. Fourth, since the manufacturing process becomes complicated and the number of masks increases, the process cost increases. Fifth, an LSI composed of an SOI (Silicon On Insulator) process pursuing a low voltage / low current operation and an LSI composed of a special process for fabricating a high voltage element element (such as a high voltage MOS transistor) are mixed. It is technically very difficult to develop a process for such an LSI.

In particular, in the future, in LSIs to which a finer and deeper sub-micron manufacturing process is applied, lowering the voltage (about 0.8 to 1.5 V) will be accelerated even in the Logic process. In this case, a plurality of voltages including a high voltage (for example, 8 to 12 V) higher than a power supply voltage (for example, 3.3 V or 5 V) are required at the time of rewriting or reading data, such as an EEPROM that can be erased at once. Therefore, it becomes difficult to realize a system LSI (such as a microcomputer with a memory that can be erased in a batch) configured by incorporating a high withstand voltage process for forming a high withstand voltage element element and a Logic process.

As described above, since the purpose of the MCP type semiconductor device is to increase the memory capacity and save space, the same type of memory system LSI is housed in one package or different types of memory system LSIs are integrated. This is limited to providing a lead for each LSI so that the LSIs are housed in a single package and different types of memory LSIs operate independently. For this reason, there is no MCP type semiconductor device that realizes a system LSI.

The object of the present invention is to solve the above problems and to easily realize a system LSI with a semiconductor device in which a plurality of LSI chips are sealed with resin.

Further, the present invention solves a problem that occurs when a system LSI is realized by a semiconductor device in which a plurality of LSI chips are sealed with resin, and does not impair the function of the system LSI as compared with the related art. It is intended to be realized.

Means taken by the present invention to solve the above-mentioned problem is to provide a semiconductor device in which a first semiconductor element and a second semiconductor element are sealed with a resin in a main surface of the first semiconductor element. A plurality of circuits arranged and electrically connected to any of a plurality of circuits provided in the first semiconductor element, and electrically connected to corresponding ones of a plurality of terminals for connection to the outside; A first pad electrode and a plurality of second pad electrodes disposed on a main surface of the first semiconductor element and each electrically connected to any one of a plurality of circuits provided in the first semiconductor element; Are arranged on the main surface of the second semiconductor element, each is electrically connected to a circuit provided in the second semiconductor element, and is electrically connected to a corresponding one of the second pad electrodes. A third pad electrode, and the first semiconductor element has a third pad electrode. By using the circuit provided in the semiconductor device, in which so as to perform a predetermined function.

With such a configuration, in the semiconductor device of the present invention, the circuit provided in the first semiconductor element and the circuit provided in the second semiconductor element include the second pad electrode and the third pad electrode. By electrically connecting the two devices, signals can be transmitted and received, and one function as a system LSI can be realized by these two semiconductor elements. For this reason, the first semiconductor element and the second semiconductor element can be manufactured separately, and the above problem can be solved.

In the present invention, the arrangement of the second pad electrode, the supply of a power supply voltage or a ground voltage in the second semiconductor element, and the selection means for selecting whether to use a circuit provided in the second semiconductor element By devising the arrangement and the like, it is also possible to solve the problems caused when the system LSI is realized by the MCP type semiconductor device.

According to the semiconductor device of the present invention, a system LSI can be easily realized by a semiconductor device in which a plurality of LSI chips are sealed with resin.

Further, according to the semiconductor device of the present invention, it is possible to further solve a problem that occurs when the system LSI is realized by a semiconductor device in which a plurality of LSI chips are sealed with a resin. It can be realized without impairing the functions.

The semiconductor device of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view showing the internal structure of an MCP type semiconductor device 100 according to the first embodiment of the present invention, and FIG. 2 is a plan view showing the internal structure of the semiconductor device 100. In FIG. 1, the same components as those in FIGS. 16 to 18 are denoted by the same reference numerals.

1 and 2, the semiconductor device 100 has an LSI chip 103 as a first semiconductor element and an LSI chip 113 as a second semiconductor element. The LSI chip 103 and the LSI chip 113 have a similar shape (in the present invention, a rectangular shape).

(4) The LSI chip 103 is fixedly disposed on a substantially central region of the die 8 with an adhesive provided between the back surface of the LSI 103 and the die 8. A plurality of first pad electrodes 105 are arranged on the main surface of the LSI chip 103. In the first embodiment, the pad electrodes 105 are arranged on two parallel sides of the LSI chip 103, respectively.

On the main surface of the LSI chip 103, a plurality of second pad electrodes 125 are further arranged. Each pad electrode 125 is arranged at an arbitrary position around the area where the LSI chip 113 is arranged.

(4) The LSI chip 113 smaller in size than the LSI chip 103 is fixedly disposed on a substantially central region of the LSI chip 103 with an adhesive provided between the back surface of the LSI 113 and the main surface of the LSI chip 103. In order to avoid unnecessary electrical connection with the LSI chip 113, it is preferable that the main surface of the LSI chip 103 is formed of an insulating protective film. A plurality of third pad electrodes 115 are arranged on the main surface of the LSI chip 113. In the first embodiment, the pad electrodes 115 are aligned on two sides of the LSI chip 113 (the side on which the second pad electrode 125 is disposed).

(4) Each of the plurality of first pad electrodes 105 is electrically connected to the corresponding lead 9 by a wire 107. Each of the plurality of second pad electrodes 125 is electrically connected to one of the corresponding plurality of third pad electrodes 115 by a wire 117.

一部 Parts of the LSI chips 103 and 113, the die 8, the wires 107 and 117, and the leads 9 including the connection portions with the wires 107 are sealed with the resin 10.

FIG. 3 is a perspective view illustrating the assembly of the semiconductor device in FIG. In FIG. 3, the leads 9 and the wires 107 are partially omitted because they are used for explaining the assembly. As shown in FIG. 3, first, an LSI chip 103 having a first pad electrode 105 and a second pad electrode 125 is prepared. At this time, at the time of manufacturing the LSI chip 103, the pad electrode 125 is arranged around the area 103a on the main surface on which the LSI chip 113 is to be mounted later. The LSI chip 113 is separately manufactured and prepared independently of the manufacture of the LSI chip 103. At this time, the arrangement of the pad electrodes 115 is set in accordance with the positions where the pad electrodes 125 are arranged, in order to more easily perform wire bonding performed later and to prevent short-circuiting between the wires. It is good to be done. The arrangement of the pad electrodes 125 and the arrangement of the pad electrodes 115 in each of the LSI chips are determined in advance at the time of designing a circuit layout in the LSI chip in which one of the pad electrodes is arranged. By doing so, it is possible to easily cope with an LSI chip on which the other pad electrode is arranged.

After the first pad electrode 105 of the LSI chip 103 and the lead 9 are electrically connected by the wire 107, the LSI chip 113 is mounted on a predetermined area 103a on the main surface of the LSI chip 103 where the LSI chip 113 is to be arranged. Thereafter, the electrical connection between the pad electrode 115 and the pad electrode 125 is performed by wire bonding. The manufacturing method is not limited to this. Before the first pad electrode 105 of the LSI chip 103 and the lead 9 are electrically connected by the wire 107, the LSI chip 113 is connected to the main surface of the LSI chip 103. Is mounted on a predetermined area 103a to be arranged, and thereafter, the first pad electrode 105 and the lead 9 are electrically connected by the wire 107 and the pad electrode 115 and the pad electrode 125 are electrically connected by the wire 117. May be performed. The latter can be expected to be more efficient because the wire bonding process can be performed collectively.

As described above, in the semiconductor device according to the first embodiment, after the LSI chip 103 and the LSI chip 113 are independently developed and manufactured, signals are transferred between the two LSI chips to the LSI chip 103. By using the pad electrode 125 provided, one function (function as a system LSI) is realized.

A typical example of a system LSI applied to the semiconductor device of the present invention will be described using a microcomputer equipped with a batch erasable EEPROM. FIG. 4 is a block diagram showing a configuration of a microcomputer 50 having an EEPROM that can be erased at once.

As shown in FIG. 4, such a microcomputer 50 includes a CPU 51, peripheral functions such as a timer 58 and a serial-parallel conversion circuit 59, an SRAM 55 used for holding and transmitting data, and a program memory for storing various instructions. , An erasable EEPROM 53 and an input / output interface unit 57.

These components are connected to each other so that signals can be transmitted and received through a large number of signal lines and buses. The common bus 56 is used for transferring an output signal of the timer 58 via a signal line 66 and for transferring an output signal from a serial-parallel conversion circuit via a signal line 67. The common bus 56 exchanges data with the CPU 51 via a signal line 61, and is used to exchange addresses and data with the SRAM via a signal line 62. The signal line 63 transmits a control signal such as a write instruction signal output from the CPU 51 to the SRAM 55. The input / output interface unit 57 transmits data received from the outside via a signal line 69 to the CPU via a signal line 64, and transmits a control signal from the CPU 51 to the interface unit 57. It is used for transmitting data read from the SRAM 55 to the interface unit 57 and receiving a signal transmitted from the interface unit 57. The interface unit 57 exchanges signals such as data with the outside via a signal line 69.

The EEPROM 53 sends a program such as a stored command to the CPU 51 by using the signal line 68. Also, a desired program is selected according to the address sent from the CPU 51 via the signal line 68. That is, the signal line 68 includes a plurality of signal lines such as an address bus, a data bus, a memory control signal, and a power supply line for the EEPROM 53.

In the semiconductor device 100 according to the first embodiment of the present invention, the LSI chip 113 is a memory LSI on which the EEPROM 53 of FIG. 4 is mounted, and the LSI chip 103 is other than that of FIG. This is a Logic LSI on which components are mounted.

Therefore, the plurality of pad electrodes 115 of the LSI 113 and the plurality of pad electrodes 125 of the LSI 103 are used for transmitting and receiving signals similar to those of the signal line 68 in FIG. In other words, by electrically connecting the plurality of pad electrodes 115 of the LSI 113 and the plurality of pad electrodes 125 of the LSI 103 using the wires 117, transmission and reception of signals similar to those of the signal line 68 can be realized.

As described above, the second pad electrode 125 provided on the LSI chip 103 becomes an electrode pad used for interfacing with the LSI chip 113, and the transmission and reception of signals to and from the LSI chip 113 using the pad electrode 125. By doing so, it becomes possible to operate as a microcomputer equipped with an EEPROM capable of batch erasure. Further, the lead 9 does not cause any new restriction on the number and arrangement of the conventional leads, and may be the same as the conventional one.

In the first embodiment of the present invention, the operation as one microcomputer can be realized by using two LSI chips of the LSI chip 103 and the LSI chip 113 housed in one package. Therefore, the following effects are obtained in the semiconductor device according to the first embodiment of the present invention.

(4) Since the LSI chip 103 serving as the first semiconductor element and the LSI chip 113 serving as the second semiconductor element can be manufactured individually, the manufacturing of each LSI chip can be performed in parallel. Therefore, the TAT for development and manufacturing can be shortened.

Also, since the LSI chip 103 can be manufactured by a Logic process and the LSI chip 113 can be manufactured by a memory-specific process, there is no need to develop a mixed mounting process combining the Logic process and the memory process. In particular, it is possible to combine an LSI composed of a high withstand voltage process unique to an LSI requiring an element element with a high withstand voltage, such as an EEPROM capable of batch erasing, and an LSI composed of an SOI process. Development becomes feasible.

(4) It is realized by stacking the LSI chips, and the arrangement and the number of the leads 9 may be the same as those of the LSI chip 103 which is one semiconductor element. For this reason, the size of the semiconductor device does not increase, and there is no need to newly develop a lead frame, and the semiconductor device manufactured by the conventional mixed mounting process can be applied as it is.

Here, in the commercialization of microcomputers, when one function is realized by mixing a circuit part that is hardware such as a CPU or a DSP (Digital Signal Processor) with a program memory that is software, the same function is realized. In doing so, as the program memory, a product using a mask ROM in which software (program) is fixed (hereinafter referred to as a mask ROM version microcomputer) and an EEPROM whose software can be changed even after the program memory is incorporated in the LSI are used. A form having a product (hereinafter referred to as an EEPROM version microcomputer) is generally used. In addition, an OTP (One Time Programming) in which an EPROM is mounted for software and a window for irradiating ultraviolet rays is provided in the package, or a program can be written only once without providing this window. There are also version microcomputers.

Generally, the EEPROM version microcomputer can be written to the EEPROM even after the EEPROM as the program memory is incorporated in the LSI, that is, can rewrite software, so that it is applied to obtain the following effects. I have.

First, software development and debugging can be supported until just before the shipment of microcomputer products. Second, since the software can be rewritten after shipment of the microcomputer product, it is possible to cope with the occurrence of software bugs and to cope with product improvement (version upgrade, etc.).

That is, the EEPROM version microcomputer is used for product development for a new field that requires rewriting of a program for the purpose of shortening the TAT of the product development or improving the functions.

However, since the EEPROM version microcomputer uses a higher voltage than the power supply voltage for data writing and the like, it requires a special manufacturing process and tends to increase the product cost.

On the other hand, the mask ROM version microcomputer uses a mask used in a general Logic process such as a metal layer, a contact layer, and an implant layer, although there is a slight difference depending on the type of the mask ROM to be mounted. It can be manufactured by manufacturing a fixed program code mask. For this reason, since the mask ROM version microcomputer does not require a special manufacturing process, the product cost can be reduced (about 1/2 to 1/3 of the product cost of the EEPROM version microcomputer).

た め Due to such a difference in product cost, the EEPROM version microcomputer and the mask ROM version microcomputer are generally applied as follows.

First, when developing a microcomputer product, use an EEPROM version microcomputer to enable program rewriting. Hardware and software are debugged by making the program rewritable.

(4) Immediately after mass production of microcomputer products starts, apply EEPROM version microcomputers for mass production. This is to make it possible to deal with a program bug that may occur in the unlikely event of a program.

(4) After shipping the product as an EEPROM version microcomputer, check the market performance (program bug occurrence status, etc.), and switch from the EEPROM version microcomputer to a mask ROM version microcomputer that can realize the same function in a stable situation.

As described above, the EEPROM version microcomputer is applied at the time of development and at the initial stage of mass production shipment. For this reason, considering the lifetime shipment quantity of this kind of microcomputer, the mask ROM version microcomputer is overwhelmingly more than the EEPROM version microcomputer.

Therefore, when considering the development of a microcomputer having new functions, it is necessary to develop not only a mask ROM version microcomputer but also an EEPROM version microcomputer whose mass production quantity is small. Therefore, when a microcomputer having a new function is released, the TAT, the development man-hour, and the development cost are each increased. In particular, an EEPROM version microcomputer whose mass production quantity is small has a poor investment efficiency.

Also, since the EEPROM version microcomputer and the mask ROM version microcomputer must be able to realize the same function, the EEPROM version microcomputer must realize various characteristics equivalent to the mask ROM version microcomputer in the final form. No. These characteristics include not only electrical characteristics and functions, but also current consumption, latch-up characteristics, noise characteristics, and the like. Unless the EEPROM version microcomputer and the mask ROM version microcomputer have substantially the same characteristics, there arises a problem that the EMC standard differs. For example, when replacing an EEPROM version microcomputer with a mask ROM version microcomputer, the operation margin becomes larger, the noise becomes larger, the accuracy of the analog circuit built into the microcomputer changes, and readjustment is required. Problems, such as changing the duration of the battery.

In the second embodiment, the semiconductor device according to the first embodiment of the present invention is applied, and further, the above-mentioned problems occurring between the EEPROM version microcomputer and the mask ROM version microcomputer are solved. To provide an improved version. Hereinafter, a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings. FIGS. 5 and 6 are plan views of a semiconductor device according to the second embodiment of the present invention. FIG. 5 is a diagram of a semiconductor device as an EEPROM version microcomputer, and FIG. 6 is a diagram of a semiconductor device as a mask ROM version microcomputer. FIGS. 5 and 6 correspond to FIG. 2, and the same components as those in FIG. 2 are denoted by the same reference numerals.

In FIG. 5, an EEPROM as a program memory is mounted on the LSI chip 213. The LSI chip 203 on which the LSI chip 213 is arranged on the main surface has a mask ROM as a program memory mounted thereon, and all circuits required as a microcomputer other than the program memory are mounted.

Each of the plurality of pad electrodes 225 disposed on the main surface of the LSI chip 203 is electrically connected to a corresponding one of the plurality of pad electrodes 215 disposed on the main surface of the LSI chip 213 by a wire 217. I have to. Each of the leads 9 is electrically connected to a corresponding one of the pad electrodes 205 by a wire 207.

Here, on the LSI chip 203, one of the first pad electrodes 205 is provided with a selection pad electrode 205a. In the EEPROM version microcomputer in FIG. 5, the pad electrode 205a is electrically connected to the power supply voltage lead 9a via a wire 207a. The power supply voltage lead 9a is also connected to the power supply voltage pad electrode 205 in the LSI chip 207.

(6) The mask ROM version microcomputer shown in FIG. 6 does not have the LSI chip 213. Therefore, none of the pad electrodes 225 is wire-bonded. The LSI chip 203 has a mask ROM 222 mounted thereon. The pad electrode 205a is not wire-bonded to the power supply voltage lead 9a.

Here, the relationship between the pad electrode 205a of the LSI chip 203 and a circuit mounted inside the LSI chip 203 will be described. FIG. 7 is a diagram showing a circuit of the LSI chip 203 connected to the pad electrode 205a.

In FIG. 7, the pad electrode 205a is connected to the grounded pull-down resistor 251 and to one input terminal of the AND gate 253. A reset signal RES for initialization of the microcomputer is input to the other input terminal of the AND gate 253 via the delay buffer 257. An output terminal of the AND gate 253 is connected to an input terminal D of a latch circuit (hereinafter referred to as LAT) 255. A reset signal RES is input to a clock terminal of the LAT 255. The output signal of the LAT 255 is input as a selection signal SEL to an internal circuit described later. Note that in FIG. 7, a flip-flop may be used as the LAT 255. Note that the AND gate 253 may not be provided, but it is preferable to provide the AND gate 253 in order to stabilize the potential level of the signal input to the input terminal D of the LAT 255. For example, if the signal input from the input terminal D is received by the analog switch whose conduction is controlled by the reset signal RES inside the LAT 255, the AND gate 253 may not be provided. If the signal input from the input terminal D is received by the inverter inside the LAT 255, the provision of the AND gate 253 is preferable because the operation state of the inverter can be reliably stabilized. .

{Operation of the circuit shown in FIG. 7 will be described. First, as shown in FIG. 5, it is assumed that the pad electrode 205a is electrically connected to the power supply voltage lead 9a by wire bonding. Therefore, a signal at the power supply potential level (hereinafter, H level) is input to one input terminal of the AND gate 253. When the microcomputer is initialized, the reset signal RES changes from the ground potential level (hereinafter, referred to as L level) to H level. At this time, the potential level of the output signal of AND gate 253 becomes H level. Thereafter, the potential level of the reset signal RES changes from the H level to the L level with the release of the initialization of the microcomputer. The LAT 255 captures the signal received at the input terminal D in response to the fall of the reset signal RES (H through L latch type). Since the buffer 257 is provided, the potential level of the signal captured by the LAT 255 corresponds to the potential level of the pad electrode 205a. As a result, the potential level of the selection signal SEL, which is the output signal of the LAT 255, becomes H level.

(6) Assume that the pad electrode 205a is not electrically connected to the power supply voltage lead 9a by wire bonding as shown in FIG. Therefore, the potential level at one input terminal of the AND gate 253 becomes L level due to the pull-down resistor 251. Thereafter, as described above, as the potential level of the reset signal RES changes from the L level to the H level and changes to the L level again, the LAT 255 captures the signal received at the input terminal D. As a result, the potential level of the selection signal SEL, which is the output signal of the LAT 255, becomes L level.

As described above, the potential level of the selection signal SEL can be switched depending on whether the pad electrode 205a is connected to the lead 9a by wire bonding.

Next, a circuit in the LSI chip 203 to which the selection signal SEL is input will be described. FIG. 8 is a conceptual diagram of the selection circuit 260 to which the selection signal SEL is input, and FIG. 9 is a specific circuit diagram of the selection circuit 260. FIGS. 8 and 9 show examples in which the EEPROM mounted on the LSI chip 213 and the mask ROM mounted on the LSI chip 203 handle 8-bit data.

8, in the selection circuit 260, data D0 to D7 from the EEPROM mounted on the LSI chip 213 are input to one input terminal (0-side input). Further, the data D'0 to D'7 from the mask ROM mounted on the LSI chip 203 is input to one input terminal (1 side input) of the selection circuit 260. FIG. 8 shows one signal line for transmitting data D0 to D7 and data D'0 to D'7, but one in which 8-bit data is transferred in parallel by eight signal lines. It is. The selection signal 260 is input to the selection circuit 260. When the potential level of the selection signal SEL is L level, the output signals ID0 to ID7 of the selection circuit 260 are signals corresponding to the data D0 to D7, respectively. When the potential level of the selection signal SEL is at the H level, the output data ID0 to ID7 of the selection circuit 260 are signals corresponding to the data D'0 to D'7, respectively.

The above operation will be described with reference to a specific circuit diagram of the selection circuit 260 shown in FIG. The selection circuit 260 includes fourteen two-input one-output AND gates 261-0 to 261-7, 263-0 to 263-7, seven two-input one-output OR gates 265-0 to 265-7, It is composed of inverters 267. Data D'n is input to one input terminal of the AND gate 261-n (where n is an integer of 0 to 7). The selection signal SEL is input to the other input terminal of the AND gate 261-n. Data Dn is input to one input terminal of the AND gate 263-n. An output signal of the inverter 267 to which the selection signal SEL is input is input to the other input terminal of the AND gate 263-n. An output signal of the AND gate 261-n and an output signal of the AND gate 263-n are input to two input terminals of the OR gate 265-n, respectively.

As can be understood from the configuration of the selection circuit 260 shown in FIG. 9, when the potential level of the selection signal SEL is at the L level, the AND gate 263-n to which the signal whose potential level is at the H level is input from the inverter 267 is valid. And the data D0 to D7 are output as output data ID0 to ID7 via the AND gate 263-n and the OR gate 265-n, respectively. When the potential level of the selection signal SEL is at the H level, the AND gate 261-n to which a signal having the potential level of the H level is input from the selection signal SEL is enabled, and the data D ′ 0 to D ′ 7 are respectively output to the AND gates. 261-n and output data ID0 to ID7 via the OR gate 265-n. The output data ID0 to ID7 are transmitted to an internal bus in the LSI chip 203 so that they can be transferred to another circuit mounted on the LSI chip 203.

As described above, when the potential level of the selection signal SEL is L level, the mask ROM mounted on the LSI chip 203 is used, and when the potential level of the selection signal SEL is H level, the mask ROM mounted on the LSI chip 213 is used. Can be switched to use the current EEPROM. In FIGS. 8 and 9, only the selection of the data bus portion for transferring data is shown as an example. However, actually, other controls necessary for accessing each memory (mask ROM, EEPROM) are also shown. The signals must be selectable as well. The EEPROM that can be erased in a batch requires a special bus for writing data as a difference from the mask ROM. In response to this, when the LSI chip 213 is selected, a bus used only when writing to the EEPROM of the LSI chip is provided in the LSI chip 203, or the data shown in FIGS. The signal lines transmitting D'0 to D'7 and the signal lines transmitting ID0 to ID7 are bidirectional buses, and the configuration of the selection circuit 260 is analog switches instead of AND gates or OR gates. Can be realized.

As described above, it is possible to switch between the MCP mode using the LSI chip 213 and the Single Chip mode using only the LSI chip 203 according to the presence or absence of bonding to the electrode pad 205a. That is, in the semiconductor device according to the second embodiment of the present invention, an LSI chip 203 mounted with a mask ROM as a program memory, and an LSI chip mounted with a batch erasable EEPROM for a program memory developed for MCP. In the case of an EEPROM version microcomputer, the operation as a microcomputer is realized by combining the LSI chip 203 and the LSI chip 213 as an MCP. In the case of a mask ROM version microcomputer, the MCP using the LSI chip 213 is not used. In addition, the operation as a microcomputer can be realized only by the LSI chip 203.

With such a configuration, in the semiconductor device according to the second embodiment of the present invention, the following effects can be obtained in addition to the effects of the semiconductor device according to the first embodiment.

First, since the LSI chip 213 of the EEPROM for the MCP type can be designed separately from the LSI chip 203, only the new design of the LSI chip 203 which is a mask ROM version microcomputer requires the EEPROM version microcomputer. Can also be realized at the same time. That is, since it is not necessary to separately develop the EEPROM version microcomputer and the mask ROM version microcomputer, the development TAT can be shortened and the development cost can be reduced. Further, since the LSI chip 213 of the EEPROM for the MCP type can be applied not only to a specific microcomputer but also to various microcomputers, a reduction in development cost can be expected.

Secondly, since the LSI chip 203, which is a mask ROM version microcomputer, is also the basis for an EEPROM version microcomputer, the configuration other than the program memory is applied to a common circuit, so that electrical characteristics, noise characteristics, etc. The difference in various characteristics can be made extremely small. As a result, it is possible to easily provide an EEPROM version microcomputer and a mask ROM version microcomputer having no difference in EMC standard.

Third, as compared with the conventional case where the EEPROM version microcomputer is realized by applying a special manufacturing process, the EEPROM portion is applied by the conventional high withstand voltage process, and the other microcomputer circuit portions are replaced by the conventional one. Can be realized by applying the MOS process described above. For this reason, the EEPROM version microcomputer can be realized at lower cost.

Fourth, by replacing the LSI chip 213, a microcomputer that conforms to various specifications can be developed in a short time. For example, a microcomputer having a different memory size, the number of times of guaranteed rewriting of an EEPROM that can be collectively erased, an operating voltage, and the like can be realized only by newly developing the LSI chip 213.

In the second embodiment, the LSI chip 203 as a mask ROM version microcomputer has been described. However, the LSI chip 203 has been developed as a microcomputer having no program memory, that is, a microcomputer having no mask ROM. A mask ROM version microcomputer and an EEPROM version microcomputer can be realized by developing a mask ROM version and a batch erasable EEPROM version as the LSI chip 213 and applying either of them as a program memory. May be. In this case, in any case, since the pad electrode 225 is electrically connected to the pad electrode 215 of the LSI chip 213, circuits such as those shown in FIGS. Further, the LSI chip 213 combined with the LSI chip 203 as the mask ROM version microcomputer is not limited to the batch erasable EEPROM, but may be a mask ROM, an EPROM, or the like. For example, when the memory capacity of the mask ROM mounted on the developed LSI chip 203 is insufficient, a new mask ROM having a large memory capacity is developed in the LSI chip 213 without newly developing the LSI chip 203. By using the mask ROM of the LSI chip 213 as the LSI chip 203, it is possible to easily cope with the problem.

As described above, the first and second embodiments of the present invention have been described in detail. In particular, in the second embodiment, the LSI chip 203 is described as a mask ROM version microcomputer, and the LSI chip 213 is described as a batch erasable EEPROM for a program memory. It is also possible to apply.

(1) A device equipped with an erasable EEPROM and an analog circuit such as an analog-to-digital converter (2) An analog circuit such as an analog-to-digital converter (3) A device equipped with an erasable EEPROM and an SRAM (4) ) Mask ROM (5) DRAM (6) SRAM (7) EEPROM

For example, the Logic process adopted by a microcomputer or the like is becoming a low voltage (for example, a power supply voltage Vdd = 1.6 to 2.0 V in a 0.18 μm process). On the other hand, in a circuit portion for handling an analog signal, such as an analog-digital converter, it is necessary to maintain a conventional interface level (5 V or 3 V) for a sensor, an actuator, or the like. The above (1) and (2) can sufficiently cope with this. Specifically, a mask ROM version microcomputer not including an analog circuit is developed as the LSI chip 203, and the circuit of (2) is applied as the LSI chip 213, and these LSI chips are used in the first or second embodiment. As described in the embodiment, a system LSI is realized by combining the MCP type. In the case of an EEPROM version microcomputer, (1) may be applied to the LSI chip 213. In this case, it is possible to commercialize the mask ROM version microcomputer as a microcomputer without an analog circuit without developing (2).

{Circle around (3)} In the second embodiment, (3) can be used to simultaneously increase the number of memories for storing data. In this case, the SRAM of the LSI chip 213 is used for adding a memory for storing data, and an EEPROM that can be erased at once is used for a program memory.

Further, (4) to (7) are applied when the memory is mounted on the LSI chip 203 to increase the number of data storage memories or when the LSI chip 203 is implemented for mixed mounting of memories having a different manufacturing process. is there. For example, when the memory space of the data storage memory in the LSI chip 203 is exceeded, the address control signal and the chip select signal are controlled so that the access is transferred to the data storage additional memory mounted on the LSI chip 213. do it. This makes it possible to realize a desired system LSI in a short period of time without increasing the product cost.

In the first and second embodiments, two LSI chips are used and connected to each other to realize an MCP type semiconductor device as a system LSI. Needless to say, a semiconductor device that realizes a function as a system LSI may be obtained by connecting three or more LSI chips to each other. For example, four LSI chips, a LSI chip as a mask ROM version microcomputer, an LSI chip as an EEPROM capable of erasing dryness, an LSI chip as a power supply control circuit, and an LSI chip as an analog LSI for communication are interconnected, The functions as a system LSI may be realized by being housed in one package.

In the first and second embodiments, a system LSI typified by a microcomputer has been described as an example. However, the present invention is not limited to this, and the present invention can be applied to the following cases. .

For example, an LSI may be realized by interconnecting a plurality of LSI chips having different manufacturing processes, which are difficult to manufacture on the same semiconductor substrate, which is one of the gist of the present invention. For example, a power LSI to which a bipolar process is applied and an LSI to which a Logic process used for the control is applied may be interconnected and housed in one package.

The present invention can also be applied to a plurality of LSI chips that can be manufactured on the same semiconductor substrate and have the same manufacturing process (for example, all of which are applied with the Logic process). For example, a communication LSI that has already been developed and has many analog circuits that can operate as a single LSI, and a microcomputer for controlling the communication LSI are interconnected and housed in one package. Is also good. In this way, it is possible to develop a different value-added LSI in a short period of time.

As described above, in each case, a plurality of LSI chips housed in one package are connected to each other so as to be able to exchange data and the like, and the plurality of LSI chips have a desired function as a semiconductor device. It is important to be configured to achieve

In the second embodiment, whether or not the LSI chip 213 is used is selected by a circuit mounted in the LSI chip 203 depending on whether or not wire bonding to the pad electrode 205a is performed. However, the present invention is not limited to this. Instead, a similar selection can be realized by the following other methods.

{Circle around (1)} This is a method of selecting using a mask layer for a mask ROM in the LSI chip 203. That is, there are various types of mask layers for determining codes (programs) in the mask ROM, such as a metal layer, a contact layer, and an implantation layer, depending on the memory type. A mask ROM is manufactured using a desired mask corresponding to the program code. For this reason, in addition to the code for the mask ROM, the mask for the mask layer can be used for the above selection, and the selection can be designated. In this case, if the selection process is performed to use the LSI chip 213, the LSI chip 203 cannot be used alone. In this case, a special pad electrode for selection such as the pad electrode 205a is provided. No need. Further, since the code mask of the mask ROM can also be used for selection, it is possible to prevent an increase in cost such as an increase in masks and an increase in manufacturing steps.

(4) This is a method of selecting using a fuse ROM. In other words, the LSI chip 203 is provided with a fuse (hereinafter, referred to as a fuse ROM) made of a metal wiring that allows a predetermined current to flow or can be disconnected by a laser, and is selected according to the disconnected state. It is good to keep it. In the example of FIG. 7, the power supply voltage is applied via the fuse ROM instead of the pad electrode 205a, and the power supply voltage is applied to the AND gate according to the disconnection state of the fuse ROM. It may be possible to selectively control whether or not the ground voltage is applied via the pull-down resistor 251. With such a configuration, selection processing can be performed at the time of wafer probing of the LSI chip 203, so that it is possible to flexibly cope with adjustments to inventory and the like.

Next, a method in which a predetermined pad electrode 205 of the LSI chip 203 is used as a dedicated pad electrode for selection. This is done by removing the pull-down resistor 251 in FIG. 7 and electrically connecting the pad electrode 205a to a selection-dedicated lead, and selecting whether to apply the m power supply voltage or the ground voltage to this lead. It is like that. In this way, the mask ROM version microcomputer and the EEPROM version microcomputer can be easily selected even after the semiconductor device containing the package is incorporated into the electronic device. As a result, in each case of the mask ROM version microcomputer and the EEPROM version microcomputer, device debugging and difference evaluation can be realized with high accuracy and at low cost.

{Circle around (2)} As described above, as a method of providing a lead or a pad electrode dedicated to selection, separate programs may be built in the LSI chip 203 and the LSI chip 213, respectively. In other words, it is possible to selectively realize a microcomputer capable of performing different operations according to different programs depending on the potential level of the signal supplied to the selection-specific lead. That is, one microcomputer can be used as a package in two types of usage. In this case, the switching can be performed without turning off the power in the electronic device to which such a semiconductor device is applied. For example, the continuation of the program stored in the mask ROM of the LSI chip 203 is stored in the EEPROM of the LSI chip 213. It can also be executed continuously by a program. It is also possible to cope with this by developing an LSI chip 203 for one microcomputer (mask ROM version microcomputer) and then developing an LSI chip 213 as an application product of this microcomputer.

(4) This is a method in which selection is performed by a program stored in the mask ROM of the LSI chip 203 or a program stored in the EEPROM of the LSI chip 213. That is, in a microcomputer in which the LSI chip 203 and the LSI chip 213 are housed in one package, the program startup at the time of the initial operation (default) is stored in the program stored in the mask ROM of the LSI chip 203 or stored in the EEPROM of the LSI chip 213. And the first program routine in the selected LSI chip program determines which LSI chip to use (which LSI chip program to use). do it. For example, in the start-up program as this program routine, the potential level of the signal input from the above-described selection lead is confirmed, and the confirmation result is obtained by a mode designation register or the like built in the microcomputer according to the confirmation result. May be held, and this may be used as a selection signal of which LSI chip program to use.

As a method of selecting the start program by another program, a method of confirming the state of the register described above is also possible. For example, as a register that is set or reset depending on whether the LSI chip 213 is connected to the LSI chip 203 so as to be able to exchange data, a register that holds a flag indicating the state is realized. It is possible.

Next, there is a method of selecting the LSI chip 203 by hardware such as a determination circuit for determining whether or not the LSI chip 213 is connected to the LSI chip 203 so as to be able to exchange data. That is, at the time of initialization of the microcomputer or the like, the presence or absence of the LSI chip 213 is determined by such a determination circuit. When it is determined that there is no LSI chip 213, the program on the LSI chip 203 side is started, and when it is determined that the LSI chip 213 is present, the program on the LSI chip 213 side is started. . As such a determination circuit, a configuration similar to the configuration shown in FIG. 7 is applicable, and this may be connected not to the pad electrode 205a but to a signal line that allows a desired determination. In addition, the determination of such a determination circuit can be made by an operation of accessing a predetermined register via a bus line, or a desired detection electrode between two LSI chips can be determined by a wire for determination detection. The connection may be made, and the determination may be made based on the connection state (for example, a power supply voltage is applied when connected, and an open state when not connected).

So far, the modifications and applications of the combination and selection processing of two LSI chips in the first and second embodiments have been described in detail. Next, modified examples and applied examples regarding the layout such as the arrangement of the pad electrodes will be described below.

In the first embodiment and the second embodiment, as shown in FIGS. 2 and 5, the pad electrode 125 and the pad electrode 225 are formed in a region relatively close to the outer periphery of the LSI chip 113 and the LSI chip 213, respectively. (In the figure, it is arranged at a position substantially at the center of the distance between the parallel outer peripheries of the two LSI chips). Further, as shown in the plan view of FIG. 10, a pad electrode 325 is further disposed in a region where the LSI chip 113 is disposed, at a position closer to the outer periphery of the LSI chip 113 than the outer periphery of the LSI chip 103. With such an arrangement of the pad electrodes, the wire 107 for connection between the lead 9 and the pad electrode 105 does not intersect with the wire 117 for connection between the pad electrode 115 and the pad electrode 325. However, the following problems are considered.

(1) First, when the chip size of the LSI chip 113 mounted on the main surface of the LSI chip 103 is changed, it is difficult to respond to the size change, or the margin for the change is reduced. It is fully conceivable that such a size change may occur due to a change in specifications such as an increase in memory size or a change in the applied manufacturing process.

Second, since the pad electrodes 125, 325 and the like are arranged in a region near the center of the LSI chip 103, the layout of the protection circuits such as the pad electrodes 125, 325 and the like is performed at the time of designing the layout of the LSI chip 103. However, there is a restriction that the circuit module in the LSI chip 103 is divided at the area where the pad electrodes 125 and 325 are arranged. With such restrictions, it is not possible to efficiently design an LSI layout by applying a normal CAD system.

In order to solve such a problem, it can be solved by applying a layout of pad electrodes as shown in the plan view of FIG. 11, the same reference numerals are given to the same components as those in FIG.

In FIG. 11, pad electrodes 425 corresponding to the pad electrodes 125 and 325 are arranged in a zigzag manner with the pad electrodes 105 at a position closer to the outer periphery of the LSI chip 103 than the outer periphery of the LSI chip 113. Other configurations are the same as those in FIG. As described above, since the pad electrodes 105 for connection to the leads and the pad electrodes 425 for connection to the pad electrodes 115 are alternately arranged in a staggered manner, the above-described problems can be solved and the space can be saved. And an efficient layout is possible.

(4) In the above-described embodiments and modified examples, pad electrodes are arranged only on two sides of the LSI chip 103 or the LSI chip 113, but the present invention is not limited to this. For example, as shown in the plan view of FIG. 12, a pad electrode 505 corresponding to the pad electrode 105 is arranged along each of four sides of an LSI chip 503 corresponding to the LSI chip 103, and an LSI corresponding to the LSI chip 113. A pad electrode 515 corresponding to the pad electrode 115 may be arranged along each of the four sides of the chip 513. Further, in accordance with the arrangement of the pad electrodes 115, the pad electrodes 525 corresponding to the pad electrodes 125 are arranged so as to be staggered with the pad electrodes 505. The pad electrode 505 is electrically connected to the corresponding lead 9 by a wire 507, and the pad electrode 515 is electrically connected to the corresponding pad electrode 525 by a wire 517.

The layout of the pad electrodes as shown in FIG. 12 depends on the relationship between the size of the LSI chip 503 and the size of the LSI chip 513, the number of the pad electrodes 525, and the design restrictions on the mounting of the pad electrodes 525 for wire bonding. It is arranged along four sides of the chip. However, if possible, as shown in the plan view of FIG. 13, the pad electrode 615 corresponding to the pad electrode 515 is arranged on two opposite sides of the LSI chip 613 corresponding to the LSI chip 513, and In addition, it is better to arrange the pad electrodes 625 corresponding to the pad electrodes 525 of the LSI chip 603 corresponding to the LSI chip 503 on two opposing sides of the LSI chip 603.

こ と By arranging the pad electrodes as shown in FIG. 12, the following effects can be expected. For example, the distance between the pad electrode 615 and the pad electrode 625 used for the internal interface needs to be a certain distance for mounting due to restrictions in wire bonding. However, since there is no limitation as described above on the side where the pad electrode 615 is not arranged, the outer peripheral portion of the LSI chip 613 is brought close to the vicinity of the pad electrode 605 for connection with the lead. You can do this. For example, it can be configured as shown in the plan view of FIG.

In FIG. 14, it will be understood that the size of the LSI chip 613 in the horizontal direction in the drawing is increased. That is, the distance (L1) between the side of the LSI chip 613 on which the pad electrode 615 is disposed and the side of the LSI chip 603 on the side where the pad electrode 625 is disposed is determined on the side where the pad electrode 615 is not disposed. The distance (L2) between the side of the LSI chip 613 and the side of the LSI chip 603 on which the pad electrode 625 is not arranged is shorter.

13 and FIG. 14 have less restrictions on the chip size and shape of the LSI chip 613 than those shown in FIG. 12, so that the degree of freedom in design and shape is increased. . Also, if the size of the LSI chip 613 can be made as close as possible to the size of the LSI chip 603 as much as possible, the thicker portion increases, so that it is possible to make it more robust against external stress. Become.

13 and FIG. 14, an example in which the pad electrode 615 and the pad electrode 625 for the interface are arranged on two sides is described, but the pad electrode 615 and the pad electrode 625 for the interface are arranged on three or one side. They may be arranged.

By narrowing down the sides on which the interface pad electrodes 615 and pad electrodes 625 are arranged, signals for these pad electrodes 625 can be collectively laid out in the LSI chip 603, so that efficient wiring It is possible to simultaneously test a plurality of LSI chips 613 at the time of wafer probing of the LSI chips 613.

Next, a modification of the semiconductor device of the present invention relating to a test will be described below. According to the present invention, in an MCP type semiconductor device, a desired function is realized by using a plurality of LSI chips housed in one package. For this reason, at the time of testing the semiconductor device after assembling, the lead 9 is used to test whether or not a desired function is correctly executed, and a good product or a defective product is selected. Here, in the semiconductor device of the present invention, for example, it is better that a test circuit capable of individually testing each of the LSI chip 103 and the LSI chip 113 is built in the LSI chip 103, for example. For example, it is possible to input a signal of a predetermined potential level to one of the leads 9 for instructing a test and one of the pad electrodes 105 for instructing a test, or to perform a test that enables individual tests. It becomes possible by providing a function. In such a case, the test signal selectively connects the input / output lead of the lead 9 to the input / output signal of the LSI chip 103 or the input / output signal of the LSI chip 113 by a selection circuit as shown in FIG. What is necessary is just to be controlled so that it may be performed. By doing so, for example, it is possible to test the LSI chip 113 composed of an EEPROM that can be erased at once by using a lead 9 with a memory tester and to perform a comprehensive test of the LSI chip 103 with a Logic tester. Therefore, the coverage for the test can be improved.

Next, modifications of the semiconductor device of the present invention relating to wire bonding will be described below. In the first and second embodiments described above, the power supply pad electrode and the ground pad electrode in the pad electrode 115 of the LSI chip 113 are also electrically connected to the pad electrode 125. However, among the pad electrodes 113, the power supply pad electrode, the ground pad electrode, and the analog signal pad electrode are considered to be affected by noise, and sometimes the amount of electric current is reduced like the power supply pad electrode. In many cases, the layout of the portion connected to these pad electrodes in the LSI chip 103 becomes large, or the desired performance cannot be realized.

に 対 し て In order to solve such a problem, the wires 517x and 517y may be used to electrically connect the leads 9x and 9y directly to the leads 9x and 9y like the pad electrodes 515x and 515y in FIG. In FIG. 12, for example, the pad electrode 515x is a pad electrode for power supply, the pad electrode 515y is a pad electrode for grounding, the lead 9x is a lead for power supply, and the lead 9y is a lead for grounding. . FIG. 13 also shows a pad electrode 615x corresponding to the pad electrode 515x and a pad electrode 615y corresponding to the pad electrode 515y.

As shown in FIGS. 12 and 13, the wires are directly connected to the power supply pad electrodes and the ground pad electrodes of the LSI chips 515 and 615 by wire bonding directly from the power supply leads 9x and the grounding leads 9y. Therefore, the above problems can be solved. Therefore, it is possible to prevent noise from flowing into the power supply system, and it is not necessary to supply power or the like through the internal wiring of the LSI chips 503 and 603, so that the metal width of the wiring for the LSI chips 503 and 603 for large currents can be secured. It becomes unnecessary.

As for the pad electrode for the analog signal among the pad electrodes 113 in the LSI chip 113, the lead 9w for the analog signal and the pad electrode 715w for the analog signal are directly connected to the wire 717 as shown in the plan view of FIG. The above problem can be solved by making the connection electrically. Further, the pad electrode for grounding in the LSI chip 113 can correspond to the pad electrode 715w and the lead 9w in FIG.

Next, mounting of the oscillation circuit in the semiconductor device of the present invention will be described below. When the LSI chip 103 and the LSI chip 113 require different source oscillation clocks on the mounted circuit, it is necessary to incorporate an oscillation circuit in each LSI chip and connect a crystal oscillator to each. In this case, in the oscillation circuit on the LSI chip 113 side, the wire length up to the lead becomes longer and the coil component becomes larger, so that the influence of the induction becomes larger.

In such a case, an oscillation circuit for the LSI chip 113 may be provided on the LSI chip 103 side. Even if the LSI chip 113 includes an oscillation circuit, the oscillation circuit mounted on the LSI chip 113 is not used, and a desired oscillation circuit for the LSI chip 113 is used as a substitute for the LSI chip 103. What is necessary is just to input a clock signal.

Next, the structure of the semiconductor device of the present invention will be described below. In any of the embodiments described above, for example, the LSI chip 103 having a large chip size is arranged below, and the LSI chip 113 having a small chip size is arranged above the LSI chip 103. Here, there is an EEPROM such as an EEPROM capable of batch erasing, in which stress is applied to an upper portion of a memory cell to affect various characteristics of a circuit such as an endurance characteristic. For such an LSI chip that is easily affected by the stress, it is preferable to arrange the LSI chip on the upper side of two LSI chips, for example, like the LSI chip 113, in order to reduce the influence on the stress. Good.

Although the present invention has been described in detail above, various improvements and changes are not prevented in the present invention without changing the gist of the present invention.

{For example, in FIG. 12, the pad electrodes 505 and the pad electrodes 525 are arranged in a staggered manner, but this is not a limitation. 12 is applied to a case where the space between the pad electrodes 505 of the LSI chip 503 is narrow or a case where the arrangement of the protection circuit with respect to the pad electrode 525 is restricted due to a layout limitation. . The restriction on the arrangement of the protection circuit with respect to the pad electrode 525 is eliminated, and the space between the pad electrodes 505 in the LSI chip 503 is relatively wide (for example, such that another pad electrode can be arranged between adjacent pad electrodes 505). In such a case, the pad electrode 525 may be arranged between the adjacent pad electrodes 505. That is, the pad electrode 505 and the pad electrode 525 may be arranged in a line on each side of the outer periphery of the LSI chip 503. In this case, the power supply wiring and the grounding wiring laid out in the vicinity of the pad electrode 505 can be shared by the protection circuit in the pad electrode 505 and the protection circuit in the pad electrode 525, which is more effective.

Also, in the second embodiment, the example using the circuit as shown in FIG. 7 has been described, but the present invention is not limited to the circuit configuration as shown in FIG. For example, if the potential level of the selection signal SEL is to be opposite to that described above, the pull-down resistor 251 is a pull-up resistor disposed between the power supply potential and the pad electrode 205a, and the pad electrode 205a is connected to the ground. The selection may be made depending on whether or not the connection is made with the lead and the wire, or the following can be realized.

FIG. 19 shows a modification of the circuit of FIG. 19, the same components as those in FIG. 7 are denoted by the same reference numerals.

In FIG. 19, an N-channel MOS transistor 851 is provided instead of the pull-down resistor 251 of FIG. Other configurations in FIG. 19 are the same as those in FIG. One electrode (for example, the drain side) of the MOS transistor 851 is connected to the pad electrode 205a, and the other electrode (for example, the source side) is grounded. The reset signal RES is input to the gate electrode of the MOS transistor 851 via the buffer 257.

With the configuration as shown in FIG. 19, when the potential level of the reset signal RES becomes H level, the MOS transistor 851 becomes conductive. At this time, if the pad electrode 205a is electrically connected to the power supply lead 9a by a wire, a signal having a potential level of H level is input to the LAT 255 from the AND gate 253. In order to surely perform this, it is desirable that the ON resistance when the MOS transistor 851 is in a conductive state is a high resistance like the pull-down resistance 251. If the pad electrode 205a is not electrically connected to the power supply lead 9a by a wire, a signal having a potential level of L level is input to the LAT 255 from the AND gate 253. Thereafter, the selection signal SEL having a potential level corresponding to the potential level of the signal input to the LAT 255 is output, and the LAT 255 maintains the potential level of the selection signal SEL even if the reset signal RES returns to the L level. be able to. Therefore, the same selection as in the second embodiment can be performed.

The circuit of FIG. 19 is different from the circuit of FIG. 7 even when the pad electrode 205a is electrically connected to the power supply lead 9a by a wire except during the reset processing (that is, when the potential level of the reset signal RES is lower). Except at the time when the level becomes the H level), the current flowing between the pad electrode 205a and the ground can be reduced by the MOS transistor 851. Therefore, the circuit in FIG. 19 can reduce power consumption as compared with the circuit in FIG. If the resistor 251 is considered to be a MOS resistor, there is no difference in layout between FIGS. 19 and 7, and the number of elements does not change.

There is also a method that does not use a circuit as shown in FIG. FIG. 20 is a plan view showing the internal structure of an MCP type semiconductor device according to a modification of the second embodiment of the present invention when the circuit of FIG. 7 is not used. FIG. 20 corresponds to FIG. 5. In FIG. 20, components similar to those in FIG. 5 are given the same reference numerals as in FIG.

20. In FIG. 20, a pad electrode 205b is added to the configuration shown in FIG. The pad electrode 205b is arranged at a position where it can be connected to the grounding lead 9b by a wire.

FIG. 21 is a diagram showing a circuit of the LSI chip 203 connected to the pad electrode 205a and the pad electrode 205b used in the modification of FIG.

As shown in FIG. 21, the LSI chip 203 is provided with a buffer 853 instead of the circuit shown in FIG. A pad electrode 205a and a pad electrode 205b are connected to an input terminal of the buffer 853 via a common wiring. That is, the pad electrode 205a and the pad electrode 205b are wired-ORed by wiring in the LSI chip 103 and input to the buffer 853. The signal output from the buffer 853 is used as the selection signal SEL.

With such a configuration, the pad electrode 205a is electrically connected to the power supply lead 9a by a wire, and the pad electrode 205b is electrically connected to the grounding lead 9b by a wire. If there is, the potential level of the selection signal SEL output from the buffer 853 is maintained at the H level. If the pad electrode 205a is in an open state without being electrically connected to the power supply lead 9a by a wire and the pad electrode 205b is electrically connected to the grounding lead 9b by a wire, the buffer The potential level of the selection signal SEL, which is the output of the signal 853, becomes L level. Therefore, the same selection as in the second embodiment can be performed.

(7) Although this increases the number of pad electrodes 205b, the circuit shown in FIG. 7 is not required, which can contribute to cost reduction and size reduction of the LSI chip 203.

If the pad electrode 205b cannot be provided, the input terminal of the buffer 853 may be connected to only the pad electrode 205a, and the signal output from the buffer 853 may be used as the selection signal SEL. In this case, as shown in FIG. 22, a power supply lead 9a and a grounding lead 9b are arranged adjacent to each other to facilitate wire bonding and prevent a short circuit between the wires. It is desirable that the pad electrode 205a is arranged between the pad electrode 205d and the ground pad electrode 205g. In this manner, the potential level of the selection signal SEL can be selectively controlled by wire bonding the pad electrode 205a to either the power lead 9a or the ground lead 9b.

Here, in order to reduce errors in wire bonding to the pad electrode 205a during manufacturing, it is more preferable to dispose the power supply lead 9a and the grounding lead 9b in FIG. 22 apart from each other. To cope with this case, it is necessary to provide the pad electrode 205a and the pad electrode 205b as shown in FIG.

方法 As a method using the pad electrode 205a and the pad electrode 205b, the following method is further considered.

(4) In this method, the input terminal of the buffer 853 in FIG. 21 can be selectively connected between the input terminal and the ground by using a mask layer for a mask ROM in the LSI chip 203. That is, as described above, there are various types of mask layers for determining the code (program) in the mask ROM, such as a metal layer, a contact layer, and an implantation layer, depending on the memory type, and a mask ROM using a desired mask corresponding to the program code is used. Is produced. For this reason, in addition to the code for the mask ROM, the mask for the mask layer can be used for the above selection, and the selection can be designated. For example, the potential level of the selection signal SEL can be fixed at the L level by connecting the input terminal of the buffer and the ground in the mask layer. In this case, both the pad electrode 205a and the pad electrode 205b can be in an open state without being electrically connected to a desired lead by wire bonding. Therefore, when the use as a mask ROM version microcomputer is determined, the above problem can be solved by fixing the potential level of the selection signal SEL in the mask layer in this way. In this case, since a mask for a program code is used, an increase in the number of manufacturing steps and an increase in manufacturing cost do not occur.

Here, when the use as a mask ROM version microcomputer is determined, the pad electrode 205a, the pad electrode 205b, and the buffer in which the pad electrode 205a and the pad electrode 205b are connected to the input terminal are used, and the buffer is used in the mask layer. It is effective to ground the input terminal of Here, a method of responding to such a microcomputer as to a request to be applied to the EEPROM version microcomputer again will be described below.

に 対 し て For such a request, it is effective to use a circuit as shown in FIG. 23 can be seen in correspondence with FIG. 19, and in FIG. 23, the same components as those in FIG. 19 are denoted by the same reference numerals as in FIG.

回路 The circuit of FIG. 23 does not include the AND gate 253 shown in FIG. This is for the reason described above in FIG. Further, instead of the buffer 853, a LAT 255, a buffer 257, and a MOS transistor 851 similar to those in FIG. 19 are provided. The pad electrode 205a and the pad electrode 205b are wired-ORed by wiring within the LSI chip 103 and connected to the input terminal D of the LAT 255. The reset signal RES is input to the gate terminal of the LAT 255 and is input to the gate electrode of the N-channel MOS transistor 851 via the buffer 257. One electrode (for example, the source side) of the N-channel MOS transistor 851 is grounded, and the other electrode (for example, the drain side) is selectively connected by the mask layer of the mask ROM described above. It can be connected to the input terminal D of the LAT 255 via the switch means 861 in FIG. The signal output from the output terminal O of the LAT 255 is the selection signal SEL. The operation is basically the same as in FIG.

Next, the operation of the circuit of FIG. 23 will be described. Note that in a semiconductor device using the LSI chip 103 and the LSI chip 113 on which the circuit of FIG. 23 is mounted, when the potential level of the selection signal SEL is L level, the semiconductor device is set to be a mask ROM version microcomputer, The description will be made on the assumption that when the potential level of the selection signal SEL is H level, the microcomputer is controlled to be an EEPROM version microcomputer. In FIG. 23, when the switch means 861 is not connected (that is, the MOS transistor and the input terminal D of the LAT 255 are not electrically connected in the mask layer), the pad electrode 205a is connected to the power supply lead 9a and the wire. The potential level of the selection signal SEL can be selectively set based on the reset signal RES depending on whether bonding is performed or the pad electrode 205b is wire-bonded to the ground lead electrode 9b. In this case, either an EEPROM version microcomputer or a mask ROM version microcomputer can be selected by wire bonding. Further, the switch means 861 is connected (that is, the MOS transistor is electrically connected to the input terminal D of the LAT 255 in the mask layer), and both the pad electrodes 205a and 205b are opened without wire bonding. In other words, even if the potential level of the selection signal SEL is set based on the reset signal RES, the potential level of the selection signal SEL can be fixed at the L level. In this case, the microcomputer is fixed as a mask ROM version microcomputer.

Further, when the switch means 861 is connected (that is, the MOS transistor and the input terminal D of the LAT 255 are electrically connected by the mask layer), the pad electrode 205a is electrically connected to the power supply lead 9a and the wire. When the connection is made, the potential level of the signal input to the input terminal of the LAT 255 can be set to the H level. Therefore, even when the switch 861 is in the connected state, the potential level of the selection signal SEL can be set to the H level based on the reset signal RES. In this case, the microcomputer fixed as the mask ROM version microcomputer can be forcibly used again as the EEPROM version microcomputer.

上 記 The above problem can be solved by using the circuit of FIG. Further, in the circuit of FIG. 23, as in FIG. 19, it is possible to contribute to reduction of power consumption.

The circuits shown in FIGS. 7, 19, and 23 each set the potential level of the selection signal SEL based on the reset signal RES. For this reason, the potential level of the reset signal RES whose potential level was at the L level temporarily changes to the H level and may return to the L level again due to an unexpected situation such as an instantaneous interruption of the power supply. In such a case, in order to more stably obtain the potential level of the selection signal SEL, for example, a circuit shown in FIG. 21 is used instead of the circuits shown in FIGS. 7, 19, and 23. It is better to set the potential level of the selection signal SEL irrespective of the reset signal RES described above.

The following method is also possible as a method of using only the pad electrode 205a without providing the pad electrode 205b without using the reset signal RES.

{For example, the input terminal is connected to the pad electrode 205a, and the output signal is used as the selection signal SEL in the same manner as described above. Here, instead of providing the pad electrode 205b, this is a method in which the pad electrode 205a and the ground can be selectively connected using a mask layer for a mask ROM in the LSI chip 203. For example, when the pad electrode 205a is opened without performing wire bonding and the pad layer 205a is connected to the ground with a mask layer, the potential level of the selection signal SEL can be fixed to L level. If the pad electrode 205a is not connected to the ground in the mask layer, and the pad electrode 205a is electrically connected to the power supply lead 9a by a wire, the potential level of the selection signal SEL becomes H level. Can be If the grounding lead 9b is arranged adjacent to the lead 9a, if the pad electrode 205a is electrically connected to the grounding lead 9b by a wire, the potential level of the selection signal SEL becomes L level. can do. Further, even if the pad electrode 205a and the ground are connected by the mask layer, if the pad electrode 205a is electrically connected to the power supply lead 9a by a wire, power consumption increases, but the selection signal The potential level of SEL can be set to H level.

As described above, there are various selection methods in the second embodiment. Therefore, it can be said that the purpose can be satisfied by applying any of the various selection methods described above according to the configuration and purpose of a product to which the semiconductor device of the present invention is applied.

In the above description, the MCP type in which a plurality of LSI chips are connected to each other by using wires has been described as an example. However, the present invention is not limited to this, and application to the following is also possible.

For example, instead of stacking a plurality of LSI chips, they may be mounted on the same plane side of a board and connected to each other by printed wiring on the board. Specifically, the pad electrodes 105 and the pad electrodes 125 of the LSI chip 103 are wire-bonded so as to be electrically connected to predetermined wiring portions provided on a substrate on which the LSI chip 103 itself is mounted. Similarly, the pad electrodes 115 of the LSI chip 113 are also wire-bonded so as to be electrically connected to predetermined wiring portions provided on a substrate on which the LSI chip 113 is mounted. Here, wire bonding is performed so that the pad electrode 115 and the pad electrode 125 are electrically connected via wiring provided on the substrate. Further, the wiring to which the pad electrode 105 is connected by wire bonding on the substrate is an external terminal such as a lead by wire bonding, or a bump electrode provided on a plane on which the LSI chip is not mounted by a through hole or the like. Is electrically connected to

Also, the respective LSI chips may be arranged on the front and back surfaces of the die or the substrate in the lead frame and connected to each other. Specifically, the LSI chip 103 is disposed on the surface of the substrate, and the pad electrode 105 and the pad electrode 125 of the LSI chip 103 are respectively connected to predetermined wiring portions provided on the surface on which the LSI chip 103 itself is mounted. Wire bonding is performed so as to be electrically connected. The LSI chip 113 is disposed on the back surface of the substrate, and the pad electrodes 115 of the LSI chip 113 are electrically connected to predetermined wiring portions provided on the back surface on which the LSI chip 113 is mounted. Wire bonding. Here, the pad electrode 115 and the pad electrode 125 are electrically connected via a wiring provided on the substrate and a through hole. The wiring of the substrate to which the pad electrode 105 is connected by wire bonding is further electrically connected to an external terminal such as a lead by wire bonding.

The pad electrodes may be connected to each other by a pump structure between the respective LSI chips. This is a configuration in which the pad electrode 105 and the pad electrode 125 are directly connected without using wire bonding.

In any case, an LSI chip having a pad electrode as in the present invention can be applied, and a desired function can be realized by interconnecting the plurality of LSI chips.

However, the cost and size increase due to the use of the substrate, the difficulty in interconnecting the LSI chips when the front and back surfaces of the die are used, and the use of a bump structure in the case of a bump structure, In view of the necessity of coping with the change in the arrangement of the pad electrodes to be connected to the upper LSI chip in the lower LSI chip with respect to the change in the arrangement, as shown in FIG. 2 and FIG. Are more optimal.

However, when it is desired to minimize the influence of the stress on each LSI chip in the laminated structure due to various factors such as wire bonding, two LSI chips are mounted on the board as described above, and this board is mounted. It is better to use them to interconnect the two LSI chips. For this reason, the method using a substrate is suitable for a product that emphasizes stress reduction or a product that has other factors that can sufficiently compensate for cost.

In addition, although it is related to the influence of the stress on the above-mentioned LSI chip, in the second embodiment, the large-sized LSI chip 203 is used as a microcomputer, and the small-sized LSI chip 213 is used as an EEPROM capable of collectively erasing data. , But is not limited to this. For example, the large-sized LSI chip 203 may be an EEPROM capable of batch erasing, and the small-sized LSI chip 213 may be a microcomputer.

(4) Depending on the manufacturing process applied to two stacked LSI chips, for example, a case where the size of the LSI chip of the microcomputer is smaller than the size of the LSI chip of the EEPROM that can be collectively erased is also considered. However, when the large-sized LSI chip 203 is an EEPROM that can be erased at once and the small-sized LSI chip 213 is a microcomputer, the following points should be considered.

FIG. 24 is a diagram showing a layout of an internal circuit in the case where a batch erasable EEPROM is used as an LSI chip 913 corresponding to the LSI chip 203.

The LSI chip 913 includes a memory cell area 913-1 in which a memory cell portion is arranged, a first peripheral circuit area 913-2 in which peripheral circuits such as a charge pump circuit are arranged, and a second peripheral circuit in which other peripheral circuits are arranged. Peripheral circuit area 913-3. At this time, the characteristics of the memory cell portion arranged in the memory cell region 913-1 tend to change due to the influence of stress. FIG. 25 is a plan view in which an LSI chip 903 as a microcomputer is stacked on the main surface of the LSI chip 913. FIG. 26 is a plan view showing the relationship between the layout of the internal circuits in the LSI chip 903 and the LSI chip 913 in FIG. Note that FIG. 25 shows a state in which the lead, the sealing resin, and the wire have been removed.

As shown in FIG. 25, pad electrodes 915 for interfacing with the internal circuit of the LSI chip 903 are arranged on the main surface of the LSI chip 913. In FIG. 25, the LSI chip 913 is arranged on two sides on the outer periphery. An LSI chip 903 is arranged on the main surface of the LSI chip 913. On the main surface of the LSI chip 903, pad electrodes 925 that are to be electrically connected to the pad electrodes 915 and that interface with internal circuits of the LSI chip 913 are arranged. The pad electrode 925 is arranged along each side of the adjacent LSI chip 903 in parallel with the side of the LSI chip 913 where the pad electrode 915 is arranged, in consideration of the ease of wire bonding processing. On the main surface of the LSI chip 903, pad electrodes 905 to be electrically connected to external connection leads (not shown) are arranged. The pad electrodes 905 may be arranged in a zigzag manner with the pad electrodes 925 along the same side of the outer periphery of the LSI chip 903 as the sides on which the pad electrodes 925 are arranged, or the pad electrodes 925 are not arranged. It may be arranged along the side. When the pad electrode 905 is arranged along the same side as the side where the pad electrode 925 is arranged, if the interval between the adjacent pad electrodes 905 is wide, the pad electrode 925 is arranged between the pad electrodes 905. The pad electrode 905 and the pad electrode 925 may be arranged in a line. In this case, at the time of wire bonding, it is difficult to distinguish between the pad electrode 905 and the pad electrode 925 to be connected to the lead. However, a wire that electrically connects the pad electrode 905 and the lead by wire bonding is used. It is easy to prevent a short circuit between the pad electrode 915 and the wire that electrically connects the pad electrode 925, and the pad electrode 905 and the lead are electrically connected by wire bonding to prevent such a short circuit. Since it is not necessary to increase the height of the apex of the wire to be connected, the thickness of the sealing resin can be reduced. The pad electrode 925 may be arranged in consideration of wire bonding with a lead to be connected.

As shown in FIG. 26, the LSI chip 903 (in FIG. 26, the area where the memory cell is arranged is indicated by a dotted line) is located above the memory cell area 913-1 of the LSI chip 913 where the memory cell section is arranged. Are arranged so as to completely cover the.

配置 By arranging in this way, the following effects are obtained. That is, for example, the region 913-2 in FIG. 26 is a memory cell region due to the difference in the thermal expansion coefficient between the LSI chips 903 and 913 and the difference in the thermal expansion coefficient between the sealing resins for sealing these LSI chips. Then, it can be seen that the memory cell has a portion covered by the LSI chip 903 and a portion not covered by the LSI chip 903. When the stacked LSI chips are sealed with a resin in such a state, the stress on the memory cells becomes non-uniform due to the above-described difference in the coefficient of thermal expansion or the like (particularly, in the LSI chip 903 in the memory cell region). This is a memory cell at the boundary between the covered part and the uncovered part), and as a result, the characteristics of the memory cell are affected. Therefore, when another LSI chip 903 is stacked on the LSI chip 913 having such a memory cell area, as shown in FIG. 26, the area above the memory cell area 913-1 is completely covered by the LSI chip 903. The above-mentioned problem can be solved by arranging so as to cover.

FIG. 27 is a cross-sectional view of a semiconductor device in which the two stacked LSI chips of FIG. 25 are resin-sealed. FIG. 27 corresponds to a sectional view taken along line A-A ′ of FIG. Note that the same components as those in FIG. 1 are denoted by the same reference numerals. As shown in FIG. 27, the pad electrode 915 for the interface and the pad electrode 925 are electrically connected by a wire 917. The pad electrode 905 is electrically connected to the lead 9 via a wire 907. Note that the height of the apex of the wire 907 needs to be sufficiently high so that the wire 907 and the wire 917 do not short-circuit. In addition, the wire 917 is resin-sealed with a sufficient thickness so that the wire 917 is not exposed to the outside.

FIG. 28 is a diagram showing a modification of the layout of the internal circuit in the LSI chip 913, in which the area where the LSI chip 903 is arranged is indicated by a dotted line, as in FIG. In FIG. 28, the memory cell area 913-1 is substantially the central area of the LSI chip 913. The periphery of the memory cell region 913-1 is defined as a first peripheral circuit region 913-2 and a second peripheral circuit region 913-3. With this arrangement, if the LSI chip 903 is arranged so as to cover a substantially central region on the main surface of the LSI chip 913, the LSI chip 903 can sufficiently cover the memory cell region 913-1.

FIG. 29 is a plan view in which an LSI chip 903 as a microcomputer is stacked on the main surface of the LSI chip 913 in FIG. By arranging the memory cell region 913-1 as shown in FIG. 28, the arrangement of the pad electrodes as shown in FIG. 29 can be realized. That is, the pad electrodes 925 for the interface can be arranged on two parallel sides of the outer periphery of the LSI chip 903, respectively, and the pad electrodes 905 for connection to the leads can be arranged on the other two parallel sides. The pad electrode 915 is provided near the outer periphery of the LSI chip where the pad electrode 925 is arranged.

FIGS. 30 and 31 are cross-sectional views of a semiconductor device in which the two stacked LSI chips of FIG. 31 are resin-sealed. FIG. 30 corresponds to a cross-sectional view taken along line A-A ′ of FIG. 29, and FIG. 31 corresponds to a cross-sectional view taken along line B-B ′ of FIG.

パ ッ ド As shown in FIG. 30, the pad electrode 905 is electrically connected to the lead 9 via a wire 907. As shown in FIG. 31, the pad electrode 915 is electrically connected to the pad electrode 925 by a wire 917.

As described above, as can be seen from FIGS. 28 to 31, the pad electrode 905 and the pad electrode 925 can be arranged along different sides on the outer periphery of the LSI chip 903, respectively. No short-circuit problem occurs. In addition, since it is not necessary to increase the height of the apex of the wire 907 in order to prevent such a short circuit, the thickness of the sealing resin in FIG. 30 can be smaller than in the case of FIG. . Further, since the pad electrode 905 and the pad electrode 925 are arranged along different sides, erroneous wire bonding can be reduced.

Note that, in the above description, the LSI chip 913 is described as an EEPROM that can be erased in a batch. The method shown in FIGS. 24 to 31 is not limited to the erasable EEPROM, and can be applied. Further, the LSI chip 903 is not limited to the microcomputer. In an MCP using LSI chips having different sizes, the arrangement of the LSI chips in the MCP in consideration of such stress is sufficiently effective even when applied to the conventional MCP shown in FIG.

As described above, in the present invention, for example, any one of the two LSI chips may be used as a microcomputer and any of the two LSI chips may be used as a memory. That is, if one is provided with the pad electrode 125 for the interface and the pad electrode 105 for connection with the lead as in the case of the LSI chip 103, if the size of the other LSI chip is large, An LSI chip having the pad electrode 105 and the pad electrode 205 may be disposed on the LSI chip. If the size of the other LSI chip is small, this size is placed on the LSI chip having the pad electrode 105 and the pad electrode 205. It is sufficient to arrange an LSI chip having a small size. As described above, by developing one LSI chip, various LSI chips having various sizes and functions can be applied, whereby various system LSIs can be provided in a short time. In this case, since it is not necessary to re-develop one LSI chip, the cost can be reduced.

Note that various modifications and application examples described in this specification can be applied to the configuration described with reference to FIGS. 24 to 31.

The pull-down resistor and the N-channel MOS transistor in the circuits shown in the above-described embodiments, modifications, and application examples may be a pull-up resistor or a P-channel MOS transistor depending on how the potential level of the selection signal SEL is used. Is also good. Further, other signals may be used instead of the reset signal RES. However, the reset signal RES is preferably automatically set at the initial stage of the operation of the LSI chip.

FIG. 1 is a cross-sectional view illustrating an internal structure of an MCP type semiconductor device 100 according to a first embodiment of the present invention. FIG. 2 is a plan view showing an internal structure of the MCP type semiconductor device 100 according to the first embodiment of the present invention. FIG. 2 is a perspective view illustrating the assembly of the semiconductor device 100 in FIG. 1. FIG. 2 is a block diagram showing a configuration of a microcomputer 50 equipped with an EEPROM that can be erased at once. FIG. 9 is a plan view illustrating an internal structure of an MCP type semiconductor device according to a second embodiment of the present invention, and is a diagram of a semiconductor device as an EEPROM version microcomputer. FIG. 9 is a plan view illustrating an internal structure of an MCP type semiconductor device according to a second embodiment of the present invention, and is a diagram of a semiconductor device as a mask ROM version microcomputer. FIG. 3 is a diagram showing a circuit of an LSI chip 203 connected to a pad electrode 205a. FIG. 3 is a conceptual diagram of a selection circuit 260 to which a selection signal SEL is input. FIG. 3 is a specific circuit diagram of a selection circuit 260. FIG. 3 is a plan view of a semiconductor device showing a modification of FIG. 2. FIG. 3 is a plan view of a semiconductor device showing a modification of FIG. 2. FIG. 12 is a plan view of a semiconductor device showing an application example of FIG. 11. FIG. 13 is a plan view of a semiconductor device showing a modification of FIG. 12. FIG. 14 is a plan view of a semiconductor device showing an application example of FIG. 13. It is a top view of the semiconductor device which shows the modification in wire bonding. FIG. 11 is a cross-sectional view illustrating a conventional semiconductor device. FIG. 14 is a cross-sectional view illustrating another conventional semiconductor device. FIG. 18 is a plan view of the semiconductor device of FIG. 17. FIG. 14 is a diagram illustrating a modification of the circuit of the LSI chip 203 connected to the pad electrode 205a. FIG. 15 is a plan view illustrating an internal structure of an MCP type semiconductor device according to a modification of the second embodiment of the present invention. FIG. 9 is a diagram showing a circuit of the LSI chip 203 connected to the pad electrodes 205a and 205b. FIG. 9 is a diagram showing an arrangement of pad electrodes and an arrangement of leads in a modified example of the present invention. FIG. 9 is a diagram illustrating another example of the circuit of the LSI chip 203 connected to the pad electrode 205a and the pad electrode 205b. FIG. 9 is a diagram illustrating a layout of an internal circuit when a collectively erasable EEPROM is used as an LSI chip 913 corresponding to the LSI chip 203; FIG. 13 is a plan view in which an LSI chip 903 is stacked on a main surface of an LSI chip 913. FIG. 26 is a plan view showing a relationship between an LSI chip 903 and an internal circuit arrangement in the LSI chip 913 in FIG. 25. FIG. 26 is a cross-sectional view of a semiconductor device in which two stacked LSI chips of FIG. 25 are resin-sealed. FIG. 14 is a diagram illustrating a modification of the layout of the internal circuit in the LSI chip 913. FIG. 29 is a plan view in which an LSI chip 903 is stacked on a main surface of an LSI chip 913 in the modification of FIG. FIG. 30 is a cross-sectional view (A-A ′ cross-sectional view) of the semiconductor device in which the two stacked LSI chips of FIG. 29 are resin-sealed. FIG. 30 is a cross-sectional view (B-B ′ cross-sectional view) of the semiconductor device in which the two stacked LSI chips of FIG. 29 are resin-sealed.

Explanation of reference numerals

9 Lead 103, 203, 503, 603, 703 LSI chip (bottom)
113, 213, 513, 613, 713 LSI chip (upper)
105, 205, 505, 605, 705 Pad electrode (for lead connection)
115, 215, 515, 615, 715 Pad electrode (for internal interface)
125, 225, 325, 425, 525, 625, 725 Pad electrode (for internal interface)
107, 207, 507 wire 117, 217, 517, 717 wire

Claims (5)

In a semiconductor device in which a first semiconductor element and a second semiconductor element mounted on the first semiconductor element are sealed with a resin,
The second semiconductor element is smaller in size than the first semiconductor element, and the second semiconductor element is formed on the first semiconductor element by a stress included in the first semiconductor element. Is placed in a position that does not make the stress of the configuration that should be uniform,
A plurality of circuits arranged on a main surface of the first semiconductor element, each of which is electrically connected to any of a plurality of circuits provided as components of the first semiconductor element; A plurality of first pad electrodes electrically connected to corresponding ones of the terminals;
A plurality of second pad electrodes disposed on a main surface of the first semiconductor element, each of which is electrically connected to any one of a plurality of circuits provided in the first semiconductor element;
The second semiconductor device is disposed on a main surface of the second semiconductor device, each of which is electrically connected to a circuit provided in the second semiconductor device, and electrically connected to a corresponding one of the second pad electrodes. A third pad electrode,
The semiconductor device, wherein the first semiconductor element performs a predetermined function by using a circuit provided in the second semiconductor element. 2. The semiconductor device according to claim 1, wherein the second semiconductor element is disposed at a position that completely covers a structure on which the stress is to be made uniform. (3) The semiconductor device according to (1) or (2), wherein the structure for making the stress uniform is a memory cell portion. 4. The semiconductor device according to claim 3, wherein the memory cell unit is disposed in a central region of the first semiconductor element. (5) The semiconductor device according to any one of claims 1 to 4, wherein the first semiconductor element is a memory that can be erased at once, and the second semiconductor element is a microcomputer.

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