JP4471990B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor disk drive having small mounting area suitable for assembling it to a portable small information terminal, etc., and capable of quickly coping with a model change due to the change of specification of a controller, etc., while a development TAT (Turn Around Time: a period required till the shipment of product from a supply of base material, and days required till the completion of a development from a start of the development) is shortened and also a development cost is suppressed to be low. <P>SOLUTION: This device is specified so that one signal output terminal of a first semiconductor chip in a single package and a first outside terminal of the semiconductor device are independently interconnected and one signal input terminal of a second semiconductor chip and a second outside terminal of the semiconductor device are independently interconnected, then the connection between the signal output terminal and the signal input terminal is completed by such a manner that the first and second outside terminals of the semiconductor device are connected in the outside of the semiconductor device. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to an MCP type semiconductor disk device capable of memory expansion and a semiconductor device in which measures for facilitating testing of a plurality of chips housed in an MCP (Multi-Chip Package) are taken.

  Along with the ever-increasing demand for high-density mounting of semiconductor devices on printed circuit boards, semiconductor device packages are becoming smaller. In recent years, various types of CSP (chip size package), which is a collective term for packages that are equal to or slightly larger than the chip size, have been developed. (The package type of CSP is classified as a derivative of the existing package.) They greatly contribute to reducing the size and weight of portable terminals and the like.

  At the same time, the speed of increasing the memory capacity required by the system equipment is faster than the speed of increasing the memory density. Therefore, as a means of increasing the memory capacity by suppressing the increase in memory mounting area, the memory tertiary An original implementation has been proposed. The present applicant has developed a DDP (Double Density Package) technology in which a LOC (Lead On Chip) structure is stacked that doubles the memory capacity with the same outer dimensions as the 1 mm thick surface mount package TSOP (Japanese Patent Laid-Open No. Hei 11). No. 163255 = Patent Document 1). Among them, a 128MDRAM / DDP is disclosed which has a structure in which leads are joined after a LOC structure (64MDRAM) lead frame is stacked and encapsulated in a mold.

  A semiconductor disk device using a flash memory in place of a conventional magnetic disk device does not have a mechanically movable part like the magnetic disk device, and thus is unlikely to malfunction or fail due to a physical shock. In addition, the size of the apparatus can be reduced, and data read / write access can be performed faster than the conventional magnetic disk apparatus. Conventionally, the semiconductor disk device has been realized as a memory board or a memory card including a plurality of flash memories and a controller for controlling the flash memories. In this case, the plurality of flash memories are realized as separate LSIs, and the controller is also realized as one LSI.

  In order to deal with the problem that the number of parts of the semiconductor disk device is large as described above and it is difficult to make it compact, Japanese Patent Laid-Open No. 6-250799 (Patent Document 2) discloses an interface between a flash memory unit and an external device. And a semiconductor disk device in which a controller unit is configured as one LSI. The semiconductor disk device of this single semiconductor chip configuration is provided with an extended memory interface, and in the case of further expansion of the flash memory built in the chip, the flash memory in units of chips is externally provided by the user as needed. To increase the storage capacity of the semiconductor disk device.

On the other hand, Japanese Patent Application Laid-Open No. 11-86546 (Patent Document 3) discloses a technique for separately manufacturing a logic chip and a memory chip and mounting them in one package in parallel. is doing.
Japanese Patent Laid-Open No. 11-163255 JP-A-6-250799 JP 11-86546 A

  The inventor of the present application has studied a semiconductor disk device suitable for incorporation into various portable information terminals (palm size PCs, handy terminals), digital cameras and the like as main application target products. The required specifications are required to be smaller in terms of mounting area, weight, and power consumption. In addition, there are various types of controllers for various applications, and it is expected that the frequency of updating the specifications will be high as a security measure. Therefore, the development period of new package products will be shortened, reducing the cost common to consumer devices. Is emphasized.

  There are the following problems in forming a so-called system LSI in which the constituent units of the semiconductor disk device disclosed in the above-mentioned JP-A-6-250799 are configured on a single semiconductor chip. (1) It becomes necessary to develop a new process and the number of process steps increases, leading to an increase in cost. (2) When all the constituent units are manufactured by the same process, there is a problem that the performance of each individual unit is reduced as compared with the case where each unit is manufactured by a dedicated process. (3) Redesigning the entire chip as the controller unit specifications change is disadvantageous in reducing development costs and development TAT. (4) Since each component unit is arranged in a plane, the single chip size is increased.

  Further, as described in Japanese Patent Application Laid-Open No. 11-86546, an LSI in which a plurality of chips are arranged in parallel and combined into one package is similarly within a range in which the mounting area does not become smaller than the total area of each chip. The mounting area will be reduced.

  (1) The first object of the present invention is to develop TAT (Turn), which has a small mounting area suitable for incorporation into a portable information terminal and the like, and can respond quickly to model changes due to changes in controller specifications. Around Time: Proposes a semiconductor disk device package configuration that shortens the development cost from the start of development to the product shipment.

  Further, the inventor of the present application examined the problem of testing a product in which a memory chip and a controller chip are mounted in one package in a scheme in which the semiconductor disk device is configured by MCP. Existing memories and controllers (logic) were individually packaged, individually tested, and mounted and connected on a printed circuit board. When a combination of two chips of this usage form is commercialized as one package, it is considered that the “wiring” on the printed circuit board of the memory and the controller is usually incorporated in the package. However, problems arise in the test before product shipment. When the existing memory and controller were tested as a single package, the memory was tested with a memory tester and the controller was tested with a logic tester. These ready-made test environments cannot be used under the same conditions as before when the memory and the controller are incorporated into one package as described above and are connected internally. For example, when a memory test is performed by a memory tester due to internal connection, there is no influence (leakage current etc.) due to the connection of the controller. Cannot be implemented. The same is true for controller testing. That is, even if the influence of the internal connection is reduced as much as possible, or the analysis considering the influence is taken in, the test quality is expected to deteriorate.

  Furthermore, comparing the characteristics of the memory tester and the logic tester, the memory tester adopts a method that increases test productivity based on the simultaneous testing of a large number of memories as the test time increases as the memory capacity increases. is doing. On the other hand, the logic tester uses many signal terminals to apply a long test pattern to the LSI under test, but the test time is generally about two orders of magnitude shorter than the memory test time. Because of this characteristic, the logic tester employs a method of increasing test productivity by speeding up the mounting rotation of the LSI under test. If it is assumed that a mixed tester having both tester functions with different characteristics is developed, a test of both functions (MCP) package mounted on the mixed tester can be performed. After the test is completed, the terminal for logic test is played for a long time until the memory test is completed, and it is predicted that the test productivity is eventually lost.

  Therefore, from the viewpoint of test productivity in which an expensive test system is efficiently used, a method of separately testing the memory chip and the logic chip in the MCP twice is considered to be promising. Therefore, the memory tester and the package under test are modified to add the function of separating the influence of connecting the controller, and the logic tester and the package under test are modified to add the function of separating the influence of connecting the memory. Expected to be a thing.

Therefore,
(2) The second object of the present invention is to make it possible to efficiently use an expensive test system that has been conventionally built for individual chips, and to reduce the cost and man-hours for developing a new test environment. It is to propose a shortened MCP implementation.

  (3) Further, the solution (2) considering the efficiency of the test environment development investigates whether it can be widely applied to all MCPs even if the types of multiple chips to be combined, built-in functions, and package forms change. .

  (4) Further, considering the problem of developing a test environment for a plurality of LSI cores in a system LSI, it is investigated whether the present invention can be similarly applied.

When considering mounting forms suitable for embedded semiconductor disk devices such as various portable information terminals and digital cameras, the chip area is 40 mm, especially when evaluated in terms of (1) small mounting area and (2) low manufacturing cost. ^In the case of ² or more, it is estimated that it is better to mount the memory chip and the controller chip on the stack package (three-dimensional mounting) than to make the system LSI into one chip. (Refer to NIKKEI MICRODEVICES August 1999 issue pp. 40-45.) Consider a form in which multiple different types of chips (combination of memory chip and controller chip, etc.) are three-dimensionally mounted into one package. Usually, since the outer shape and electrode pad arrangement of a plurality of chips are different, the form is different from a package in which a plurality of chips having the same shape and specifications are stacked, such as DDP and stack memory. Considering the fact that the manufacturing cost can be reduced by using the existing equipment with the widely used package type and the effect of reducing the mounting area is high, there are the following two types.

  (1) A TQFP (Thin Quad Flat Package) type having a four-way lead arrangement structure in which a second semiconductor chip is stacked on a semiconductor chip having a LOC (Lead On Chip) structure.

  (2) Stacked chip CSP (Chip Size Package) type based on the small BGA (Ball Grid Array) type.

  The CSP type is superior in the effect of reducing the mounting area, but the TQFP type using a lead frame with a low cost is superior from the viewpoint of a short development period such as product design and low manufacturing cost.

  As a package form of a semiconductor disk device suitable for incorporation into various portable information terminals, digital cameras, etc., the development period of product design that combines and packages existing chips is short, and multiple chips in a single lead frame The TQFP type having the lowest manufacturing cost due to the structure in which the layers are stacked is disclosed as the first solution in the first embodiment. For expansion of the memory of this semiconductor disk device, a memory expansion terminal is provided on the package. It has specifications that allow the controller to access externally connected expansion memory in the same way as the built-in memory.

  Further, the following is proposed as a second object of the present invention, a measure for facilitating the test of a plurality of chips incorporated in the MCP.

  In the first embodiment, there is basically no internal connection between the controller and the flash memory in the package constituting the semiconductor disk device. Each electrode pad of the controller chip and the flash memory chip is independently connected to an external terminal of the package. Note that the power supply or ground may be connected to a common external terminal for both chips. When the semiconductor disk device is used, it is mounted on a board and the external terminals are connected by wiring on the board. The controller accesses the flash memory via an external terminal and wiring on the board.

  With such a configuration, the flash memory and the controller in the package of the present invention operate independently when viewed from the outside of the package through the external terminals. Therefore, the package of the present invention can be mounted on a conventional test environment developed for individual chips, and the memory test and the logic test can be sequentially executed in the same manner as in the case of individual chips. According to the system of the present invention, it is possible to execute a reliable test equivalent to the conventional one without adding a function for shielding the influence of other chips to the environment of the memory test and the logic test.

  The configuration of the MCP of the present invention that enables independent testing is not limited to the MCP of the combination of the flash memory and the controller (ASIC) of the first embodiment, but is the same in any MCP of any package form and any combination of multiple chips. It can be applied with the effect of

  Further, as a modification of the present invention, a selector is provided on the internal wiring between a plurality of chips in the MCP, and a test mode signal is input to the selector from an external terminal, so that the connection between the plurality of chips is disconnected. A mode is also conceivable in which a selector can select a mode in which a chip is independently tested from an external terminal, and a mode in which a plurality of chips are internally connected to allow access between chips within the package.

  In this case, a selector having a switch function for switching the connection by a mode signal is installed on the internal wiring in the package or in the controller chip.

  A system program according to a combination of a flash memory and a controller is built in the flash memory, and a package that guarantees that the system program operates is provided.

  According to the present invention, by storing a plurality of types of semiconductor chips in a single package, the mounting area can be reduced, and internal connections between a plurality of chips in the package can be eliminated to the extent possible. By independently connecting each terminal (electrode pad) to the external terminal of the package, when testing each chip in the package, it eliminates the influence of signals, leakage current, etc. from chips other than the chip under test It is possible to provide an environment where each chip can be tested independently. This can be applied to an existing test system developed for each individual chip as it is, or with a slight correction, and if each chip is tested independently, the reliability of the test is also guaranteed. As a result, it is not necessary to spend man-hours and costs for the development of a new test system, so that the product development TAT and cost can be reduced.

  As a modification of the present invention, a test selector is provided in the package, the internal connection is switched by a mode signal, and each chip is tested independently. It is possible and has the same effect. However, it is necessary to design the selector on the internal wiring in the package or in the controller chip.

  Hereinafter, embodiments (examples) of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.

(Embodiment 1)
FIG. 1 shows a block diagram of a semiconductor disk device 100 composed of a single semiconductor package 10 of the present invention. The memory chip 20 and the controller chip 30 constituting the semiconductor disk device 100 are not internally connected in the semiconductor package 10, but are connected to the external terminal groups 11 to 16 included in the semiconductor package 10 (each external terminal group includes a plurality of external terminals). The signal terminals of the memory chip 20 and the controller chip 30 (hereinafter, a plurality of electrode pads are collectively referred to as “electrode pads 21, 22, 31 to 34”). Are internally interconnected independently. That is, the controller chip 30 includes an electrode pad 31 for inputting / outputting an address / various access signals and an electrode pad 32 for inputting / outputting a data / command signal from the external host device as external terminals for connecting the semiconductor package 10 to the host device. 11 (host interface) and internal connections 317, 318, output address / data / command signals to the memory, and electrode pads 33 for inputting data signals from the memory are external terminals 12 (memory interface) of the semiconductor package 10. In addition, an electrode pad 34 for inputting / outputting an access control signal to / from the memory is internally connected to the external terminals 13 and 16 for the access control signal of the semiconductor package 10. Further, the memory chip 20 inputs address / data / command signals from the controller 30 and internally connects the electrode pads 21 for outputting the data signals to the controller 30 with the external terminals 14 of the semiconductor package 10, Electrode pads 22 for inputting / outputting access control signals to / from the controller are internally connected to the external terminals 15 for access control signals of the semiconductor package 10. Other than the above, the controller chip 30 and the memory chip 20 are connected to the outside of the semiconductor package 10, and signals that need to be input / output, power supply (Vcc), ground (Vss), etc. Other electrode pads of the memory chip 20 and other external terminals of the semiconductor package 10 are internally connected. At that time, electrode pads such as ground (Vss) and power supply (Vcc) may be connected to a common external terminal, or some signals may be connected to a common external terminal or internally.

  The semiconductor package 10 of the present invention is mounted on a motherboard 150, and external terminals 12 (memory interface) and external terminals 14 of the semiconductor package 10 are externally connected by a memory bus 301 on the board. By externally connecting the external terminal 13 and the external terminal 15 of the semiconductor package 10 through the control bus 302, the controller 30 and the memory 20 are connected to enable access control as a semiconductor disk device. .

  In this way, by making the mounting form that avoids connecting the controller chip 30 and the memory chip 20 in the semiconductor package 10 inside as much as possible, when testing each chip individually by the test system from the external terminal, Reliable tests can be performed while suppressing the influence from other chips.

  Further, in the semiconductor disk device 100 of the present invention, in order to be able to expand the storage capacity of the memory, a memory expansion terminal 16 for connecting the expansion memory 50 to the outside is provided so that the controller 30 can access it. For memory expansion, the expansion memory 50 mounted in the same manner on the motherboard 150 is supplied to the memory bus 301 connecting the controller 30 and the built-in memory 20 and the control bus 302 in the same hierarchy (address, various control signals, etc. are supplied in common). Connected). A part of the access control signal 303 is input / output to / from the expansion memory 50 in common with the input / output between the controller 30 and the built-in memory 20. The expansion memory dedicated access control signal 304 is directly input / output from the controller 30 to the expansion memory 50 via the memory expansion terminal 16. Which of the built-in memory 20 and the extended memory 50 is accessed is determined by which of chip enable signals F_CEA_1 to F_CEA_5 described later is generated. The extended memory 50 is mounted with a memory chip having the same specifications as the built-in memory 20 or a memory chip having a different storage capacity as a single or a plurality of package configurations.

  FIG. 2 shows an example in which the semiconductor disk device 100 of the present invention is configured in a single package 10. FIG. 2 is a plan view of the TQFP (Thin Quad Flat Package) type semiconductor package 10 having a four-way lead arrangement structure with the top of the resin sealing body removed, and FIG. 3 is taken along line AA in FIG. 4 is a schematic cross-sectional view taken along line BB in FIG. 2, and FIG. 5 is a schematic cross-sectional view taken along line CC in FIG.

  As shown in FIG. 2, FIG. 3, FIG. 4 and FIG. 5, the semiconductor disk device 100 according to the first embodiment has a controller chip 30 in which a plurality of electrode pads 4 are formed on a main surface 30X of a rectangular semiconductor substrate. A memory chip 20 in which a plurality of electrode pads 4 are formed on a main surface 20X of a rectangular semiconductor substrate having a size larger than that of the semiconductor substrate of the controller chip 30, and the outer sides of the controller chip 30 and the memory chip 20 The electrode part 4 of the controller chip 30 and the memory chip 20 and the inner part 7A are electrically connected via a conductive wire 8 and composed of an inner part 7A and an outer part 7B. A resin seal in which a plurality of leads 7, a support lead 6 that supports the memory chip 20, the controller chip 30, the memory chip 20, the wire 8, and the inner portion 7A of the lead 7 are sealed with resin. And a body 9.

  The support lead 6 is a semiconductor chip support lead disposed in a central space portion surrounded by a suspension lead portion 6A disposed between the lead group consisting of the plurality of leads 7 and an inner portion 7A of the lead 7. The part (bus bar) 6B is composed of a lead integrally formed. The lead frame including the plurality of leads 7 and the support lead 6 is etched or pressed into a flat plate material made of, for example, an iron (Fe) -nickel (Ni) alloy or copper (Cu) or a copper alloy. Is applied to form a predetermined lead pattern.

  The surface (back surface) opposite to the main surface 30X of the controller chip 30 is placed on the main surface (front surface) 20X of the memory chip 20, and the back surface of the controller chip 30 and the memory chip 20 are left as they are. The main surface 20X is bonded and fixed with an adhesive 5 to constitute a semiconductor chip laminate. The semiconductor chip support lead 6B is bonded and fixed to the main surface 20X of the memory chip 20 of the semiconductor chip stack to support the semiconductor chip stack. The upper surface of the support lead 6B is lower than the top of the wire 8.

  The planar shape of the resin sealing body 9 is formed in a rectangular shape, and in the first embodiment, for example, it is formed in a rectangular shape. A plurality of lead outer portions 7B are arranged along the four sides of the resin sealing body 9. The outer portion 7B of the lead is formed in a gull wing shape, for example, as a surface mount type shape.

  Since the semiconductor package 10 does not have a tab between the main surface 30X of the controller chip 30 and the main surface (front surface) 20X of the memory chip 20, the thickness can be reduced. Further, by bonding and fixing the semiconductor chip support lead 6B to the main surface 20X of the memory chip 20, the thickness of the support lead 6 is offset by the loop height of the wire 8, and resin sealing by the support lead 6 is performed. There is no effect on the thickness of the body 9. As a result, it is possible to reduce the thickness of the semiconductor package 10 in which a plurality of chips are stacked, and to form a TSOP type.

  In the embodiment, the area of the memory chip 20 is larger than the area of the controller chip 30. In such a case, since the bending strength of the large-area chip is weaker than that of the two chips having the same thickness, the chip thickness can be increased for the large-area chip. Conceivable.

  In order to configure the above-described stack type MCP in the TSOP type, when connecting each electrode pad 4 of each chip and the inner portion 7A of the lead 7 arranged on the four sides with the wire 8, the proximity of the wire, In order to avoid crossing, the total number of electrode pads of a plurality of chips needs to be distributed in each direction according to the ratio of the number of leads on each side. In the example shown in FIG. 2, the arrangement of the electrode pads on one side of the controller chip 30 is rougher than the arrangement of the electrode pads on the other three sides, and the arrangement of the electrode pads on the memory chip 20 is one side corresponding. Gather to the side and combine both chips. As a result, the ratio of the number of electrode pads on the four sides is substantially the same as the ratio of the number of leads, and the intersection of the connection wires is eliminated.

  FIG. 6 shows an example of signal arrangement of the external terminals (outer portions 7B of the leads) of the semiconductor package 10 shown in FIG. For example, the VCC terminal is a controller power supply potential terminal, for example, 3.3 volts (V) or 5 volts (V). The VCCf terminal is a memory power supply potential terminal, for example, 3.3 volts (V). The VSS terminal is a reference potential terminal that is fixed at a reference potential (for example, 0 volt). The I / O0 to I / O7 terminals are connected to the electrode pads 21 of the memory chip 20 and are address / data / command input / output terminals for the memory. The F_DA (0) terminal to F_DA (7) terminal are connected to the electrode pad 33 of the controller chip 30 and are address / data / command input / output terminals for the memory. The F_CEA_1 to F_CEA_5 terminals output the chip enable signal 1 from the F_CEA_1 terminal when the controller selects the memory 20 in the package, and select the F_CEA_2 to F_CEA_5 terminals to select the external expansion memory 50 Chip enable signals 2 to 5 are output to the corresponding extended memory. The F_OEA pin is set by the controller when reading data from the memory. The F_RDY_1 and F_RDY_2 pins are set by the controller for memory write / erase operations. The F_WEA terminal sets the memory write enable signal from the controller. The F_SC_A1 and F_SC_A2 pins set the serial clock from the controller. The F_CDEA terminal is set by the controller to control the multiplex bus when writing to the memory. The F_RES pin sets the RESET signal from the controller. Table 1 shows a list of functions assigned to each external terminal.

  FIG. 7 shows the first embodiment in which signals are assigned to the external terminals of the semiconductor package 10 as shown in FIG. 6. When the semiconductor package 10 is mounted on a board and used, the user short-circuits the wiring on the board. A combination example of external terminals that need to be connected between two points having different potentials by a conductor having a very low resistance in a circuit and a wiring example on a board are shown. That is, for example, an F_DA (0) terminal having a pin number 44 internally connected to the controller and an I / O0 terminal having a pin number 9 internally connected to the memory are externally connected. Further, the F_RDY_1 terminal of pin number 47 internally connected to the controller and the RDY / Busy terminal of pin number 5 internally connected to the memory are externally connected. The other terminals are also externally connected as in the combination of FIG. 7 so that the semiconductor device 100 of the present invention functions as a semiconductor disk device. If the external connection wiring on the board is wired without crossing as shown in FIG. 7, it can be short-circuited by a single wiring layer on the board. The degree to which the increase of the wiring layer on the board is suppressed and the other wiring is disturbed is small. In this way, it is considered necessary to assign signals to the external terminals that are ordered so as not to cross each other as much as possible on the board.

  FIG. 8 shows an example of a block diagram of the controller 30, and FIG. 9 shows an example of a block diagram of the flash memory 20.

  The functions of the controller shown in FIG. 8 are based on the specifications specified by PCMCIA (Personal Computer Memory Card International Association) for the interface with the host device, and the memory card mode, I / O card mode, and IDE (Integrated Device Electronics). ) Supports any operation mode of compliant mode. It is possible to access the memory from the host device by an access method similar to that of a memory card or I / O card (PCCard), or by an interface similar to that of a conventional IDE-compliant hard disk device. As shown in the figure, this controller comprises a host interface control unit 35, a data transfer control unit 36, and a memory interface control unit 37 with a 16-bit CPU as a core processor 38.

  The host interface control unit 35 has a register for recording various attribute information CIS (Card Information Structure) of hardware resources referred to from the host device side when accessed by the PCCard specification, and various card standard specifications as CCR. Prepare for (Card Configuration Register). When accessing the semiconductor disk device 100 from the host device, it is one of the interfaces of the ATA standard (AT Attachment: hard disk), for example, via an external terminal (host interface) 11 for connecting the host device from the host device. A command compliant with ANSI (standardized by ANSI (American National Standards Institute)) is sent to establish a connection with reference to the CIS, and then read and write data. The host interface control unit 35 takes in and interprets the command, and temporarily stores the address indicating the access head position, the data length, and the received write data in the task register. When data is read, the data read from the memory is temporarily stored in the task register, and then sent to the host device by a command conforming to the ATA standard.

  The memory interface control unit 37 constitutes an interface according to the specific characteristics of the memory built in or expanded in the semiconductor disk device 100. Memory access control is performed using memory commands determined in a memory specific manner. If the memory specification changes, only the specification of the memory interface control unit 37 is changed. The memory interface control unit 37 determines whether the address accessed from the host device corresponds to the built-in (flash) memory or external expansion (flash) memory, and stores it in the corresponding (flash) memory. A corresponding chip enable signal is generated. At the same time, the ATA-compliant command from the host device is converted into a memory command for controlling the corresponding (flash) memory, and sent to the corresponding (flash) memory via the external terminal 12 (memory interface). The (flash) memory that has received the chip enable signal enters an active state, and an operation mode is set by a memory command from the memory interface control unit 37 and access control is performed.

<Overall configuration of flash memory>
FIG. 9 shows an overall configuration of, for example, the flash memory 20 that is access-controlled by the memory interface control unit 37.

  A memory matrix (memory array) 201 has a large number of nonvolatile memory cell transistors that can be electrically erased and written in an array. For example, as illustrated in FIG. 20, the memory cell transistor includes a source S and a drain D formed in a semiconductor substrate or a memory well SUB, a floating gate FG formed in a channel region via a tunnel oxide film, and a floating The control gate CG is configured to overlap the gate via an interlayer insulating film. The control gate CG is connected to the word line 221, the drain D is connected to the bit line 220, and the source S is connected to a source line not shown.

  The external input / output terminals I / O0 to I / O7 are also used as address input terminals, data input terminals, data output terminals, and command input terminals. An X address signal (sector address signal) input from the external input / output terminals I / O 0 to I / O 7 is supplied to the X address buffer 203 via the multiplexer 202. The X address decoder 204 decodes the internal complementary address signal output from the X address buffer 203 and drives the word line 221.

  (A sense latch circuit (not shown) is provided on one end side of the bit line 220, and a data latch circuit (not shown) is also provided on the other end). The bit line 220 is selected by the Y gate array circuit 207 based on a selection signal output from the Y address decoder 206. The Y address signal input from the external input / output terminals I / O0 to I / O7 is preset in the Y address counter 205, and the address signal sequentially incremented from the preset value is given to the Y address decoder 206. The bit line 220 selected by the Y gate array circuit 207 is conducted to the input terminal of the output buffer 208 during the data output operation, and is conducted to the output terminal of the input buffer 210 via the data control circuit 209 during the data input operation. The bit line 220 is provided with a data register 215 that holds write data for one sector. Write data is input 8 bits at a time from the external input / output terminals I / O0 to I / O7, stored in the data register 215, and when the write data for one sector is held, the sector address specified by the X address Is written to.

  Connections between the output buffer 208 and the input buffer 210 and the input / output terminals I / O 0 to I / O 7 are controlled by the multiplexer 202. Commands supplied from the input / output terminals I / O 0 to I / O 7 are given to the mode control circuit 211 via the multiplexer 202 and the input buffer 210. The data control circuit 209 makes it possible to supply the memory array 201 with logical value data in accordance with the control of the mode control circuit 211 in addition to the data supplied from the input / output terminals I / O0 to I / O7.

  The control signal buffer circuit 212 is supplied with a chip enable signal CE, an output enable signal OE, a write enable signal WE, a serial clock signal SC, a reset signal RES, and a command enable signal CDE as access control signals. The mode control circuit 211 controls the signal interface function with the outside according to the state of these signals, and controls the internal operation according to the command code.

  When a command or data is input to the input / output terminals I / O0 to I / O7, the signal CDE is asserted. If the command is a command, the signal WE is further asserted, and if it is data, WE is negated. If it is an address input, the signal CDE is negated and the signal WE is asserted. Thereby, the mode control circuit 211 can distinguish commands, data, and addresses that are multiplexed from the external input / output terminals I / O0 to I / O7. The mode control circuit 211 can assert the ready / busy signal RDY / Busy during an erase or write operation to notify the state to the outside.

  The internal power supply circuit 213 generates various operation power supplies 222 for writing, erasing verification, reading, and the like, and supplies them to the X address decoder 204 and the memory cell array 201.

  The mode control circuit 211 controls the flash memory 20 as a whole according to the memory command. The operation of the flash memory 20 is basically determined by a memory command. Memory commands assigned to the flash memory 20 are commands such as read, erase, additional write, rewrite, erase verify, reset, and status register read / clear, as exemplified in Table 2.

  The flash memory 20 has a status register 214 to indicate its internal state, and the contents can be read from the input / output terminals I / O0 to I / O7 by asserting the signal OE. For example, according to the additional write command, the mode control circuit 211 controls the data write, and the write result is verified. In the case of an error, retry is performed a predetermined number of times, and in the case of an error, a write abnormality flag is set in the status register 214. After issuing the additional write command, the controller 30 can confirm whether or not the data writing has been completed normally by issuing a status register read command.

  The memory interface control unit 37 in FIG. 8 includes a disk address (track number, sector number, etc.) indicating an access head position designated by the host device, and a memory address (block number, sector number, chip number) of the (flash) memory. , Etc.) are defined, and the disk address designated by the host device is converted into the corresponding (flash) memory address by referring to it. For example, FIG. 10 shows a memory map of a 64-Mbit flash memory, and one sector is composed of data bytes in units of 512 bytes and control bytes of 16 bytes. The memory interface control unit 37 controls sequential read / write access for each sector of the memory. In the data write mode, the write data accumulated in the data buffer 39 is cut out in units of 512 bytes, and transferred to the flash memory in units of 8 bits, for example, via the memory interface 12 and the memory bus 301. In the read mode, read data is transferred from the flash memory in units of 8 bits and written to the data buffer 39. The internal state read from the status register 214 of the flash memory 20 is written to the Control / status register. The read data of the data buffer 39 that has been read normally is sent to the host device via the host interface 11 by the host interface control unit 35. The data written to the flash memory 20 in the write mode is read again and verified with the written data to confirm that the data has been normally written. For the read / write control of the flash memory 20 described above, the above memory command (Table 2) and access control signal are issued. The memory interface control unit 37 multiplexes and transmits and receives memory commands, addresses, and data via the memory interface 12.

  Control bytes, which are redundant bytes added to each sector shown in FIG. 10, identify error correcting code (ECC), storable area / alternative area / defective area, etc. Information such as a code, a logical address, and the number of rewrites is written. Each sector is checked at an initial stage or at any time to check whether it can be stored, and the sector in which an error has occurred is managed with the identification code of the “bad area”. In the flash memory shown in FIG. 10, it is guaranteed that the number of good sectors (storable area / sector used as alternative area) is at least 16,057 (98%). Further, the memory cell in the data area where the write error occurs is replaced with a memory cell of Control bytes.

  The data transfer control unit 36 shown in FIG. 8 stores the write data sent from the host device in the data buffer 39 and then creates an error correction code ECC based on the BCH code (Bose-Chaudhuri-Hocquenghem code) theory. Write to Control bytes. The memory interface control unit 37 writes the write data stored in the data buffer 39 and the error correction code ECC into the memory. Further, the data transfer control unit 36 stores the read data read from the memory in the data buffer 39, and then performs error correction processing of the read data based on the error correction code ECC in the Control bytes read simultaneously. I do. In the error correction processing, for example, a bit error in data of 512 bytes per sector is corrected up to 2 bits.

  Further, when security is particularly required for information stored in the memory, various cryptographic processes are performed. The data transfer control unit 36 performs an encryption process on the write data held in the data buffer 39 and a decryption process on the read data. Examples of ciphers used include “MULTITI2” and US encryption standard DES (Data Encryption Standard) for “common key cipher” and RSA cipher for “public key cipher”. It is also conceivable that the read data sent to the host device side is encrypted and the data received from the host device is decrypted.

  As described above, by dividing the controller 30 shown in FIG. 8 into functional blocks, when the interface specification with the host device changes, only the function of the host interface control unit 35 can be changed and dealt with. Further, when the memory specification changes, it is possible to cope with the same by changing only the function of the memory interface control unit 37.

  FIG. 11 shows a connection example when the (flash) memory is further expanded in the embodiment in which the semiconductor device 100 of the present invention shown in FIG. 7 is mounted on a board. The I / O 0 to I / O 7 terminals of the expansion (flash) memory 50 are external to the semiconductor device 100 (on the board), as well as the I / O 0 to I / O 7 terminals of the built-in (flash) memory. Connected to (0) to F_DA (7) terminals. In the memory bus, the built-in (flash) memory and the expansion (flash) memory are connected in the same hierarchy (connection form in which addresses, data, various control signals, etc. are supplied in common). As for the other access control signals, the chip enable signal CE has the output terminals F_CEA_1 and F_CEA_2 of the controller individually connected to the built-in (flash) memory and the expansion (flash) memory, respectively. Similarly, the serial clock signal SC is individually connected to the output terminals F_SC_A1 and F_SC_A2 of the controller. Similarly, the ready / busy signals RDY / Busy are individually connected to the output terminals F_RDY_1 and F_RDY_2 of the controller. The command enable signal CDE, the output enable signal OE, and the write enable signal WE are connected to the signal terminal of the controller and the signal terminals of the built-in (flash) memory and the expansion (flash) memory in common.

  Accordingly, the memory expansion terminal (external terminal 16 in FIG. 1) for the expansion (flash) memory is a general term for the external terminals of the chip enable signal CE, the serial clock signal SC, and the ready / busy signal RDY / Busy. Become.

  The extended memory 50 is mounted on the board in the form of a package in which a plurality of memory chips are three-dimensionally mounted, for example, as shown in FIG. As the required memory capacity increases, it is considered as a highly likely implementation. For example, the semiconductor chips 51 and 52 are configured as 64-megabit flash memory EEPROM (Electrically Erasable Programmable Read Only Memory). The semiconductor chips 51 and 52 are bonded and fixed with the adhesive layer 5 interposed therebetween with their respective back surfaces facing each other and shifted in the direction orthogonal to the arrangement direction of the electrode pads 4. Each of the semiconductor chips 51 and 52 is supported by a support lead 6B, each electrode pad 4 and each lead 7 are electrically connected by a wire 8, and the whole is sealed by a resin sealing body 9.

  When the extended memory 50 of FIG. 11 has a plurality of chips 51 and 52 as described above, each of the extended memories 51 and 52 has access control signals (chip enable signal CE, serial clock signal SC, ready The busy signal RDY / Busy and the like are individually connected to each other, and are commonly connected to a connection bus between the controller 30 and the built-in memory 20. As described above, the semiconductor disk device in which the expansion memory is added on the motherboard is configured.

  Since the semiconductor device 100 of the present invention described above has a plurality of different types of semiconductor chips built in one package and the test contents are different because they are different types of semiconductor chips, the respective semiconductor chips are connected to each other after the package is assembled. Different tests need to be done. In order to increase the accuracy with which a defective portion is specified in a test, it is necessary to avoid the leakage current caused by one semiconductor chip from being mixed into the input terminal and the output terminal of the other semiconductor chip. As a solution for this, it is conceivable that internal connection between a plurality of chips in the semiconductor device 100 is avoided as much as possible, and each chip is independently provided to an external terminal of the package. Only the ground Vss is shared at a minimum, and the power supply Vcc of each chip is used as an independent terminal, so that the test accuracy of standby current screening can be improved.

  For the test of the semiconductor device 100, it is efficient to perform a two-stage test including a step of simultaneously performing a memory test in a memory test system and a step of performing a controller test at a high speed in a logic test system. This makes it possible to use a test environment for individual semiconductor chips, and has a great effect of shortening the turn-around time (TAT) of development of a semiconductor device.

(Embodiment 2)
FIG. 12 shows an external terminal arrangement plan in consideration of the ease of short-circuit connection outside the semiconductor device 100, which is a different plan from the external terminal example shown in FIG. The concept changed from FIG. 6 is that, in order to shorten the external connection distance between the external terminal from the controller chip 30 and the external terminal from the memory chip 20, the terminals requiring external connection are arranged adjacent to each other as much as possible. That is.

  The first embodiment shown in FIG. 6 is an example in which an existing controller chip and memory chip are mounted in one package. The arrangement of the electrode pads of the controller chip and memory chip is originally for individual packages. The ones decided on are the main. Even if such an existing chip is used, each lead is wired with a wire as shown in FIG. 2 due to the positional relationship in the horizontal direction of a plurality of stacked chips, a slight change in the arrangement of electrode pads, a device for wire connection, etc. An example in which electrode pads are connected and external terminals can be arranged on four sides is shown. However, a burden on the user who has to connect the external terminal by wiring on the board is also conceivable.

  In the second embodiment of FIG. 12, for example, if the arrangement of the electrode pads of the controller is designed to be suitable for MCP use so that the external terminals that require connection between the controller chip and the memory chip are adjacently arranged, It becomes feasible. If the external terminals to be connected are adjacent to each other, the user can easily perform a short-circuit connection on the board. In addition, since there are various restrictions on the arrangement of the electrode pads on the chip, it is considered that the adjacent external terminals to be connected are realized as much as possible.

(Embodiment 3)
FIG. 13 shows an example of a cross-sectional view of a stacked CSP implementing the present invention. As in the first embodiment, for example, the controller chip 30 and the memory chip 20 are housed in one package, and the wiring layer 112 is connected to the electrode portion of the wiring layer 112 by the wire 114 from the electrode pad of each chip. The external terminal 115 is connected to the land portion 117 through the through hole 116 of the insulating substrate 111. The wiring layer 112 is often multi-layered rather than a single layer.

  In the case of the present embodiment, as in the case of the first embodiment, the input / output terminals of the address, data, command, and access control signal of the controller chip 30 and the memory chip 20 are basically not connected internally, but independently. Connect to the external terminal 115. Other signals and power sources are basically connected to the external terminal 115 independently of each other.

  FIG. 14 is an example of a conceptual diagram showing a state of CSP internal connection of each signal that requires external connection and connection in the wiring layer to the external terminal 115 of the CSP of FIG. The signal name is the same as the signal name shown in FIG. As shown in FIG. 14, the reason for connecting to the external terminal 115 is that when the CSP is mounted on the board, the wiring on the board to the external terminal 115 located on the inner side in the arrangement of the external terminals 115 is the external terminal. Since the wiring density has to be increased as the pitch of the array becomes smaller, it tends to be difficult. Therefore, the external terminals to be externally connected on the board are selected by selecting the adjacent external terminals on the inner side as much as possible.

  FIG. 15 shows an example in which the corresponding signal terminals output to the external terminals in FIG. 14 are externally connected on the board.

(Embodiment 4)
In the lead frame type MCM (Multi Chip Module) mounting form as shown in FIG. 16, if the present invention is carried out, that is, each chip is not connected internally but connected to an external terminal independently. As described in 1, the test environment of each chip in the MCM can be the same as the test environment developed for each individual chip. 16A is an example of a module using a circuit board, FIG. 16B is an example of a module using a lead frame, FIG. 16C is an example of a module using a circuit board and a lead frame, and 161 is a first module. 1 LSI chip, 162 is a second LSI chip, 163 is resin, 164 is a wire, 165 is a lead frame, 166 is a thick film resistor, and 167 is a chip capacitor.

(Embodiment 5)
Summarizing the technical idea of the present invention described in the first to fourth embodiments, the present invention can be similarly applied to an object in which a plurality of chips are packaged.

  For example, in the “conventional mounting form” shown in FIG. 17, it is assumed that a plurality of existing chips (package form or bare chip form) mounted on a motherboard or an MCM circuit board and realizing a predetermined function are mounted. If there is a demand to increase the mounting density and a large number of products can be expected, it is conceivable that a plurality of chips with appropriate groupings are contained in one package. In particular, three-dimensional chip mounting is effective in increasing the mounting density.

  As described above, when a plurality of chips are accommodated in one package, in the present invention, the connection between the plurality of chips is not brought into the package as much as possible, and the terminals of each chip are independently connected to the external terminals of the package. It is characterized by putting out. As a result, the environment for testing each chip in the package can be tested in a situation very close to the environment for testing each chip in a single package, or in the same environment. This has the advantage that the existing test environment can be used as it is, and the test reliability can be guaranteed. Furthermore, since the number of man-hours required for test development when developing a new package can be reduced, the development cost can be reduced and the development period can be shortened.

  If some connections between multiple chips are contained in a package, test reliability cannot be guaranteed unless testing is performed by taking measures to remove the effects of the above-mentioned partial connections in the test of each chip. . As described above, a case where a partial connection between a plurality of chips is accommodated in the package may be a case where the wiring length needs to be shortened for high-speed processing.

  The present invention can be applied not only to chips (Chip A, Chip B) {groups of closely related chips} that are directly connected and used on the board shown in FIG. However, the same effect can be considered for chips (ChipD, ChipE) {grouping of distantly related chips} that can be regarded as an indispensable combination for realizing a certain function.

  In particular, the distantly related chip grouping package described above has a configuration in which the connections are independent within the package (the power supply or the ground can be shared), so that one chip is defective. Even if it cannot be used, if other chips can be used, the package can be used within the range of functions of the other chips.

(Embodiment 6)
FIG. 18 shows an example of a package that uses a DRAM as a memory and is combined with a controller that executes image processing and the like.

  Further, FIG. 19 shows an example of a package combining a DRAM and a flash memory. It is expected that demand will increase in the future for mobile phone applications that require a large amount of temporary storage memory such as image communication.

  In any of the above packages, the configuration of the independent terminal of the present invention is conceivable, and the same effect is expected.

(Embodiment 7)
FIG. 21 shows another solution of the semiconductor disk device 100 disclosed in the first embodiment in order to facilitate testing of a plurality of chips housed in the semiconductor package 10. In the semiconductor disk device 100 of the seventh embodiment, a test mode switching external terminal 17 is provided in the semiconductor package 10 and a test mode switching signal is input from the outside. The plurality of chips 20 and 30 in the semiconductor package 10 are internally connected. For example, connection switching selectors 61 and 62 are provided at the intersections with the internal buses 311 and 312 and at the intersections with the internal buses 313, 314, and 315.

  For example, when the test mode of the controller chip 30 is designated according to the test mode switching signal input from the outside, the selector 61 connects the controller chip 30 to the external terminal 12 via the internal bus 311 and connects the internal bus 312. Disconnect from. The selector 62 connects the internal buses 313 and 314 to connect the controller chip 30 to the external terminal 18.

  When the test mode of the memory chip 20 is designated, the selector 61 connects the internal bus 311 on the external terminal 12 side and the internal bus 312 and disconnects the internal bus 311 on the controller side. The selector 62 connects the internal buses 314 and 315, connects the memory chip 20 to the external terminal 18, and disconnects the internal bus 313.

  By switching the test mode as described above, the controller chip 30 or the memory chip 20 can be independently tested by the test system connected to the external terminals 12 and 18. This is the same effect as in the case of testing in the first embodiment by connecting each chip to an independent external terminal.

  When the semiconductor disk device 100 of the present embodiment is mounted on a motherboard and used, a normal mode signal is input to the test mode switching external terminal 17, and the selector 61 connects the internal buses 311 and 312 based on the signal. The selector 62 connects the internal buses 313, 314, and 315. The controller 30 can access the expansion memory 50 connected to the external terminals 12 and 18 in the same hierarchy as the built-in memory 20.

  The connection switching selectors 61 and 62 include a decoder for decoding the test mode switching signal, and the internal bus side to be disconnected is controlled to a high output impedance state by a built-in switch means. The connection switching selectors 61 and 62 can be understood as tri-state (3-state) type output circuits arranged in the output circuits in the plurality of chips 20 and 30.

  It is conceivable that the place where the connection switching selectors 61 and 62 are installed in the semiconductor package 10 is incorporated in an input / output terminal portion in the controller chip 30, for example.

  As shown in FIG. 22, connection switching selectors 63 and 64 are incorporated in the controller chip 30 by being connected to input / output terminal portions (electrode pads) 33 and 34, respectively. The input / output terminal sections 33 and 34 are expected to increase the number of electrode pads due to the connection with external terminals and the memory chip 20, but the connection switching selectors 63 and 64 are built into the controller chip 30. There is. The functions of the connection switching selectors 63 and 64 are substantially the same as the functions of the connection switching selectors 61 and 62 of FIG. However, the connection switching selectors 63 and 64 switch the connection with the controller internal circuit. The test mode switching signal is commonly input to the electrode pad 45 of the controller 30.

  In the embodiment shown in FIG. 22, when the specific examples corresponding to the chip A30 and the chip B20 are given, the combinations shown in Table 3 can be considered.

  In addition, the test mode switching signal terminal 17 described in FIGS. 21 and 22 does not need to be a dedicated external terminal. When the test mode switching signal is substituted by a combination of a plurality of other signals, The switching signal terminal 17 may not be provided.

  If the connection switching selectors 61, 62, 63, and 64 are provided in the package 10 as described above, a test can be performed in an individual test environment for each chip as in the semiconductor disk device 100 described in the first embodiment. I can do it. Also, the difference is that the semiconductor disk device 100 of the present embodiment can incorporate connection wirings 312, 313, 315 between a plurality of chips into the semiconductor package 10.

(Embodiment 8)
FIG. 23 shows a modification of the MCP type semiconductor disk device 100 described in the first and seventh embodiments. In the semiconductor disk device 100 of the present embodiment, the controller 30 selects the internal memory 20 and internally connects the signal path of the chip enable signal CE1 to be activated between the controller 30 and the internal memory 20. Further, the controller 30 outputs chip enable signals CE 2 and CE n for selecting the expansion memories 51 and 52 mounted outside the semiconductor disk device 100 via the external terminal 19. All other input / output signals necessary for the controller 30 to access the memory are internally connected to the built-in memory 20 via the internal bus 316. The internal bus is connected to the expansion memory interface 41, and the controller 30 can access the expansion memories 51 and 52 via the expansion memory bus 301 on the motherboard. In the embodiment of FIG. 23, all other input / output signals are internally connected to the built-in memory 20 via the internal bus 316, but some of the signals are shown in FIG. As shown in FIG. 1, it is conceivable to appropriately take out the connection between the controller 30 and the built-in memory 20 through an external connection through an external terminal.

  The difference between this embodiment and the publicly known example “Japanese Patent Laid-Open No. 6-250799” is that the semiconductor disk device of this embodiment is configured in the MCP format, whereas the publicly known example is on a one-chip LSI. It is a configured semiconductor disk device. The extended memory interface of this embodiment is an interface in which address / data / command is multiplexed. Further, as described above, if the connection between the controller 30 and the built-in memory 20 is performed via an external connection by outputting some signals to an external terminal, the expansion memory interface 41 is expanded memory 51, 52 is a common interface between the built-in memory 20 and the extended memory interface of the above-described known example is clearly different from the interface dedicated to the extended memory.

(Embodiment 9)
FIG. 24 shows a configuration example of a semiconductor disk LSI 60 in which the controller unit 70 and the memory unit 80 are included on one LSI. Even in testing an LSI with such a configuration, in order to test each unit individually and with high reliability, it is considered better to avoid internal connections between the units as much as possible. Therefore, as in the example of the first embodiment, the external terminals 12, 13, 14, 15, 16 of the semiconductor package 10 enclosing the LSI chip and the input / output units 73, 74, 81 of the units 70, 80 are used. , 82 are independently connected to each other. After mounting the semiconductor disk LSI on the board, external terminals are connected on the board to constitute a semiconductor disk device. The controller 70 accesses the memory unit 80 via the external terminal (memory interface) 12, the memory bus 301, and the external terminal 14.

  The difference between the present embodiment and the publicly known example “Japanese Patent Laid-Open No. 6-250799” is that the present embodiment is configured such that the controller and memory configured on a single LSI are not connected internally, and the outside of the semiconductor package 10 The specification is such that the connection is completed by an external connection on the board via the terminal. This is because the memory interface 12 is a common interface between the built-in memory 80 and the expansion memory 50, and is clearly different from the known interface.

  Note that not only the signal connections between the controller unit 70 and the memory unit 80 are all external connections as described above, but only the signal connections that are greatly affected by the connection with other units are tested for individual units. It is conceivable that other signals having a small influence are used as internal connections by connecting them externally.

  Some of the embodiments of the present invention described above are summarized as follows.

<Aspect 1> In a semiconductor device including a first semiconductor chip and a second semiconductor chip in a single package,
A selector that is provided in an internal connection portion of a signal between the first semiconductor chip, the second semiconductor chip, and an external terminal of the package, and switches an internal connection;
A test mode input external terminal for inputting a test mode signal to the selector;
A first test mode in which the selector connects each input / output terminal of the first semiconductor chip independently from each external terminal of the package and disconnects the connection of the second semiconductor chip according to the test mode signal; ,
A second test mode in which the selector connects each input / output terminal of the second semiconductor chip independently from each external terminal of the package according to the test mode signal, and disconnects the connection of the first semiconductor chip; ,
A normal mode in which the selector internally connects the first semiconductor chip and the second semiconductor chip according to a normal mode signal;
A semiconductor device comprising:

  <Aspect 2> The selector is incorporated in the input / output terminal portion of the first semiconductor chip, the input / output terminals of the first semiconductor chip, the input / output terminals of the second semiconductor chip, and the first 2. The semiconductor device according to aspect 1, wherein the input / output terminals of the semiconductor chip and the external terminals of the package are internally connected.

  <Aspect 3> The aspect 1 or aspect 2, wherein the test mode signal is substituted by a combination of a plurality of other signals, and the test mode input external terminal is substituted by a plurality of other signal input external terminals. Semiconductor device.

<Aspect 4> In a semiconductor device including a first semiconductor chip and a second semiconductor chip in a single package,
Each signal electrode pad of the first semiconductor chip and each terminal of the first external terminal group of the package are connected in a one-to-one relationship within the package,
Each signal electrode pad of the second semiconductor chip and each terminal of the second external terminal group of the package are connected one-to-one within the package,
Either a power supply terminal or a ground terminal is commonly connected to the first semiconductor chip and the second semiconductor chip.

<Aspect 5> The first semiconductor chip is placed on the second semiconductor chip, and the surface (back surface) opposite to the circuit formation surface of the first semiconductor chip and the second semiconductor chip. The circuit forming surface of
5. The semiconductor device according to aspect 1 or aspect 4, wherein the support lead portion of the lead frame is adhesively fixed to the circuit forming surface of the second semiconductor chip and sealed with resin.

  <Aspect 6> Of the external terminals independently connected to the input / output signal electrode pads of the first semiconductor chip and the second semiconductor chip, the external terminals connected to the first semiconductor chip The aspect according to any one of aspects 1 to 5, wherein at least one set of the external terminals to be connected to the terminals and the external terminals connected to the second semiconductor chip is disposed adjacent to each other. Semiconductor device.

<Aspect 7> A memory chip;
A host interface having a plurality of input / output external terminals for connection to a host device;
A controller chip for controlling access to the memory chip according to a memory access request received from the host device via the host interface;
A plurality of first external terminals independently connected to each input / output terminal of the controller chip of a signal for the controller chip to access the memory;
A second plurality of external terminals independently connected to each input / output terminal of the memory chip of a signal accessed by the controller;
The semiconductor device is characterized in that the memory is accessed by the controller by externally connecting the first plurality of external terminals and the second plurality of external terminals.

  <Aspect 8> The aspect in which the controller chip further includes a third plurality of external terminals for inputting / outputting access control signals for controlling access to an expansion memory connected to the outside of the semiconductor device. 8. The semiconductor device according to 7.

  <Aspect 9> Of the external terminals connected to the address and data input / output electrode pads of the controller chip and the memory chip, the external terminals connected to the controller chip and the memory chip The semiconductor device according to aspect 7, wherein at least one set of external terminals to be connected to the external terminals is disposed adjacent to each other.

<Aspect 10> A memory chip;
A host interface having a plurality of input / output external terminals for connection to a host device;
A controller chip for controlling access to the memory chip according to a memory access request received from the host device via the host interface;
A plurality of first external terminals connected in a one-to-one relationship with each input / output terminal of the controller chip for a signal for the controller chip to access the memory;
Mounting a semiconductor device on a motherboard, the memory chip having each input / output terminal of the memory chip of a signal accessed from the controller chip and a plurality of second external terminals connected one-to-one;
A semiconductor disk device comprising: a plurality of first external terminals and a plurality of second external terminals connected to each other by wiring on the mother board.

<Aspect 11> A control unit and a memory unit are provided in a single semiconductor chip.
One signal output of the control unit and the first external terminal of the semiconductor chip are independently connected internally,
One signal input of the memory unit and the second external terminal of the semiconductor chip are internally connected independently,
The first and second external terminals of the semiconductor chip are connected outside the semiconductor chip, whereby the connection between the signal output of the control unit and the signal input of the memory unit is completed. A semiconductor device characterized by the above.

<Aspect 12> A control unit and a memory unit are provided in a single semiconductor chip.
The path through which the output signal A of the control unit is input to the memory chip is
A first partial path connecting the output unit of the control unit and the first external terminal of the semiconductor chip;
A second partial path connecting the second external terminal of the semiconductor chip and the input portion of the memory chip; and the first external terminal and the second external terminal of the semiconductor chip are connected to the outside of the semiconductor chip. And a third partial path that is short-circuited to form a semiconductor device.

  <Aspect 13> The control unit has an interface function for responding to an access from a host device, and an interface function for controlling access to the memory unit by converting the access from the host device into an access specific to the memory unit. The semiconductor device according to aspect 11 or aspect 12, which is provided.

  <Aspect 14> Any one of Aspects 1 to 3, wherein the first semiconductor chip is an SRAM or a controller, and the second semiconductor chip is a flash memory (batch erase EEPROM) or a DRAM. A semiconductor device according to an aspect.

  <Aspect 15> The semiconductor device according to aspect 4, wherein only one of the first semiconductor chip and the second semiconductor chip becomes defective in the test and does not function, and only the remaining semiconductor chip functions.

<Aspect 16> A memory chip in a single package;
A host interface having a plurality of input / output external terminals for connection to a host device;
A controller chip for controlling access to the memory chip according to a memory access request received from the host device via the host interface;
A semiconductor device including a memory interface having a plurality of input / output external terminals for the controller chip to access an external expansion memory;
A motherboard on which the semiconductor device is mounted;
A semiconductor disk device comprising: an extension memory connected to a memory interface of the semiconductor device by wiring on the mother board.

  <Aspect 17> The semiconductor disk device according to Aspect 16, wherein the semiconductor device has a package structure in which the memory chip and the controller chip are laminated and sealed with resin.

  <Aspect 18> The semiconductor disk device according to Aspect 16, wherein the expansion memory is mounted on the motherboard in a package form in which a plurality of memory chips are stacked and sealed with resin.

1 is a block diagram of a semiconductor disk device of the present invention. It is a top view of the state which removed the upper part of the resin sealing body of the semiconductor disc device of this invention. It is typical sectional drawing which follows the AA line shown in FIG. It is typical sectional drawing which follows the BB line shown in FIG. It is typical sectional drawing which follows the CC line shown in FIG. It is the example of signal arrangement | positioning allocated to the external terminal of the semiconductor package of the semiconductor disc apparatus of this invention. It is an example of connection wiring when the semiconductor disk device of the present invention is mounted on a board. FIG. 3 is a block diagram of a controller provided in the semiconductor disk device according to the first embodiment of the present invention. 1 is a block diagram of a flash memory provided in a semiconductor disk device according to a first embodiment of the present invention. It is a memory mat of a 64 Mb flash memory provided in the semiconductor disk device according to the first embodiment of the present invention. 2 is an example in which an expansion memory is connected to the semiconductor disk device according to the first embodiment of the present invention. It is the example of signal allocation to the external terminal in consideration of the ease of connecting the semiconductor disk device of Embodiment 2 of this invention on a board. It is sectional drawing of stack type CSP which implements this invention. It is an example which connects each signal to the external terminal of CSP of FIG. It is an example which connects the external terminal of CSP of FIG. 13 on a board. It is an example of the lead frame type MCM which implements this invention. It is a figure explaining the independent terminal 1 packaging of a several chip | tip. It is a figure which shows the example which made the controller and DRAM 1 package. It is a figure which shows the example which packaged DRAM and flash memory in 1 package. It is an example of sectional drawing of the memory cell of flash memory. 2 is a block diagram of a semiconductor disk device incorporating a test selector. 2 is a block diagram of a semiconductor disk device in which a test selector is built in a controller chip. This is an embodiment in which the MCP includes an expansion terminal for expansion memory. 3 is a block diagram in which a semiconductor disk device of the present invention is configured in a system LSI. It is an example of a stacked package of expansion memory.

Explanation of symbols

DESCRIPTION OF SYMBOLS 4 ... Electrode pad, 5 ... Adhesive, 6A ... Suspension lead part, 6B ... Support lead part (bus bar), 7A ... Lead inner part, 7B ... Lead outer part, 8 ... Wire, 9 ... Resin sealing body, 10 ... Semiconductor package, 11 ... Host interface (external terminal for connection to host device), 12 ... Memory interface (external terminal for address / data / command commonly used for built-in memory and expansion memory), 13 ... Built-in memory , External terminals for access control signals common to expansion memories, 14... External terminals for addresses / data / commands connected to internal memories, 15... External terminals for access control signals connected to internal memories, 16. Control signal external terminal (expansion memory terminal), 17 ... Test mode switching external terminal, 18 ... External memory access control external terminal, DESCRIPTION OF SYMBOLS 9 ... External memory chip selection signal external terminal, 20 ... Built-in memory chip, 20X ... Main surface (front surface) of memory chip, 21, 22 ... Electrode pad (group) of built-in memory chip, 30 ... Controller chip, 30X ... Controller chip Main surface (surface), 31 to 34 ... electrode pads (group) of controller chip, 35 ... host interface control unit, 36 ... data transfer control unit, 37 ... memory interface control unit, 38 ... core processor, 39 ... data buffer , 41 ... expansion memory interface, 45 ... electrode pad for mode switching signal of controller chip, 50, 51, 52 ... expansion memory, 60 ... semiconductor disk LSI, 61, 62 ... connection switching selector, 63, 64 ... controller built-in connection switching selector DESCRIPTION OF SYMBOLS 70 ... Controller unit, 71-74 ... Input / output part, 80 ... Memory unit, 81, 82 ... Input / output part, 100 ... Semiconductor disk device, 111 ... Insulating substrate, 112 ... Wiring layer, 113 ... Insulating adhesive layer, DESCRIPTION OF SYMBOLS 114 ... Wire, 115 ... External terminal, 116 ... Through-hole, 117 ... Land part, 118 ... Resin sealing body, 150 ... Mother board, 161 ... 1st LSI chip, 162 ... 2nd LSI chip, 163 ... Resin, 164 ... Wire, 165 ... Lead frame, 166 ... Thick film resistor, 167 ... Chip capacitor, 201 ... Memory matrix, 202 ... Multiplexer, 203 ... X address buffer, 204 ... X address decoder, 205 ... Y address counter, 206 ... Y Address decoder, 207... Y gate array circuit, 208... Output buffer, 209 Data control circuit 210 ... Input buffer 211 ... Mode control circuit 212 ... Control signal buffer circuit 213 ... Internal power supply circuit 214 ... Status register 215 ... Data register 220 ... Bit line 221 ... Word line 222 ... Various operating power supplies, 301... Memory bus, 302... Control bus, 303... (Access control signal), 304... (Extended memory dedicated access control signal), 311, 312 ... internal bus (address / data / command signal path), 313 , 314, 315... Internal bus (access control signal package internal path), 316... Internal bus (internal memory / extended memory common access path), 317, 318... Internal bus (signal connection path with host interface).

Claims (3)

A memory chip,
A first interface having a plurality of input / output external terminals for connection to a host device;
A function of responding to a memory access request received from the host device via the first interface;
A controller chip having a function of converting the memory chip-specific access according to the memory access request and controlling the access of the memory chip in a single package;
Providing a signal interface for the controller chip to access the memory chip at the first plurality of external terminals of the package; and
A semiconductor device, wherein a signal interface for accessing the memory chip is provided in a second plurality of external terminals of the package. A memory chip,
A first interface having a plurality of input / output external terminals for connection outside the package;
A function of responding to a memory access request received from outside the package via the first interface, and a function of converting the access to the memory chip and controlling the access to the memory chip according to the memory access request. Controller chip with a single package,
A signal interface for the controller chip to access the memory chip is provided at a plurality of first external terminals of the package, and a signal interface for the memory chip to be accessed is provided at a plurality of second terminals of the package. Provided on the external terminal of
The memory chip is a semiconductor device characterized in that it is accessed by from the controller chip via the first and second external terminals. The package includes a third external terminal for providing said memory chip and the controller chip both to the supply voltage, and a fourth external terminal for providing a ground voltage to both the controller chip and the memory chip, to have a The semiconductor device according to claim 2 .

Images