JP2003007963A - Semiconductor memory device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To overcome such a problem of a conventional multichip stack type semiconductor memory that since a plurality of chip enable terminals are provided, the number of terminals is increased as compared with a one chip semiconductor device when the semiconductor memory is regarded as one semiconductor device and thereby the package size is increased and compatibility with conventional products is lost. SOLUTION: The semiconductor memory device comprises a first terminal part (CAD) being connected with any one of first or second power supply voltage terminal, and chip selection control circuits (17, 20) for controlling internal chip selection signal based on the state of the first terminal part and the state of any one or more than one of a plurality of address input terminal parts (e.g. the input pad of a most significant bit A22). The chip selection control circuit controls the internal chip selection signal (CEB) to valid or invalid state based on any one or more than one bit of address signals inputted under a set state of the first terminal part and a state where an external chip selection signal is validated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique effective when applied to a semiconductor memory device and further to a multi-chip stack type semiconductor memory device in which a plurality of semiconductor memory chips are housed in one package. The present invention relates to a technique effectively used for increasing the capacity of such a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art Conventionally, in the field of semiconductor integrated circuits, there is a technique for accommodating a plurality of semiconductor chips in a package to improve the packaging density. The ones designed for commercialization are being put to practical use. In such a multi-chip stack type semiconductor memory device, for most input signals such as address signals and control signals, the number of terminals can be reduced by sharing the terminals of the package among a plurality of chips. Moreover, the number of terminals of the package can be reduced by sharing the I / O terminals for inputting / outputting data among the chips.

However, when the I / O terminals are shared, generally, in order to select each chip separately and read / write data from / to a desired chip, a chip enable signal / Regarding the chip selection signal called CE, it is necessary to allocate different terminals of the package for each chip and connect the CE signal pad of each chip and the CE signal terminal of the package with a bonding wire or the like. There wasn't.

[0004]

Therefore, since the conventional multi-chip stack type semiconductor memory device has a plurality of chip enable terminals, when viewed as one semiconductor device, it is compared to a one-chip semiconductor device. As a result, the number of terminals increases, the package becomes larger, and compatibility with conventional products is lost. That is, since it has a plurality of chip enable terminals, it is possible to newly develop a system that uses a memory or configure a memory module that uses a multi-chip stack type semiconductor memory device instead of a conventional memory chip. In such a case, the design data of the existing board cannot be utilized, and it is necessary to redesign the board.

If one package has a plurality of CE signal terminals, a decoder circuit for decoding an address signal and setting any one of a plurality of chip enable signals to an effective level may be provided as an external circuit. In order to access the memory, the device that outputs the address must be configured to generate and output a plurality of chip enable signals, which causes a problem that the design burden on the user increases.

Therefore, there has been proposed an invention of a multi-chip stack type semiconductor memory device in which a chip enable terminal is shared by two chips and a chip can be selected by an address signal (most significant bit) (Japanese Patent Application No. Hei 10 (1999) -135242). 11
-207701). However, in this prior invention, although a schematic configuration and device structure of a multi-chip stack type semiconductor memory device are disclosed, a specific circuit configuration or a specific circuit configuration that makes it possible to select any chip by the most significant bit of an address, No manufacturing technique such as a specific bonding method is disclosed.

An object of the present invention is to provide a multi-chip stack type semiconductor memory device in which a chip enable terminal is shared by a plurality of chips and a chip can be selected by an address signal.

Another object of the present invention is to provide an effective manufacturing method of a multi-chip stack type semiconductor memory device in which a chip enable terminal is shared by a plurality of chips and the chips can be selected by an address signal. is there.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, the semiconductor memory device according to the present invention includes a first terminal portion connected to either the first power supply voltage terminal or the second power supply voltage terminal, a state of the first terminal portion, and a plurality of address input terminals. Any one or two of the parts
A chip selection control circuit for controlling an internal chip selection signal based on the state of the terminal section described above, wherein the chip selection control circuit is enabled by the setting state of the first terminal section and the chip selection signal from the outside. The internal chip select signal is controlled to the valid state or the invalid state based on any one or more bits of the address signal input in the set state.

According to the above-mentioned means, when a plurality of memory chips are combined, the setting state of the first terminal portion is changed to operate as a memory device in which the chip is selected according to an address signal, or Depending on the combination of the setting state of the terminal section and the setting state of the address terminal section, it becomes possible to operate as a storage device having different input / output bit numbers.

Further, in a semiconductor memory device in which a plurality of semiconductor memory chips are housed in one package and corresponding terminals of respective chips are commonly connected to corresponding terminals of the package, the plurality of semiconductor memories are provided. The chip has a first terminal portion that can be set in different states, and an internal chip selection based on the state of the first terminal portion and the state of any one or more of the plurality of address input terminal portions. A chip selection control circuit for controlling a signal, and each chip selection control circuit in the plurality of semiconductor memory chips selects a chip from the outside when the first terminal portions are set in different states. Even if the input address signal is the same when the signal is enabled, the internal chip select signal is enabled in any one of the chips. .

Thus, when a plurality of memory chips are combined, it is possible to operate as a memory device in which the chips are selected according to the address signal by changing the setting state of the first terminal portion. Even if there is, the chip selection signal can be shared, the number of external terminals for the device can be reduced, and it can be handled in the same way as a normal memory chip, so a system using memory was developed. In this case, the existing design board can be used.

Furthermore, a semiconductor memory in which a plurality of semiconductor memory chips are housed in one package, and the terminals of each chip other than the data input / output terminals are commonly connected to the corresponding terminals of the package. In the device, each of the plurality of semiconductor memory chips includes a first terminal portion that can be set to a different state, and a state of the first terminal portion and one or more terminal portions of the plurality of address input terminal portions. A chip selection control circuit for controlling an internal chip selection signal based on a state, wherein each of the chip selection control circuits in the plurality of semiconductor memory chips has the first terminal portion set to the same state and has an address input. When a predetermined one or more of the terminal portions are fixed to the same potential, it is determined that the chip selection signal from the outside has been validated. Respectively configured to enable the internal chip select signal.

Thus, when a plurality of memory chips are combined, the setting state of the first terminal section of each chip and the setting state of a predetermined address input terminal section are matched so that even if there are a plurality of chips, they can be inserted. Since it can be handled in the same way as a normal memory chip in which the number of bits of output data is doubled, it is possible to use an existing design board when developing a system using a memory.

It is desirable that any one or more bits of the address signal should be the most significant bit of the address or two or more bits from the most significant side. As a result, it is possible to realize a multi-chip stack type semiconductor memory device in which a chip is selected according to an address signal without changing the conventional memory chip mat structure or address decoder structure.

Further, according to another invention of the present application, a plurality of semiconductor memory chips are housed in one package, and terminals for data input / output are provided corresponding to each chip in the package, and data input / output of each chip is provided. In the semiconductor memory device in which the terminal portion is separately connected to the corresponding terminals of the package, and the package is provided with a predetermined terminal, the plurality of semiconductor memory chips can be set to different states. 1 terminal part, one of the states of the first terminal part and a plurality of address input terminal parts or 2
And a chip selection control circuit for controlling an internal chip selection signal based on the state of the terminal section described above, wherein each chip selection control circuit in the plurality of semiconductor memory chips has the first
When the terminal parts are set to the same state and one or more predetermined ones of the address input terminal parts are fixed to the same potential, the external chip select signal is validated. In accordance with the above, the first terminal portion of any one of the plurality of semiconductor memory chips is connected to the predetermined terminal of the package, and another semiconductor memory chip The first terminal portion of is connected to any power supply voltage terminal of the package. Thus, the user can select the number of bits of input / output data of the semiconductor memory device by appropriately setting the voltage applied to the predetermined terminal.

Further, preferably, the plurality of semiconductor memory chips are stacked so that the terminal portions are exposed in the same direction, and the respective chips are bonded to each other at a portion inside the terminal portions of the chips. They are bonded to each other by the agent layer. Thus, when the electrical connection between the terminal portion of each chip and the corresponding terminal on the package side is performed by the bonding wire, the wire bonding process is performed even if the terminal portions of the respective chips are laminated so that they appear in the same direction. be able to.

In the method of manufacturing a semiconductor memory device according to the present invention, a plurality of semiconductor memory chips are housed in one package, and the corresponding terminal portions of each chip are commonly connected to the corresponding terminals of the package. In the method for manufacturing a semiconductor memory device, after the completion of the previous step, a test of the plurality of semiconductor memory chips is performed in a wafer state, and after performing a trimming process in a wafer state on a semiconductor memory chip determined to be a good product by the test, A wafer is cut and divided into each chip, and the semiconductor memory chip is set to the first terminal portion and the terminal portion of each chip is connected to the package terminal, and then sealed in the package. Is. As a result, the terminal setting can be performed in the process of connecting the terminal portion of each chip and the terminal of the package while using the memory chip whose state needs to be set. A multi-chip stack type semiconductor memory device can be manufactured without modification. The defective bit relief process may be performed together with the trimming process.

The setting of the first terminal portion is performed by connecting the first terminal portion to one of the power supply voltage terminals provided on the package with a bonding wire. Since the wire bonding technique is a highly reliable technique, setting the first terminal portion using the wire bonding technique can prevent a setting error, and can prevent a multi-chip chip from changing the conventional semiconductor memory process at all. A stack type semiconductor memory device can be manufactured.

Further, the plurality of semiconductor memory chips are stacked so that the terminal portions appear in the same direction,
The process of connecting with the bonding wire is performed for each chip after the process of joining the chips with an adhesive. As a result, the wire bonding process can be performed using the existing device even if the terminals of the respective chips are stacked so that they appear in the same direction.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a package structure of a multi-chip stack type semiconductor memory device to which the present invention is applied, and FIG. 2 shows a block configuration diagram of a circuit.

As shown in FIG. 1, the multi-chip stack type semiconductor memory device of this embodiment has a package 100 in which two memory chips 10A and 10B are stacked.
It is enclosed inside. The memory chips 10A and 10B enclosed in the package 100 in this embodiment are, for example, non-volatile memories such as a flash memory in which data can be electrically written and data can be collectively erased in a predetermined unit. Sex memory.

Although not particularly limited, the memory chips 10A and 10B are laminated in a state of being electrically insulated from each other with a spacer 20 made of an insulator smaller than those chips interposed therebetween. The spacers 20 are provided because the two chips have the same size, and if they are directly overlapped with each other, the bonding pad portion of the lower chip is hidden and wire bonding cannot be performed. The memory chips 10A and 10B and the spacer 20 are joined by a pellet adhesive 170. Memory chip 10
Each of A and 10B may be a binary memory capable of storing 1-bit data in one memory cell, or a so-called multi-level memory capable of storing 2-bit or more data in one memory cell. good.

Reference numeral 110 denotes an insulating substrate made of ceramic or the like. On one surface (inner surface) of the insulating substrate 110, a plurality of bonding electrode terminals 120 are arranged at predetermined intervals along the outer periphery of the chip, and each bonding electrode is formed. Terminal 12
Corresponding to 0, the insulating substrate 110 is provided with a conductive plug 130 embedded so as to penetrate the substrate.
One end (the upper end in the drawing) of these conductive plugs 130 is in contact with the lower surface of any one of the pads 120, and the other end, that is, the portion exposed on the other surface (outer surface) of the substrate 110 (in the drawing). Solder balls 140 are welded to the lower end). The memory chip 10B is the insulating substrate 1
Bonded on top of 10 by pellet adhesive 170.

Further, one end of the bonding wire 150 is coupled to the bonding electrode terminal 120 on the substrate side, and the other end of the bonding wire 150 is coupled to the corresponding bonding pad of the memory chips 10A and 10B, so that the substrate side. The bonding electrode terminals 120 and the corresponding bonding pads of the memory chips 10A and 10B are electrically connected. The memory chips 10A and 10B are bonded on the insulating substrate 110 with the bonding wire 1
The package 100 is configured by being molded with resin 160 in a state of being connected by 50.

As shown in FIG. 2, each of the memory chips 10A and 10B has a memory array 11 in which a plurality of memory cells are arranged in a matrix and a memory array 11 by decoding an input X-system address. X-decoder 12 that sets one word line in the selected level to a selection level, Y-decoder 13 that decodes the input Y-system address and selects the corresponding bit line in memory array 11, and input X-system address And an address buffer 14 which takes in the Y-system address and supplies it to the X-decoder 12 and the Y-decoder 13, and a sense which amplifies the signal read to the selected bit line and gives the potential of the bit line according to the write data. An amplifier & write circuit 15, an input / output circuit 16 for outputting read data and fetching write data from outside the chip, A chip enable control circuit 17 for generating an internal control signal takes in the chip enable signal / CE input from the flop outside, the write enable signal / WE and the reset signal RES, out enable signal /
Input buffer 18 for receiving an external control signal such as OE
And a control circuit 19 for controlling the inside by generating a control signal inside the chip according to the fetched control signal.

The chip enable signal / CE is a signal indicating that the chip is selected, the write enable signal / WE is a signal indicating that the chip is in the write state, and the reset signal RES is a reset state inside the chip. The enable signal, the out enable signal / OE, is a signal indicating that the read data signal is output. Among the pads to which these control signals and address signals are input, the following two pads (CAD, A
For pads other than 22), the memory chips 10A,
Corresponding pads of 10B are commonly connected to corresponding electrode terminals provided on the package by bonding wires. Further, the data input pads I / O0 to I / O15 of each chip are also commonly connected to the corresponding electrode terminals provided in the package.

Memory chips 10A, 10B of this embodiment
Are provided with chip address data setting pads CAD, which are not provided in a normal memory, respectively. In each memory chip 10A, 10B, the most significant bit A22 of the address signals A0 to A22 such as 23 bits supplied from the outside of the chip and the potential applied to the chip address data setting pad CAD are set. Address bit comparison circuits 20 for enabling the chip enable control circuits 17 are provided accordingly. One of the chip address data setting pad CAD of the memory chip 10A and the chip address data setting pad CAD of the memory chip 10B is the first power supply voltage terminal Vcc of the package, and the other is the second power supply of the package. It is connected to the voltage terminal Vss.

FIG. 3 shows the chip enable control circuit 17
And a specific configuration example of the address bit comparison circuit 20 is shown. The chip enable control circuit 17 has an AND gate G1 which receives the chip enable signal / CE and a reset signal RES, an inverter G2 which inverts the output of the AND gate G1 and supplies it to the address bit comparison circuit 20, and an AND gate G1. And an NAND gate G3 that generates an internal chip enable signal CEB based on the output signal from the address bit comparison circuit 20 and the signal from the address bit comparison circuit 20.

On the other hand, the address bit comparison circuit 20 receives the output signal of the inverter G2 of the chip enable control circuit 17 and the address most significant bit A22 as N.
An OR gate G11, an inverter G12 that generates a signal according to the potential applied to the chip address data setting pad CAD, and an exclusive signal that receives the output signal of the inverter G12 and the output signal of the NOR gate G11. OR gate G13 and the exclusive O
An inverter G that inverts the output of the R gate G13 and supplies it to the NAND gate G3 of the chip enable control circuit 17.
24 and.

The operation of the circuit shown in FIG. 3 will be described below. The reset signal RES is a signal whose valid level is high level, and the chip enable control circuit 17 validates the chip enable signal / CE when the reset signal RES is low level. That is, when the reset signal RES is at the low level, the output of the AND gate G1 changes according to the chip enable signal / CE. Chip enable signal /
CE is a signal indicating that the low level is a valid level, that is, a chip selection state, and when both the reset signal RES and the chip enable signal / CE are low level, the output of the AND gate G1 becomes high level.

The output of the AND gate G1 is inverted by the inverter G2 and the address bit comparison circuit 20
Is supplied to the NOR gate G11, the NOR gate G11 changes according to the address most significant bit A22 which is the other input of the NOR gate G11 when the reset signal RES and the chip enable signal / CE are both low level. When either the reset signal RES or the chip enable signal / CE is high level, NO
The output of the R gate G11 is fixed to the low level. In addition, a reset signal RES or a chip enable signal /
When either one of CE is at the high level, the output of the NAND gate G3 at the output stage of the chip enable control circuit 17 is fixed at the high level, and the internal chip enable signal CEB indicates the chip non-selected state.

When both the reset signal RES and the chip enable signal / CE are low level, the NOR gate G11 of the address bit comparison circuit 20 operates as an inverter having the address most significant bit A22 as an input signal, and the address most significant bit A22 is low level. When is NOR
When the output of the gate G11 is high level and the most significant bit A22 of the address is high level, the NOR gate G
The output of 11 becomes low level. Then, the exclusive O which receives the output signal of the NOR gate G11 as an input
Since the R gate G13 is an exclusive OR circuit, the output logic level of the buffer G12 that outputs a signal according to the potential applied to the chip address data setting pad CAD and the output logic level of the NOR gate G11 are the same. When the output of the exclusive OR gate G13 is low, the output of the exclusive OR gate G13 is high when the output logic levels of G11 and G12 are different.

The exclusive OR gate G1
The output of 3 is inverted by the inverter G14 and supplied to the NAND gate G3 at the output stage of the chip enable control circuit 17. Therefore, when the output logic levels of G11 and G12 are different, the internal chip enable signal output from the NAND gate G3. CEB is set to high level indicating a chip non-selected state. On the other hand, when the output logic levels of G11 and G12 are the same, the NAND gate G3 operates as an inverter, and the output is the internal chip enable signal CE.
B is set to the low level indicating the chip selection state according to the other input signal (high level at this time) of the NAND gate G3.

As described above, the circuit of FIG. 3 has the address most significant bit A22 and the chip address data setting pad C.
Depending on the potential applied to AD, the internal chip enable signal CEB is brought into a chip selection state or a non-selection state. Table 1 below shows combinations of the address most significant bit A22 and the potential applied to the chip address data setting pad CAD in the semiconductor memory device using two mem-ops equipped with the embodiment circuit of FIG. The relationship with the operating state is summarized and shown.

[0037]

[Table 1]

As shown in Table 1, the potential applied to the chip address data setting pad CAD is Vss.
In the chip (1), the internal chip enable signal CEB becomes the high level and the chip is in the non-selected state according to the address most significant bit A22 regardless of whether / CE is at the high level or A22. Is low level, when / CE is low level, the internal chip enable signal CEB becomes low level and the chip is selected.

On the other hand, the chip (2) whose potential applied to the chip address data setting pad CAD is Vcc.
In response to the most significant address bit A22, the internal chip enable signal CEB becomes low level when / CE is low level when A22 is high level, and the chip is in the selected state, and / CE when A22 is low level.
Internal chip enable signal CEB regardless of
Becomes a high level and the chip is in a non-selected state.

Further, as shown in (3) of Table 1, the potentials applied to the address most significant bit A22 and the chip address data setting pad CAD are both Vcc (or both V).
ss), the chip similarly changes the internal chip enable signal CEB according to the chip enable signal / CE from the outside. Therefore, by fixing the potential applied to the chip address data setting pad CAD and the terminal to which the most significant bit A22 of the address is input to Vcc in both two chips, the two chips can be brought into the selected state at the same time. .

Therefore, the two enclosed in one package
Separate data input / output electrode terminals are provided in the package corresponding to the data input / output pads of one chip, and a pad to which the chip address data setting pad CAD and the address most significant bit A22 are input is set to Vcc.
It is possible to operate as a memory (× 2n) having a double data width by fixing the value to. For example, 2
Each chip has a storage capacity of 64 Mbits, 1
If 6-bit data is input / output in parallel, 12
It can be configured as a semiconductor memory device having a storage capacity of 8 Mbits and inputting / outputting 32-bit data in parallel.

However, in this case, the chip address A2
Since the 2-input pad is connected to the Vcc terminal in the package, the package does not require an electrode terminal corresponding to the address most significant bit A22. When the chip having the structure as shown in FIG. 2 is configured not as a multi-chip but as a semiconductor memory device in which one chip is housed in one package, an address most significant bit A22 and a chip address data setting pad CAD By fixing both of the potentials applied to Vcc to Vcc inside the package, it is possible to configure a normal semiconductor memory device having a storage capacity of 64 Mbits and inputting / outputting 16-bit data in parallel.

On the other hand, in Tables 1 (1) and (2), each of the two chips has a storage capacity of 64 Mbits.
128 if bit data is input / output in parallel
It is configured as a semiconductor memory device having a storage capacity of M bits and 16-bit data input / output in parallel, and each chip is selectively accessed by an address most significant bit A22.

In the embodiment shown in FIG. 3, the chip enable control circuit 17 to the address bit comparison circuit 20.
The control signal corresponding to the chip enable signal / CE is sent to the NOR gate G11 of the inverter G2 to control the fetching of the address A22, but this signal is not always necessary and may be omitted. .
By controlling the NOR gate G11 with this control signal, it is possible to prevent an increase in power consumption due to a through current flowing through the internal circuit due to a change in the address A22 which is the input of the NOR gate G11 in the chip non-selected state. There is.

Therefore, bit A0 other than address A22
~ Regarding the buffer that takes A21 inside the chip,
Similarly, it is desirable to control the inverter G2 so that it does not operate in the chip non-selected state. Further, in the embodiment of FIG. 3, the chip enable control circuit 17 is provided with the AND gate G1 for controlling the input of the chip enable signal / CE according to the reset signal RES, but the AND gate G1 is also omitted. Is possible.

FIG. 4 shows the chip enable control circuit 17
Another example of the configuration of the address bit comparison circuit 20 is shown. FIG. 4 shows an example of a circuit configuration suitable when a semiconductor memory device is configured with four chips as one set. In this embodiment, two chip address data setting pads CAD1 and CAD2 and an input terminal for the address signal A23 are provided. In response to this, the address bit comparison circuit 20 includes logic gates G11 to G13.
Logic gates G21 to G23 similar to the above are provided, and an AND gate G2 is used instead of the inverter G14.
4 are provided. Then, the address signal A23 and the output of the inverter G2 of the chip enable control circuit 17 are input to the NOR gate G21, and the exclusive O
The output of the NOR gate G21 and the output of the inverter G22 that generates a signal according to the potential applied to the chip address data setting pad CAD2 are input to the R gate G23.

Further, the exclusive OR gate G1
The outputs of 3 and G23 are input to the AND gate G24. The chip enable control circuit 17 is the same as that of the embodiment of FIG. In this embodiment, each of the four chips has a chip address data setting pad CA.
By setting (bonding wire connection) so that the combinations of the voltages Vcc and Vss applied to D1 and CAD2 are different, the internal enable signal CEB of any one of the chips depending on the address signals A22 and A23.
Is set to the low level, and only one of the four chips is selected. However, similar to the embodiment of FIG. 3, the chip address data setting pads CA of all the chips are
By setting the voltage applied to the input pads of D1 and CAD2 and the address signals A22 and A23 to Vcc, it is possible to operate as a memory having a data width four times as large.

Table 2 shows the address most significant bits A22 and A23 and the potentials applied to the chip address data setting pads CAD1 and CAD2 in the semiconductor memory device which uses four memory chips equipped with the embodiment circuit of FIG. The relationship between the combination and the operating state of the chip is summarized and shown.

[0049]

[Table 2]

FIG. 5 shows another configuration example of the address bit comparison circuit 20 shown in FIG. In FIG. 3, the exclusive OR gate G13 that compares the most significant bit A22 of the address signal with the state of the chip address data setting pad CAD is used, but in FIG. 5, the exclusive OR gate G13 of the exclusive OR gate G13 is used. Instead, a selector SEL is provided, and the selector SEL is configured to be controlled by the output of the buffer G12 that generates a signal according to the potential applied to the chip address data setting pad CAD.

Further, in the embodiment shown in FIG. 5, an OR gate G11 'is used instead of the NOR gate G11 shown in FIG. The input of the OR gate G11 'is a signal from the address A22 and the chip enable control circuit 17, like the input of the NOR gate G11, and the OR gate G11' passes the address A22 according to the signal from the chip enable control circuit 17. It acts as a transmission gate that turns on and off.

The data input terminal of the selector SEL is connected to the output of the OR gate G11 'and the OR gate G1.
A signal obtained by inverting the output of 1 ′ by the inverter G16 is input. In this way, by selecting the address most significant bit A22 or its inverted signal which has passed through the OR gate G11 ′ according to the potential of the pad CAD by the selector SEL and supplying it to the chip enable control circuit 17,
Even if the same address A22 is input, the pad C
One is an internal chip enable signal C according to the potential of AD.
On the other hand, the internal chip enable signal CEB is set to the invalid level. As a result, the chip can be selected by the address A22.

In the embodiment shown in FIG. 5, the pad C is used.
The output of the buffer G12 that generates a signal according to the potential applied to AD controls the selector SEL to control the address A2.
However, either the address A22, that is, the OR gate G is selected.
The output of 11 'controls the selector SEL to control the buffer G1.
Alternatively, either one of the two outputs or its inverted signal may be selected and output.

Further, the address bit comparison circuit 20 of the present embodiment can be applied to the embodiment shown in FIG. 4 which is suitable for the case where a semiconductor memory device is constructed with four chips as one set. it can. Specifically, instead of the exclusive OR gates G13 and G23 of FIG. 4, a selector may be used to configure the address bit comparison circuit 20.

FIG. 6 shows another embodiment of the present invention. This embodiment is a modification of the semiconductor memory device in which the two flash memory chips shown in FIGS. 1 and 2 are stacked, and the configurations of the flash memory chips 10A and 10B are the same as those in FIG. The difference from FIG. 2 is that the package is provided with the bit configuration switching terminal BC and the memory chip 1
The chip address setting terminal CAD of one of 0A and 10B (for example, 10A) is connected to the bit configuration switching terminal BC, and 16 data input / output terminals of the package (I / O0 to I / O15). ) Instead of 32 (I / O0 to I / O31), the data input / output pad of one chip (for example, 10A) is connected to the data input / output terminals I / O0 to I / O15 of the package, and the other chip (for example, 10A). The data input / output pad 10B) is connected to the data input / output terminals I / O16 to I / O31 of the package.

The semiconductor memory device of this embodiment is characterized in that the user can use it as both a 16-bit parallel input / output memory and a 32-bit parallel input / output memory. Specifically, the bit configuration switching terminal BC to which the chip address setting terminal CAD of the memory chip 10A is connected
Is connected to the power supply voltage Vss, the chip is selected by the most significant bit A22 of the address and operates as a memory for inputting and outputting 16-bit data in parallel as in the semiconductor memory device of the embodiment of FIG. Therefore, in this case, the data input / output terminals I / O0 to I / O15 of the package and the I / O
16 to I / O 31 are commonly connected to the same 16-bit bus.

On the other hand, when the bit configuration switching terminal BC to which the chip address setting terminal CAD of the memory chip 10A is connected is connected to the power supply voltage Vcc, the two chips are simultaneously selected by the chip enable signal CE, and 32 bits are set. It operates as a memory that inputs and outputs data in parallel. Therefore, in this case, the data input / output terminals I / O0 to I / O15 and I / O16 to I /
O31 is connected to another signal line of a 32-bit bus.

7 and 8 show still another embodiment of the present invention. This embodiment is a development of the semiconductor memory device in which the two flash memory chips shown in FIGS. 1 and 2 are stacked, and a static RAM is further provided on the two stacked flash memory chips 10A and 10B. This is a stack of chips 10C. The configurations of the flash memory chips 10A and 10B are the same as those in FIG. In this embodiment, the static RAM chip 10
Since the size of C is smaller than the size of the flash memory chips 10A and 10B, even if the static RAM chip 10C is stacked on the flash memory chip 10A, the bonding pad of the flash memory chip 10A is not hidden. Static RAM chip 1 with pellet glue 170 on top
0C is joined.

Of the pads provided on these chips 10A, 10B and 10C, the write enable signal / W
Pad to which E is input and address signals A0 to A18
7, the input pads are commonly connected to corresponding electrode terminals 120 provided on the package 100 via bonding wires 150.

Further, as shown in FIG. 8, the data input pads I / O0 to I / O15 of each chip are also commonly connected to the corresponding terminals provided in the package. Regarding the chip enable signal / CE, the pads of the flash memory chips 10A and 10B are commonly connected to the corresponding terminals PCE-F provided in the package as in the above-described embodiment, but the chip of the SRAM chip 10C. The pad to which the enable signal / CE is input is connected to a dedicated terminal PCE-S provided in the package.

The static RAM chip 10C includes a memory array 11, an X decoder 12, a Y decoder 13, an address buffer 14, a sense amplifier & write circuit 15, a data input / output circuit 16, and an input buffer 18 for a control signal such as a write enable signal / WE. , The chip address data setting pad CAD and the chip enable control circuit 17, which have the same structure as a general-purpose SRAM including a control circuit 19 and the like, and are provided in the flash memory chips 10A and 10B of the above-described embodiment. The address bit comparison circuit 20 is not provided.

In the semiconductor memory device of this embodiment, since two flash memories and one SRAM are stacked and housed in one package, compared with the case where the ones housed in different packages are used. The mounting density can be further increased, and the device can be downsized.

Next, an example of a procedure from development to manufacturing of the multi-chip stack type semiconductor memory device of the above embodiment will be described with reference to FIG. First, the logic operation of the memory chip provided with the chip address data setting pad CAD, the chip enable control circuit 17, and the address bit comparison circuit 20 described in the above embodiment and the logic operation are confirmed by simulation (step S200). Next, a layout design is performed based on the logical design data using a design support program called a layout tool (step S201). Then, a mask used for the process is created based on the layout design data (step S202).

Next, a pre-process of forming a plurality of memory chips on the semiconductor wafer using the mask is performed (step S203). Then, a wafer test is performed by applying a probe to the pads of each chip in a wafer state by a tester to perform a test (step S204). Chips determined to be defective in this wafer test are marked, cut into individual chips, and then discarded as defective products. On the other hand, for the chip determined to be non-defective in step S204, the process of setting the relief information of the defective bit by the redundant circuit and the trimming information of the voltage value of the internal power supply circuit in the fuse or the nonvolatile memory element provided on the chip. It is performed (step S205).

When the processing such as probe inspection and repair for all the chips on the wafer is completed, the wafer is cut into each chip (step S206). Then, the chip is mounted on an insulating substrate, and wire bonding for connecting the pads of the chip to corresponding electrode terminals on the substrate side and a packaging process for molding with resin are performed (step S207). In this bonding and packaging process, first, the lower memory chip 10B is attached to the insulating substrate 110.
After bonding with the adhesive pellet 170 and wire bonding, the upper memory chip 10A is bonded with the adhesive pellet 170 on the lower memory chip 10B and wire bonding is performed with respect to this chip 10A. It is good to

Then, in this embodiment, at the time of the wire bonding, the chip address data setting pad CAD of each chip is connected to one of the power supply voltage terminals provided in the package. As a result, the setting process for the chip address data setting pad CAD can be performed without adding any new process. In addition, when the upper memory chip 10A is bonded to the lower memory chip 10B with the adhesive pellet 170 and then the two chips 10A and 10B are collectively wire-bonded, the upper chip interferes. Although it becomes difficult to wire bond the lower chip, the wire bonding process is performed in the existing device by performing the wire bonding to the lower chip 10B and then bonding the upper memory chip 10A and performing the wire bonding. be able to.

As a method of connecting the chip address data setting pad CAD to either power supply voltage terminal, in addition to wire bonding, the chip address data setting pad CAD is previously supplied with the power supply voltage Vcc or Vss.
It is conceivable to provide a fuse to be connected to the chip and cut the fuse before the packaging process. In the case of the fuse, the chip address data setting pad CA
Since there are two chips, one in which D is connected to the power supply voltage Vcc and the other in which Vss is connected to Vss, it is necessary to manage each chip individually. Then, it is not necessary to manage the chips separately, and the cost can be reduced accordingly.

After the packaging process, a pre-shipment test for testing each device with a tester is executed (step S208). The chip determined to be defective in this test is marked and discarded as a defective product in the subsequent sorting step, while the device determined to be non-defective in step S208 is shipped as a product.

FIG. 10 shows the configuration of a memory card as an application example of the semiconductor memory device of the first embodiment (see FIGS. 1 and 2). In FIG. 10, CD is a card body formed of an insulating material, FLM0 to FLM3 are nonvolatile storage devices built in the card body, and CNT is a nonvolatile memory via a data bus DB, an address bus AB and a control bus CB. And a controller connected to the external storage devices FLM0 to FLM3. Nonvolatile storage device FLM0-F
The LM 3 has two chips each having the structure shown in FIG. 2, or 3 even if only one chip is built.
The above chips may be incorporated. Controller CN
T is connected to an external control device such as a microprocessor via a serial input / output terminal SIO, and in response to a command from the control device, a nonvolatile storage device FLM inside the card.
Data is written to and read from 0 to FLM3.

The controller CNT selects a dedicated selection signal / for each of the nonvolatile memory devices FLM0 to FLM3.
CE0, / CE1, / CE2, / CE3 are generated, and one of them is selected. Each non-volatile memory FLM
0 to FLM3, as described in the embodiment of FIG. 2, the chip address data setting pad CAD of the memory chip (10A) is connected to the first power supply voltage Vss of the package, and the other memory chip (10B). The chip address data setting pad CAD is connected to the second power supply voltage terminal Vcc of the package, and one of the chips is set to the selected state according to the address most significant bit (for example, A22).

As can be seen from this application example, by using the semiconductor memory device of the above embodiment, it is possible to construct a memory card which can be handled in exactly the same way as the conventional semiconductor memory and which has double the memory capacity. In the memory card of this application example, the insulating substrate 110 shown in FIG.
To the storage devices FLM0 to FLM3 and the controller CN.
It may be configured as a substrate common to T, and the whole may be molded with resin or the like and enclosed in one package. That is, when a memory card is constructed using a semiconductor memory device having a structure as shown in FIG. 1, the package has a double structure, but each memory device FLM0
If the FLM3 and the controller CNT are mounted on a common substrate, they can be enclosed in one package.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. Figure 1
In the above embodiment, the description has been given of the case where a plurality of memory chips are enclosed in a package in a stacked state.
It can also be applied to the case where a plurality of memory chips are enclosed in a package in a state where they are arranged side by side on one insulating substrate. Further, the address bit for selecting the chip is not limited to the most significant bit of the address, and may be another bit such as the least significant bit.

In the above description, a multi-chip stack type semiconductor memory device mainly composed of a flash memory, which is a field of application which is the background of the invention made by the present inventor, has been mainly described. It can also be used for a semiconductor memory device having a plurality of embedded therein.

[0074]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, the chip enable terminal can be shared by a plurality of chips, and the chip can be selected by the address signal, which can reduce the number of external terminals as a semiconductor memory device and is equivalent to a normal semiconductor memory. Therefore, it is possible to realize a multi-chip stack type semiconductor memory device in which an existing design board can be used when developing a system using a memory. Further, such a semiconductor memory device can be manufactured without changing the conventional semiconductor memory manufacturing process or modifying the manufacturing apparatus.

[Brief description of drawings]

FIG. 1 is a sectional view showing a package structure of an embodiment of a multi-chip stack type semiconductor memory device to which the present invention is applied.

FIG. 2 is a block diagram showing an embodiment of a multi-chip stack type semiconductor memory device to which the present invention is applied.

FIG. 3 is a logical configuration diagram showing a specific example of a chip enable signal control circuit and an address bit comparison circuit.

FIG. 4 is a logical configuration diagram showing another specific example of the chip enable signal control circuit and the address bit comparison circuit.

FIG. 5 is a logical configuration diagram showing still another specific example of the chip enable signal control circuit and the address bit comparison circuit.

FIG. 6 is a block diagram showing another embodiment of a multi-chip stack type semiconductor memory device to which the present invention is applied.

FIG. 7 is a sectional view showing a package structure of still another embodiment of a multi-chip stack type semiconductor memory device to which the present invention is applied.

8 is an SRAM of the semiconductor memory device of the embodiment of FIG.
FIG. 3 is a block configuration diagram showing a configuration example of FIG.

FIG. 9 is a flowchart showing an example of a method of manufacturing a multi-chip stack type semiconductor memory device according to the present invention in the order of steps.

FIG. 10 is a block diagram showing a configuration example of a memory card as an application example of the semiconductor memory device according to the present invention.

[Explanation of symbols]

10A, 10B flash memory chip 10C SRAM chip 17 Chip enable signal control circuit 20 address bit comparison circuit 100 packages 110 insulating substrate 120 electrode terminals 130 conductive plug 140 solder balls 150 bonding wire 160 Mold resin

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Shin Ito             64 Naganuma, Tenno-cho, Minami-Akita-gun, Akita Prefecture Akita Den             Child Co., Ltd. (72) Inventor Masashi Wada             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group F term (reference) 5B025 AD13 AD16 AE02 AE09                 5L106 AA10 CC04 CC05 CC08 CC09                       CC13 CC21 CC31 GG00 GG06

Claims (10)

[Claims] 1. A first terminal portion connected to either the first power source voltage terminal or the second power source voltage terminal, a state of the first terminal portion, and any one of a plurality of address input terminal portions. Or a chip selection control circuit for controlling an internal chip selection signal based on the states of two or more terminal portions, the chip selection control circuit comprising the setting state of the first terminal portion and a chip selection signal from the outside. Is configured to control an internal chip select signal to a valid state or a invalid state based on any one or two or more bits of an address signal input in a valid state. Semiconductor memory device. 2. A semiconductor memory device in which a plurality of semiconductor memory chips are housed in one package, and corresponding terminals of respective chips are commonly connected to corresponding terminals of the package. The semiconductor memory chip includes a first terminal portion that can be set in different states and the first terminal portion.
A chip selection control circuit that controls an internal chip selection signal based on the state of the terminal section and the state of one or more terminal sections of the plurality of address input terminal sections; When the first terminal portions are set to different states, each chip selection control circuit of the above-mentioned circuit is capable of inputting the same address signal while the chip selection signal from the outside is enabled. A semiconductor memory device characterized in that any one of the chips is configured to validate an internal chip selection signal. 3. A semiconductor memory in which a plurality of semiconductor memory chips are housed in one package, and corresponding terminals of each chip other than the data input / output terminal are commonly connected to corresponding terminals of the package. In the device, each of the plurality of semiconductor memory chips has a first terminal portion that can be set in a different state, and one or more terminals of the state of the first terminal portion and the plurality of address input terminal portions. A chip selection control circuit that controls an internal chip selection signal based on the state of each section, and in each of the chip selection control circuits in the plurality of semiconductor memory chips, the first terminal section is set to the same state and When a predetermined one or more terminal portions of the address input terminal portions are fixed to the same electric potential, the chip selection signals from the outside are validated respectively. A semiconductor memory device configured to enable an internal chip selection signal. 4. One or two of the above address signals.
4. The semiconductor memory device according to claim 2, wherein the above bits are the most significant bit of the address or two or more most significant bits of the address. 5. A plurality of semiconductor memory chips are accommodated in one package, terminals for data input / output are provided corresponding to each chip in the package, and a data input / output terminal portion of each chip corresponds to the package. A semiconductor memory device, wherein the package is provided with predetermined terminals while being separately connected to the terminals, wherein the plurality of semiconductor memory chips have first terminal portions that can be set in different states, respectively. And a chip selection control circuit for controlling an internal chip selection signal based on the state of the first terminal portion and the state of any one or more terminal portions of the plurality of address input terminal portions. In each chip selection control circuit in the memory chip, the first terminal portions are set to the same state, and one or more predetermined terminal portions of the address input terminal portions are the same. When fixed to the potential, the internal chip select signal is configured to be enabled in response to the external chip select signal being enabled, and one of the plurality of semiconductor memory chips A semiconductor memory characterized in that the first terminal portion is connected to the predetermined terminal of the package, and the first terminal portion of another semiconductor memory chip is connected to any power supply voltage terminal of the package. apparatus. 6. The plurality of semiconductor memory chips are stacked so that the terminal portions appear in the same direction, and an adhesive layer interposed between the chips in a portion inside the terminal portions of these chips. The semiconductor memory device according to claim 5, wherein the semiconductor memory devices are bonded to each other. 7. A plurality of semiconductor memory chips are housed in one package, and corresponding terminals of the respective chips are commonly connected to corresponding terminals of the package, and each of the plurality of memory chips has a different state. Configurable first
A method for manufacturing a semiconductor memory device having a terminal portion, wherein a plurality of semiconductor memory chips are tested in a wafer state after completion of a pre-process, and the semiconductor memory chips judged to be non-defective by the test After performing the trimming process in the state, the wafer is cut and divided into each chip, and the setting for the first terminal portion of each semiconductor memory chip and the connection between the terminal portion of each chip and the terminal of the package are performed. A method for manufacturing a semiconductor memory device, which comprises encapsulating in a package. 8. The setting for the first terminal portion is the first terminal portion.
8. The method of manufacturing a semiconductor memory device according to claim 7, wherein the step of connecting the terminal portion to any one of the power supply voltage terminals provided in the package with a bonding wire. 9. The plurality of semiconductor memory chips are stacked so that the terminal portions appear in the same direction, and the process of connecting with the bonding wire is performed for each chip after the process of joining the chips with an adhesive. 9. The method of manufacturing a semiconductor memory device according to claim 8, wherein. 10. The method of manufacturing a semiconductor memory device according to claim 7, further comprising a trimming process in the wafer state and a repair process for replacing a defective memory cell detected by the test.