JPH0917964A - Semiconductor device - Google Patents

Abstract

PURPOSE: To enable the change of data by design change and the change of word constitution, by equipping a gate array with an antifuse ROM. CONSTITUTION: In a gate array equipped with an antifuse ROM, the antifuse ROM is composed of a resistor 101 pulled up to power voltage, a transistor 102 for write of antifuse, antifuses 103-106, transistors 107-110 for antifuse selection at the time of write, a pull down resistor 115, and a buffer 116 for read of data. To secure the breakdown strength of the transistor for write of antifuse, the antifuse ROM is arranged in the peripheral area including an i/o part. Or, by connecting the transistors for selection of antifuses at write severally in series, the voltage applied to one transistor is lowered, and the elements other than the transistor for write of antifuses are arranged in a logical region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an antifuse ROM.

[0002]

2. Description of the Related Art It is known that the conduction characteristics of amorphous metals have irreversible characteristics. Amorphous metals usually exhibit non-conducting properties, but when an electric current is passed through them, they exhibit conducting properties. An amorphous metal exhibiting such characteristics is called an antifuse or an antifuse, and a semiconductor memory device using the same has been proposed.

A semiconductor memory device using an antifuse is described in Japanese Patent Laid-Open No. 4-61156. This will be described below with reference to FIG. 701 is a MOS transistor,
702 is a substrate, 703 is a drain, 704 is a gate electrode, 705 is an upper electrode, 706 is a source, and 707 is an antifuse.

While the MOS transistor 701 is turned on by applying a predetermined voltage to the gate electrode 704, the upper electrode 705 is positive between the upper electrode 705 of the antifuse 707 and the source 706 of the MOS transistor 701,
A voltage Vp of several volts is applied in the direction in which the source 706 becomes negative. Then, a current is passed through the upper electrode 705, the drain 703, and the source 706 as a path, and the antifuse 70
Conduct 7 As a result, the electrical resistance of the anti-fuse 707 is reduced and the anti-fuse 707 has a conductive property.

The above is the basic operation of the antifuse.

By the way, in order to build a ROM in a conventional gate array chip, write data must be prepared in advance. For this reason, there is a drawback that the ROM data cannot be changed even if it is desired to change it due to the design change. EE makes it possible to change ROM data
PROM (electrically erasable and programmable RO
M). Recently, a flash RAM, which can be used as a program ROM, has been made.

[0007]

In recent years, such ROMs and EEPROMs have been incorporated in gate arrays. However, it is necessary to determine the data in advance in the ROM, and the data cannot be changed after manufacturing.
In the EEPROM, it is necessary to determine the bit / word structure, and there is a problem that the bit / word structure cannot be corrected by design change.

Therefore, according to the present invention, by using an antifuse in the gate array, it is possible to change the data and the bit / word structure by such a design change.
It is an object of the present invention to provide a semiconductor device containing an OM.

[0009]

[Means for Solving the Problems]

(Means 1) A logic area that is built mainly in the center of the semiconductor chip and includes a logic circuit block that implements predetermined logic processing, and a logic area that is built around the logic area and that is outside the semiconductor chip and the logic circuit. An anti-fuse ROM is provided in a gate array having an input section for handling an input / output signal and a peripheral area including an output section between the blocks.

(Means 2) In the means 1, according to the data of the antifuse ROM, the antifuse RO
It is characterized in that the circuit operation of the logic circuit block connected to M can be changed.

(Means 3) In the means 1, the high breakdown voltage transistors required for writing to the anti-fuse ROM are transistors in the peripheral region.

(Means 4) In the means 1, the antifuse ROM is constituted by the logic area.

(Means 5) The means 1 is characterized in that the voltage can be directly applied to the gate of the write transistor from the external terminal of the chip through the input portion of the peripheral region.

[0014]

【Example】

(Embodiment 1) FIGS. 1 and 2 are a circuit diagram and a time chart, respectively, showing an embodiment of an anti-fuse ROM provided in a semiconductor device according to the invention described in means 1. First, the configuration will be described. In FIG. 1, 101 is a resistor pulled up to a power supply voltage VDD1 during normal operation, 102 is a P-type transistor for antifuse writing, the source of which is connected to the write voltage VDD2, 103 to 106 are antifuses, and 107 to 106 Reference numeral 110 is an N-type transistor for selecting an anti-fuse at the time of writing, the source of which is grounded, 111 to 114 are N-type transistors for selecting an anti-fuse at the time of reading, 115 is a pull-down resistor, and 116.
Is a buffer for reading data. 1 with this configuration
It becomes an anti-fuse ROM of bit x 4 words.

The antifuse ROM can be realized in a process (customization process) after the wiring of the gate array. That is, in FIG. 1, the antifuse 103
1 to 106 can be realized by using amorphous metal for the contacts connecting the aluminum wirings to different wiring layers, and the other constituent elements in FIG. 1 are built in immediately before the customized construction. Therefore, the antifuse ROM can have an arbitrary bit / word configuration and can be changed during design.

Next, the operation of the antifuse ROM will be described. In FIG. 2, 201 is a signal applied to the gate of the P-type transistor 102 for antifuse writing,
202 to 205 are N for antifuse selection at the time of writing
Signals to be applied to the gates of the type transistors 107 to 110, 206 to 209 are signals to be applied to the gates of the N-type transistors 111 to 114 for antifuse selection at the time of reading, and 210 is an output signal of the buffer 116 for reading data. The numbers on the top of the time chart indicate the operating time.

At time 1, an “L” level signal is input to 201 and an “H” level signal is input to 202. As a result, the transistors 102 and 107 are turned on and a current flows through the antifuse 103, and after a certain period of time, the high resistance state is changed to the conductive state. At time 2, 203 is "L"
Therefore, no current flows through the anti-fuse 104, and the resistance remains high. At time 3, the same as at time 1, the antifuse 105 becomes conductive. Time 4 is time 2
And the antifuse 106 remains high resistance.

At time 6, the "H" level is input to the gate of the anti-fuse selecting N-type transistor 111 at the time of reading, and the N-type transistor 111 becomes conductive. At this time, since the anti-fuse 103 is a conductor, the voltage divided by the resistors 101 and 115 is applied to the input of the buffer for reading data. Here, by setting the resistance value of 115 to be higher than 101, “H” is input to the input of the data reading buffer 116 and the buffer output becomes “H”.
Becomes "H".

At time 7, the "H" level is input to the gate of the N-type transistor 112 for selecting the anti-fuse at the time of reading and the N-type transistor 112 becomes conductive. At this time, since the anti-fuse 104 is in the high resistance state, the buffer 11 for reading data is used.
Since "L" is input to the input of 6, the buffer output becomes "L", and 210 at time 7 becomes "L".

Time 8 is the same as time 6, and 210 at time 8 becomes "H".

Time 9 is the same as time 7, and 210 at time 9 becomes "L".

An anti-fuse ROM provided in a semiconductor device can be realized by the above circuits and operation examples.

(Embodiment 2) FIG. 3 is a circuit diagram showing an embodiment according to the invention described in means 2. First, the configuration will be described. In FIG. 3, 301 is the anti-fuse ROM described in FIG. 1, and 302 is the EX-OR gate of the internal logic circuit. Reference numeral 303 denotes a register that can be controlled by the chip external terminals 304 and 305, and its output is connected to the read terminals RD0 to RD3 of the antifuse ROM 301.

In the antifuse ROM 301, "H" is written in the first word, "L" is written in the second word, "H" is written in the third word, and "L" is written in the fourth word. .

"LL" is added to the external terminal 304 of the register 303.
When a rising signal is input to the external terminal 305 after "LL" is input, the output of the register 303 becomes "LLLL", whereby the antifuse ROM output outputs "H" which is the first word data. This allows EX-O
The R gate 302 operates as an inverter.

"LL" is added to the external terminal 304 of the register 303.
When a rising signal is input to the external terminal 305 after “LH” is input, the output of the register 303 becomes “LLLLH.” As a result, the antifuse ROM output outputs “L” which is the second word data. With this, EX-
The OR gate 302 operates as a buffer.

In this embodiment, EX-O is used as an internal logic circuit.
The R gate is used as an example, but this is an AND gate, O
R gate, other combination gate, and flip gate
Similar effects can be obtained by connecting to a sequential circuit such as a flop.

The antifuse ROM and the internal logic circuit are connected as described above, and the circuit operation can be changed by controlling the output of the ROM. The data of the anti-fuse ROM can be arbitrarily written after the gate array is manufactured. Therefore, in the same gate array, R
By changing the data of the OM, it is possible to realize the circuit operation of different specifications.

(Embodiment 3) FIG. 4 is a circuit diagram showing an embodiment according to the invention described in means 3. First, the configuration will be described. In FIG. 4, 401 is a semiconductor chip, and 402
Is a logic area including a logic circuit block that realizes a predetermined logic process, and 403 is a peripheral area including an input unit and an output unit that handle input / output signals.

The writing transistor of the anti-fuse ROM needs to flow a sufficient current through the anti-fuse as described in the problem, and requires a higher voltage than the normal operating voltage. Therefore, when configuring an antifuse ROM, the breakdown voltage of the antifuse writing MOS transistor becomes a problem. Generally, with the miniaturization of the semiconductor process, the breakdown voltage of the transistor is lowered, and it is necessary to increase the integration degree of the logic region 402, so that the miniaturization is advanced and the operating voltage tends to be lowered. The operating voltage of the logic area of the gate array of the fine process of 0.5 micron or less currently commercialized is 3V.

Due to miniaturization, the operating voltage of the internal logic area is 3
Although the lower voltage such as V is progressing, peripheral area 4 is required because of the necessity of interfacing with the existing 5V components.
No. 03 requires breakdown voltage. When the circuit configuration as shown in FIG. 1 is adopted, the withstand voltage is secured by disposing the anti-fuse ROM in the peripheral region 403 and increasing the oxide film pressure of the gate of the MOS transistor in this region. Therefore, the peripheral region 403 can be provided with the anti-fuse ROM.

(Embodiment 4) FIG. 5 is a circuit diagram showing an embodiment of an antifuse ROM provided in the semiconductor device according to the invention described in means 4. First, the configuration will be described. In FIG. 5, 501 is a resistor pulled up to the power supply voltage VDD1 during normal operation, 502 is a P-type transistor for antifuse writing, and its source is the writing voltage VDD2.
503 to 506 are antifuses and 507
˜514 are N-type transistors for anti-fuse selection at the time of writing, and 515-518 are N-type transistors for anti-fuse selection at the time of reading 508, 510, 512.
The source of 514 is grounded, 519 is a pull-down resistor, and 520 is a buffer for reading data. In this configuration, a transistor is connected in series to each of the anti-fuse selecting N-type transistors 107 to 110 at the time of writing in the circuit diagram of FIG.

The case of writing to the antifuse 503 will be described. "L" for transistor 502, 5
"H" is applied to the gates of 07 and 508. Since the anti-fuse 503 is in the high resistance state in the initial stage of application, the voltage VDD2 is applied to the transistor 502. As time passes, the antifuse 503 changes to a conductor and the voltage VDD2 is applied to the transistor 507. Here, since the transistors 507 and 508 are connected in series, the voltage applied to each transistor is divided and becomes half of the voltage VDD2. Transistor 50
2 needs to be a high breakdown voltage transistor, while the breakdown voltage of the transistors 507 to 514 need only be half.

By connecting the transistors in series as described above, the voltage applied to one transistor can be reduced. As a result, elements other than the transistor 502 can be arranged in the logic area, and a large-scale ROM can be configured as compared with the case where the anti-fuse ROM is arranged in the peripheral area.

(Embodiment 5) FIG. 6 is a circuit diagram showing an embodiment according to the invention described in means 5. First, the circuit configuration will be described. In FIG. 6, reference numeral 601 denotes a semiconductor chip,
2 is an anti-fuse ROM built in the chip.
Reference numeral 603 is a writing transistor in the anti-fuse ROM 602. This writing transistor 603
The gate of is connected to the external terminal 604, and the voltage can be controlled directly from the outside of the chip.

It has become clear from studies that the conduction characteristics of the antifuse can be stabilized by controlling the amount of current flowing through the antifuse. Therefore, by controlling the voltage applied to the gate of the writing transistor 603 in an analog manner, the current flowing into the antifuse is controlled.

Therefore, the conduction characteristic of the antifuse can be stabilized by controlling the voltage applied to the gate of the writing transistor 603 without changing the voltage during writing.

[0038]

According to the invention described in the means 1, since the semiconductor device is provided with the anti-fuse ROM, arbitrary data can be written in the ROM.

According to the invention described in the means 2, since the semiconductor device is provided with the anti-fuse ROM and is connected to the operation of the internal logic circuit, the read data of the ROM causes
The circuit operation can be changed.

According to the invention described in the means 3, by disposing the anti-fuse ROM in the peripheral region, it is possible to have a sufficient breakdown voltage against a high voltage at the time of writing.

According to the invention described in the means 4, by arranging a part of the anti-fuse ROM in the logic area,
A ROM having a large word structure can be formed.

According to the invention described in the means 5, by connecting the gate input of the writing transistor of the anti-fuse ROM to the external terminal of the chip, it is possible to control the current during writing.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of an anti-fuse ROM included in a semiconductor device according to means 1 of the present invention.

FIG. 2 is a time chart showing an embodiment of an anti-fuse ROM provided in the semiconductor device according to means 1 of the present invention.

FIG. 3 is a circuit diagram showing an embodiment according to means 2 of the present invention.

FIG. 4 is a circuit diagram showing an embodiment according to means 3 of the present invention.

FIG. 5 is a circuit showing an embodiment of an anti-fuse ROM provided in the semiconductor device according to means 4 of the present invention.

FIG. 6 is a circuit diagram showing an embodiment according to means 5 of the present invention.

FIG. 7 is a diagram showing a conventional technique.

[Explanation of symbols]

Reference numeral 101 ・ ・ ・ ・ ・ ・ A resistor pulled up to the power supply voltage during normal operation 102 ・ ・ ・ ・ ・ ・ N-type transistor for antifuse writing 103 to 106 ・ ・ ・ Antifuse 107 〜 110 ... N-type transistor for antifuse selection at the time of writing 111-114 ... N-type transistor for antifuse selection at the time of reading 115 ... .... Buffers for reading data

Claims (5)

[Claims] 1. A logic area, which is built mainly in a central portion of a semiconductor chip and includes a logic circuit block that realizes a predetermined logic process, and a logic area that is built around the logic area and is located outside the semiconductor chip and the logic area. A semiconductor device comprising an anti-fuse ROM in a gate array having an input section for handling input / output signals and a peripheral area including an output section with a circuit block. 2. The semiconductor device according to claim 1, wherein the circuit operation of the logic circuit block connected to the anti-fuse ROM can be changed by the data of the anti-fuse ROM. 3. The semiconductor device according to claim 1, wherein a transistor in the peripheral region is used as a high breakdown voltage transistor required for writing in the anti-fuse ROM. 4. The semiconductor device according to claim 1, wherein the anti-fuse ROM is formed of the logic area. 5. The semiconductor device according to claim 1, wherein a voltage can be directly applied from an external terminal of the chip to the gate of the write transistor of the anti-fuse ROM through the input portion of the peripheral region.