US11705188B2

US11705188B2 - Output buffer circuit with metal option

Info

Publication number: US11705188B2
Application number: US17/529,101
Authority: US
Inventors: Toshiaki Tsukihashi; Kenichi Watanabe; Kazuyuki Morishige; Moeha Shibuya; Kumiko Ishii
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2020-02-25
Filing date: 2021-11-17
Publication date: 2023-07-18
Anticipated expiration: 2040-02-25
Also published as: US20220076736A1; CN113380832A; US20210264967A1; US11183232B2

Abstract

Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.

Description

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No. 16/800,899, filed Feb. 25, 2020. These applications and patents am incorporated by reference herein in their entirety and for all purposes.

BACKGROUND

In a semiconductor device such as a DRAM, a large current flows through a transistor that configures an output buffer. Therefrom, when a semiconductor device is used for a long time, it may cause a change of the shape of a wiring pattern connected to the output buffer due to a migration phenomenon. Particularly, when the cross-sectional area of the wiring pattern becomes small due to miniaturization, the density of a current flowing through the wiring pattern becomes high, so that there is a risk of disconnection caused by the migration phenomenon.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a configuration of a semiconductor device according to the present disclosure.

FIG. 2 is a block diagram showing a circuit of a data output system included in an I/O circuit.

FIG. 3 is a circuit diagram of a unit driver.

FIG. 4 is a circuit diagram of a circuit that generates enable signals.

FIG. 5 is a schematic plan view showing a layout of a main driver.

FIGS. 6A to 6C ae circuit diagrams showing several configurations of a main driver that is switched by a metal option.

FIGS. 7A to 7C ae layout diagrams showing several configurations of a main driver that is switched by a metal option.

DETAILED DESCRIPTION

Various embodiments of the present invention will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized, and structural, logical and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein ae not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

A semiconductor device 10 shown in FIG. 1 is a DRAM, for example, and includes a memory cell array 11, an access control circuit 12 that makes access to the memory cell array 11, and an I/O circuit 13 that inputs and outputs data to and from the memory cell array 11. The access control circuit 12 makes access to the memory cell array 11 on the basis of a command address signal CA input from an external controller via command address terminals 14. In a read operation, data DQ read out from the memory cell array 11 is output to external data I/O terminals 15 via the I/O circuit 13. In a write operation, data DQ input from an external contoller to the external data I/O terminals 15 is supplied to the memory cell array 11 via the I/O circuit 13.

FIG. 2 shows circuit blocks as a circuit of a data output system included in the t/O circuit 13, which correspond to one external data I/O terminal 15. As shown in FIG. 2 , the I/O circuit 13 includes a pull-up circuit 21, a pull-down circuit 22, and pre-emphasis

circuits

23 and 24. The pull-up circuit 21 is activated in a pull-up operation, that is, while high-level read data DQ is output from the external data VO terminal 15. The pull-down circuit 22 is activated in a pull-down operation, that is, while low-level read data DQ is output from the external data I/O terminal 15. Each of the

pre-emphasis circuits

23 and 24 temporarily lowers its output resistance only during a period of data transition, so as to compensate a skin resistance loss and a dielectric loss generated in a high-frequency operation. Therefore, also in the high-frequency operation, it is possible to allow data transition to occur with an appropriate slew rate and to drive the external data I/O terminal 15 with a set resistance in a steady state.

Pull-up data DATAu is supplied to the pull-up circuit 21 and the pre-emphasis circuit 23. Pull-down data DATAd is supplied to the pull-down circuit 22 and the pre-emphasis circuit 24. A calibration code signal ZQ and a driver-strength selection signal DS are supplied to the pull-up circuit 21 and the pull-down circuit 22. The pull-up circuit 21 has a configuration in which a plurality of unit drivers 30 are connected in parallel. The unit drivers 30 have the same circuit configuration as each other, and one or two or more unit divers 30 is/are selected on the basis of the driver-strength selection signal DS. The pull-down circuit 22 has a configuration in which a plurality of unit drivers 40 are connected in parallel. The unit drivers 40 have the same circuit configuration as each other, and one or two or more unit drivers 40 is/are selected on the basis of the driver-strength selection signal DS.

As shown in FIG. 3 , each unit driver 30 includes a main driver 31 and a sub-driver 32. The main driver 31 includes four N-channel MOS transistors 311 to 314 connected in parallel. Sources of the transistors 311 to 314 are connected to the external data I/O terminal 15, and a power-supply potential VDDQ is supplied to drains of the transistors 311 to 314. An enable signal En or a ground potential GND is supplied to gate electrodes of the transistors 311 to 314. In the example shown in FIG. 3 , the enable signal En is supplied to the gate electrode of the transistor 311 and the ground potential GND is supplied to the gate electrodes of the other transistors 312 to 314, h is determined, by a metal option in manufacturing, whether to supply the enable signal En to the gate electrodes of the transistors 311 to 314. As for the transistors 312 to 314 to which the ground potential GND is supplied to the gate electrodes, sources thereof may be disconnected from the external data I/O terminal 15 by the metal option. In this case, it is not always necessary to supply the ground potential GND to the gate electrodes.

The enable signal En is always supplied to the gate electrode of the transistor 311, which is among the transistors 311 to 314 that configure the main driver 31. As in the example shown in FIG. 3 , when the ground potential GND is supplied to the gate electrodes of the other transistors 312 to 314, the transistor that is activated in the main driver 31 is one. Therefore, the slew rate of the unit driver 30 becomes minimum. In a case where it is necessary to set the slew rate to be higher, wirings are switched by the metal option in a manufacturing stage in such a manner that the enable signal En is supplied to the gate electrodes of the

transistors

311 and 312 and the ground potential GND is supplied to the gate electrodes of the

other transistors

313 and 314, so that the number of transistors activated in the main driver 31 becomes two. Further, by designing wirings in such a manner that the enable signal En is supplied to the gate electrodes of the transistors 311 to 313 and the ground potential GND is supplied to the gate electrode of the other transistor 314, the number of transistors activated in the main driver 31 becomes three and the slew rate becomes even higher. By designing the wirings in such a manner that the enable signal En is supplied to the gate electrodes of all the transistors 311 to 314, the number of transistors activated in the main driver 31 becomes four and the slew rate becomes maximum. The sizes of the transistors 311 to 314 may be the same as one another.

The sub-driver 32 includes seven transistors 321 to 327. Sources of the transistors 321 to 327 are connected to the external data I/O terminal 15, and the power-supply potential VDDQ is supplied to drains of the transistors 321 to 327. An enable signal En1 is supplied to a gate electrode of the transistor 321, an enable signal En2 is commonly supplied to gate electrodes of the

transistors

322 and 323, and an enable signal En3 is commonly supplied to gate electrodes of the transistors 324 to 327. The sizes of the transistors 321 to 327 may be the same as one another. Accordingly, it is possible to adjust the impedance of the unit driver 30 to eight levels by using the sub-driver 32.

It is also possible that the enable signals En and En1 to En3 are generated on the basis of the pull-up data DATAu and the calibration code signal ZQ. In the example shown in FIG. 4 , the enable signal En is generated by buffering the pull-up data DATAu by using a buffer circuit 50. Further, the enable signals En1 to En3 are generated by logic synthesis of bit signals ZQ1 to ZQ3 that configure the calibration code signal ZQ and the pull-up data DATAu by AND gate circuits 51 to 53, respectively.

FIG. 5 is a schematic plan view illustrating a layout of the main driver 31. The transistors 311 to 314 that configure the main driver 31 are arranged between

wiring patterns

61 and 62 that extend in the X-direction in a plan view. The wiring pattern 61 is connected to the external data I/O terminal 15, and read data DQ appears thereon. The power-supply potential VDDQ is supplied to the wiring pattern 62. As shown in FIG. 5 , the

transistors

311, 314, 313, and 312 are arranged in the X-direction in this order. On the left side of the leftmost transistor 311 in FIG. 5 , a diffusion region SC1 for supplying a fixed potential to a semiconductor substrate is arranged. On the right side of the rightmost transistor 312 in FIG. 5 , a diffusion region SC2 for supplying a fixed potential to the semiconductor substrate is arranged.

The transistor 311 is constituted by a source region 311S, a drain region 311D, and a gate electrode 311G. The source region 311S is connected to a wiring pattern 71 via a contact electrode 81, and the drain region 311D is connected to a wiring pattern 72 via a contact electrode 82. The transistor 314 is constituted by a source region 314S, a drain region 314D, and a gate electrode 314G. The source region 314S is connected to a wiring pattern 73 via a contact electrode 83, and the drain region 314D is connected to a wiring pattern 74 via a contact electrode 84. The transistor 313 is constituted by a source region 313S, a drain region 313D, and a gate electrode 313G. The source region 313S is connected to a wiring pattern 75 via a contact electrode 85, and the drain region 313D is connected to a wiring pattern 76 via a contact electrode 86. The transistor 312 is constituted by a source region 312S, a drain region 312D, and a gate electrode 312G. The source region 312S is connected to a wiring pattern 77 via a contact electrode 87, and the drain region 312D is connected to a wiring pattern 78 via a contact electrode 88. In the example shown in FIG. 5 , the source regions 311S to 314S are located on the left side and the drain regions 311D to 314D are located on the right side; however, the positional relation between them can be reversed.

The wiring patterns 71 to 78 are wirings provided in a second wiring layer located below a first wiring layer in which the

wiring patterns

61 and 62 are provided, and all the wiring patterns extend in the Y-direction. Tungsten may be used as the material for the wiring patterns 71 to 78, and aluminum or copper having a resistance lower than that of tungsten may be used as the material for the

wiring patterns

61 and 62. Here, when it is assumed that the X-direction width of each of the

wiring patterns

71 and 72 is W1, the X-direction width of each of the

wiring patterns

73 and 74 is W4, the X-direction width of each of the

wiring patterns

75 and 76 is W3, and the X-direction width of each of the

wiring patterns

77 and 78 is W2, those widths satisfy a relation of W1>W2>W3>W4.

As shown in FIG. 5 , the

wiring patterns

71, 73, 75, and 77 overlap with the wiring pattern 61, and the

wiring patterns

72, 74, 76, and 78 overlap with the wiring pattern 62. The

wiring patterns

72, 74, 76, and 78 are connected to the wiring pattern 62 via

contact electrodes

92, 94, 96, and 98, respectively. With this configuration, the power-supply potential VDDQ is supplied to all the drain regions 311D to 314D of the transistors 311 to 314. Meanwhile, in the example shown in FIG. 5 , whereas the wiring pattern 71 and the wiring pattern 61 are connected to each other via contact electrodes 91, any contact electrode is not provided between each of the

wiring patterns

73, 75, and 77 and the wiring pattern 61, so that the

wiring patterns

73, 75, and 77 and the wiring pattern 61 are electrically isolated from each other. This means that a contact electrode that connects each of the

wiring patterns

73, 75, and 77 and the wiring pattern 61 to each other is omitted due to a metal option. Accordingly, the main driver 31 shown in FIG. 5 functions as the circuit shown in FIG. 3 . That is, only the transistor 311 is enabled and the other transistors 312 to 314 are disabled.

In a case where only the transistor 311 is enabled and the other transistors 312 to 314 are disabled in this manner, every time high-level read data DQ is output, the transistor 311 is turned on, and thus a large current flows through the

wiring patterns

71 and 72. Therefore, when the cross-sectional area of each of the

wiring patterns

71 and 72 is small, the

wiring patterns

71 and 72 may be deformed by a migration phenomenon, and this may lead to disconnection. However, in the present embodiment, the wiring width W1 of the

wiring patterns

71 and 72 is set to be wider than the wiring widths of the other wiring patterns 73 to 78, and therefore a sufficient cross-sectional area is ensured, so that the migration phenomenon can prevented from happening.

As shown in FIG. 6A, in a case where the

transistors

311 and 312 are enabled and the

other transistors

313 and 314 are disabled by a metal option, the enable signal En is supplied to the gate electrodes of the

transistors

311 and 312. In order to implement this supply, the wiring pattern 77 and the wiring pattern 61 are connected to each other via contact electrodes 97, as shown in FIG. 7A. In this case, when the enable signal En is activated, the two

transistors

311 and 312 connected in parallel are turned on. Because the value of a current flowing through the main driver 31 is kept substantially constant by an external circuit connected to the external data I/O terminal 15, the value of a current that flows through each of the

transistors

311 and 312 is ½ of a current that flows when only the transistor 311 is turned on. In this manner, because the maximum value of the current that flows through the transistor 312 is smaller than the maximum value of the current that flows through the transistor 311, the wiring width W2 of each of the

wiring patterns

77 and 78 is designed to be smaller than the wiring width W1 of each of the

wiring patterns

71 and 72, so that an occupied area is reduced.

As shown in FIG. 6B, in a case where the transistors 311 to 313 are enabled and the other transistor 314 is disabled by a metal option, the enable signal En is supplied to the gate electrodes of the transistors 311 to 313. In order to implement this supply, the wiring pattern 75 and the wiring pattern 61 are connected to each other via contact electrodes 95, as shown in FIG. 7B. In this case, when the enable signal En is activated, the three transistors 311 to 313 connected in parallel are turned on. As described above, because the value of the current flowing through the main driver 31 is substantially constant, the value of a current that flows through each of the transistors 311 to 313 is ⅓ of the current that flows when only the transistor 311 is turned on. Because the maximum value of the current that flows through the transistor 313 is smaller than the maximum value of the current that flows through the transistor 312 in this manner, the wiring width W3 of each of the

wiring patterns

75 and 76 is designed to be smaller than the wiring width W2 of each of the

wiring patterns

77 and 78, so that an occupied area is reduced.

As shown in FIG. 6C, in a case where all the transistors 311 to 314 are enabled by a metal option, the enable signal En is supplied to the gate electrodes of the transistors 311 to 314. In order to implement this supply, the wiring pattern 73 and the wiring pattern 61 are connected to each other via contact electrodes 93, as shown in FIG. 7C. In this case, when the enable signal En is activated, the four transistors 311 to 314 connected in parallel are turned on. As described above, because the value of the current flowing through the main driver 31 is substantially constant, the value of a current that flows through each of the transistors 311 to 314 is ¼ of the current that flows when only the transistor 311 is turned on. Because the maximum value of the current that flows through the transistor 314 is smaller than the maximum value of the current that flows through the transistor 313 in this manner, the wiring width W4 of each of the

wiring patterns

73 and 74 is designed to be smaller than the wiring width W3 of each of the

wiring patterns

75 and 76, so that an occupied area is reduced.

Here, when it is assumed that a space in the X-direction between the

wiring patterns

72 and 73 is S1, a space in the X-direction between the

wiring patterns

74 and 75 is S2, and a space in the X-direction between the

wiring patterns

76 and 77 is S6, the spaces satisfy a relation of S2>S6>S1. Further, when it is assumed that a space in the X-direction between the drain region 311D and the source region 314S is S3, a space in the X-direction between the drain region 314D and the source region 313S is S4, and a space in the X-direction between the drain region 313D and the source region 312S is S7, the spaces satisfy a relation of S3>S7>S4.

As shown in FIG. 5 , the wiring pattern 72 has the wiring width W1 that is the widest width and protrudes in the X-direction beyond the drain region 311D in a plan view. Therefore, the distance between the

transistors

311 and 314 is limited by the minimum space (S1) that is required between the

wiring patterns

72 and 73. As a result, the space S3 between the drain region 311D and the source region 314S is wider than the minimum space (S4) that is required between the drain region 311D and the source region 314S. A relation of S3>S1 is satisfied in the example shown in FIG. 5 .

Meanwhile, the wiring pattern 74 has the wiring width W4 that is the narrowest width and has no protrusion in the X-direction beyond the drain region 314D in a plan view. This is also the same for the wiring pattern 75, and the wiring pattern 75 has no protrusion in the X-direction beyond the source region 313S in a plan view. Therefore, the distance between the

transistors

314 and 313 is limited by the minimum space (S4) that is required between the drain region 314D and the source region 313S. As a result, the space S2 between the

wiring patterns

74 and 75 is wider than the minimum space (S1) that is required between the

wiring patterns

74 and 75. A relation of S2>S4 is satisfied in the example shown in FIG. 5 .

The wiring pattern 77 has the wiring width W2 that is the second widest width and protrudes in the X-direction beyond the source region 312S in a plan view. Therefore, the distance between the

transistors

313 and 312 is limited by the minimum space (S1=S6) that is required between the

wiring patterns

76 and 77. As a result, the space S7 between the drain region 313D and the source region 312S is wider than the minimum space (S4) that is required between the drain region 313D and the source region 312S. A relation of S7>S6 is satisfied in the example shown in FIG. 5 . However, because the amount of the X-direction protrusion of the wiring pattern 77 is smaller than the protrusion amount of the wiring pattern 72, a relation of S3>S7 is satisfied.

The source region 311S of the leftmost transistor 311 has to be apart from the diffusion region SC1 by a predetermined distance or more. Similarly, the drain region 312D of the rightmost transistor 312 has to be apart from the diffusion region SC2 by a predetermined distance or more. Here, generally, the minimum space S5 that is required between the source region 311S and the diffusion region SC1 and the minimum space S8 required between the drain region 312D and the diffusion region SC2 are wider than the minimum space (S4) that is required for a diffusion region between the transistors 311 to 314. Therefore, even in a case where

wiring patterns

101 and 102 extending in the Y-direction are provided at positions overlapping with the diffusion regions SC1 and SC2, respectively, a sufficient space is ensured between the

wiring patterns

71 and 101 and a sufficient space is ensured between the

wiring patterns

78 and 102. By using this, the transistor 311 to which the

wiring patterns

71 and 72 having the widest wiring width W1 are allocated is arranged to be close to the diffusion region SC1, and the transistor 312 to which the

wiring patterns

77 and 78 having the second widest wiring width W2 are allocated is arranged to be close to the diffusion region SC2, so that an occupied area is reduced.

As described above, it is possible to minimize increase of the occupied area while suppressing a migration phenomenon, by arranging the transistor 311 to which the

wiring patterns

71 and 72 having the widest wiring width W1 are allocated and the transistor 312 to which the

wiring patterns

77 and 78 having the second widest wiring width W2 are allocated at both ends in the X-direction, and arranging the transistor 314 to which the

wiring patterns

73 and 74 having the narrowest wiring width W4 are allocated to be adjacent to the transistor 311.

While the above descriptions have focused on the unit driver 30 included in the pull-up circuit 21, also with regard to the unit driver 30 included in the pull-down circuit 22, by applying a layout identical to the unit driver 30, it is possible to minimize increase of an occupied area while suppressing a migration phenomenon.

Although this invention has been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the inventions extend beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the inventions and obvious modifications and equivalents thereof. In addition, other modifications which are within the scope of this invention will be readily apparent to those of skill in the art based on this disclosure. It is also contemplated that various combination or sub-combination of the specific features and aspects of the embodiments may be made and still fall within the scope of the inventions. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying mode of the disclosed invention. Thus, it is intended that the scope of at least some of the present invention herein disclosed should not be limited by the particular disclosed embodiments described above.

Claims

The invention claimed is:

1. An apparatus comprising:

a main driver comprising a plurality of transistors including a first transistor and a second transistor connected in parallel;

wherein the first transistor comprises a first wiring pattern and a second wiring pattern and the second transistor comprises a third wiring pattern and a fourth wiring pattern,

wherein first and second wiring patterns of the first transistor have a greater width in a first direction than the third and fourth wiring patterns of the second transistor,

wherein gate electrodes of the plurality of transistors are configured to connect to a ground potential or a first enable signal based on a wiring of a respective metal option, and

wherein the first transistor of the plurality of transistors is configured to receive the first enable signal and the second transistor of the plurality of transistors is configured to receive the ground potential.

2. The apparatus of claim 1, further comprising an external data terminal,

wherein sources of the plurality of transistors are connected to the external data terminal,

and

wherein drains of the plurality of transistors are connected to a power supply potential.

3. The apparatus of claim 2,

wherein sources of the second plurality of transistors are connected to the external data terminal, and wherein drains of the second plurality of transistors are connected to the power supply potential,

wherein a second enable signal is provided to a first gate electrode of a first transistor of the second plurality of transistors,

wherein a third enable signal is provided to second and third gate electrodes of second and third transistors of the second plurality of transistors, and

wherein a fourth enable signal is provided to remaining gate electrodes of remaining transistors of the second plurality of transistors.

4. The apparatus of claim 3, wherein the first, second, third, and fourth enable signals are generated based on a pull-up data signal and a calibration code signal.

5. The apparatus of claim 4, wherein the first enable signal is generated by buffering the pull-up data signal using a buffer circuit and wherein the second, third, and fourth enable signals are generated by logic synthesis of a respective bit signal of the calibration code signal and the pull-up data signal by a respective gate circuit.

6. The apparatus of claim 2, further comprising:

a third wiring pattern coupled to the external data terminal; and

a fourth wiring pattern coupled to the supply potential,

wherein the plurality of transistors is arranged between the third and fourth wiring patterns in a first direction,

wherein the first transistor is arranged on a first end between the third and fourth wiring patterns along the first direction, and

wherein the second transistor is arranged on a second end opposite the first end between the third and fourth wiring patterns along the first direction.

7. The apparatus of claim 2, further comprising:

a first diffusion region adjacent to the first transistor on the first end away from the second transistor;

a second diffusion region adjacent to the second transistor on the second end away from the first transistor;

a fifth wiring pattern overlapping with the first diffusion region; and

a sixth wiring pattern overlapping with the second diffusion region,

wherein the first and the second diffusion regions extend in a second direction opposite the first direction, and

wherein a fifth wiring pattern overlaps with the first diffusion region and a sixth wiring pattern overlaps with the second diffusion region.

8. The apparatus of claim 6, wherein the first and second wiring patterns comprise a first material and the third and fourth wiring patterns comprise a second material having a lower resistance than the first material.

9. The apparatus of claim 1, further comprising a sub-unit of a second plurality of transistors coupled to the main driver, wherein each of the second plurality of transistors is a same size.

10. A method comprising:

activating a first transistor of a plurality of transistors connected in parallel in response to an enable signal supplied to a first gate electrode of the first transistor;

outputting a ground potential to remaining gate electrodes of other transistors of the plurality of transistors;

activating a second transistor of the plurality of the plurality of transistors connected in parallel in response to the enable signal supplied to a second gate electrode of the second transistor; and

outputting the ground potential to remaining gate electrodes of remaining transistors of the plurality of transistors except the activated first and second transistors,

wherein

the first transistor comprises a first wiring pattern and a second wiring pattern and the second transistor comprises a third wiring pattern and fourth wiring pattern,

the first and second wiring patterns are greater in width than the third and fourth wiring patterns, and

the second gate electrode is connected to a data terminal by a metal connection.

11. The method of claim 10, further comprising:

outputting read data to a fifth wiring pattern;

supplying a power potential to a drain regions of the plurality of transistors via a sixth wiring pattern, wherein the first, second, third, and fourth wiring patterns cross the fifth ands sixth wiring patterns.

12. The method of claim 10, wherein

a first source of the first transistor is connected to the first wiring pattern and a first drain of the first transistor is connected to the second wiring pattern.

13. The method of claim 10, further comprising:

buffering a pull-up data signal; and

generating the enable signal based on the pull-up data signal.

14. An apparatus comprising:

first, second, and third transistors arranged in a first direction, the second transistor arranged between the first and third transistor, and the first, second and third transistors are connected in parallel; and

first, second, third, fourth, fifth, and sixth wiring patterns extending in a second direction different than the first direction,

wherein the first transistor comprises the first wiring pattern and the second wiring pattern,

wherein the second transistor comprises the third wiring pattern and the fourth wiring pattern,

wherein the third transistor comprises the fifth wiring pattern and the sixth wiring pattern,

wherein the first, second, third, fourth, fifth, and sixth wiring patterns are arranged in order in the first direction,

wherein the first and second wiring patterns have a greater width than the third and fourth wiring patterns, and

wherein the fifth and sixth wiring patterns have a greater width than the third and fourth wiring patterns.

15. The apparatus of claim 14, further comprising:

a power supply wiring pattern extending in the first direction.

16. The apparatus of claim 15, wherein the first, third, and fifth wiring patterns are connected to one of source/drain regions of the first, second, and third transistors, respectively, and wherein the second, fourth, and sixth wiring patterns are connected between the power supply wiring pattern and other of source/drain regions of the first, second, and third transistors, respectively.

17. The apparatus of claim 16, wherein the other of source/drain regions of the first transistor and the one of source/drain regions of the second transistor are arranged adjacent to each other with a first space in between, and wherein the other of source/drain regions of the second transistor and the one of source/drain regions of the third transistor are arranged adjacent to each other with a second space in between.

18. The apparatus of claim 17, wherein the second space is narrower than the first space.

19. The apparatus of claim 14,

wherein the second and third wiring patterns are arranged adjacent to each other with a third space between them,

wherein the fourth and fifth wiring patterns are arranged adjacent to each other with a fourth space between them, and

wherein the third space is narrower than the fourth space.