JPH11317423A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, in which the connection of a package substrate with a semiconductor chip is realized with high reliability and at low cost. SOLUTION: In a semiconductor device in which a semiconductor chip is mounted on a tape carrier, a tape carrier consists of an insulating film 11, conductive pattern 12 formed on the resin film 11, and a metal bump 18 formed on the conductive pattern 12. This conductive chip 13 is provided with plural electrode pads 15 at the peripheral part of the tape carrier side face, and a spacer 14 made of synthetic resin is provided in a region surrounded by the electrode pads 15. Each electrode pad 15 is connected with a metal bump 16 formed on the conductive pattern 12, and the spacer 14 is formed thinner than the height of the metal bump 16, so that it does not adhere to the tape carrier.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a semiconductor chip mounted on a tape carrier.

[0002]

2. Description of the Related Art In a small semiconductor package structure having a size substantially equal to that of a semiconductor chip, that is, a so-called chip scale package (CSP) structure, it is desired to realize high reliability and low cost connection between a circuit board and a semiconductor chip. It is. FIG. 5 shows a conventional CSP structure.

As shown in FIG. 5, in a conventional CSP structure, a semiconductor bare chip 3 is mounted on a circuit board 1 via a tape carrier 2. The connection between the circuit board 1 and the tape carrier 2 is made by soldering via solder balls 4.

In such a conventional CSP structure, the coefficient of linear expansion of the bare chip 3 (silicon) is 3.5 ppm, and the coefficient of linear expansion of a circuit board as a resin substrate is 15 to 18 ppm. If stress acts directly on the solder ball connection due to the difference between the two coefficients of linear expansion, there is a problem that the solder ball connection is broken.

In order to solve such a problem, it is conceivable to provide a stress relief mechanism for preventing the stress from directly acting on the solder ball connection portion in the tape carrier 2 or the connection structure between the tape carrier 2 and the bare chip 3.

That is, as shown in FIG. 6, there is a method in which a thermosetting resin 5 is filled in a gap in a connection structure between the circuit board 1 and the tape carrier 2 and cured. According to this method, the stress applied to the solder ball connection portion is dispersed, and the solder ball 4
It is possible to improve the life until fatigue fracture of the steel. However, in this method, the process of filling and curing the resin 5 is complicated, and the mounting cost increases,
Not an appropriate method.

FIG. 7 shows a structure in which the connection structure between the tape carrier 2 and the bare chip 3 is provided with a stress relaxation structure.
Has been proposed. In this structure, the connection between the tape carrier 2 and the bare chip 3 is performed by a gull-wing-shaped conductor lead 6, and the tape carrier 2 and the bare chip 3 are bonded with an elastomer resin 7. According to such a structure, the tape carrier 2 is deformed with respect to the bare chip 3, whereby the stress applied to the solder balls 4 can be reduced.

However, in the structure shown in FIG. 7, it is necessary to form fine conductor leads 6 on the tape carrier 2 and cut, form, and bond them one by one. Time is required, and the cost increases. Further, since the elastomer resin 7 is softened at a high temperature, the adhesive force with the bare chip 3 is reduced, the tape carrier 2 is peeled off, or water invades the interface between the bare chip 3 and the tape carrier 2 to form a package. A problem arises in the reliability of

[0009]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and has as its object to provide a semiconductor device which realizes high reliability and low cost connection between a package substrate and a semiconductor chip. Aim.

[0010]

In order to solve the above-mentioned problems, the present invention (claim 1) is a semiconductor device comprising a semiconductor chip mounted on a tape carrier, wherein the tape carrier comprises an insulating film. And a conductive pattern formed on the resin film and a metal bump formed on the conductive pattern, and the semiconductor chip has a plurality of electrode pads on a peripheral portion of a surface facing the tape carrier side. In addition, a spacer made of a synthetic resin is provided in a region surrounded by the electrode pads, the electrode pads are joined to metal bumps formed on the conductor pattern, and a gap between the semiconductor chip and the tape carrier is formed. Resin is filled, the spacer is thinner than the height of the metal bump, and is not bonded to the tape carrier To provide a semiconductor device which is characterized and.

According to the present invention (claim 2), in the above-described semiconductor device (claim 1), the conductor pattern has a terminal for connecting to a circuit board, and the insulating pattern below the terminal is provided. A hole is provided in the film, a bonding electrode is formed in the hole, and through the bonding electrode,
The conductor pattern is connected to a circuit board.

The present invention (claim 3) is characterized in that, in the above-mentioned semiconductor device (claim 1), the tape carrier has an air hole. According to a fourth aspect of the present invention, in the above-described semiconductor device (the first aspect), the tape carrier has a larger outer size than the semiconductor chip.
The bonding electrode is located inside or outside a region surrounded by the electrode pad.

The present invention (Claim 5) is characterized in that, in the above-mentioned semiconductor device (Claim 1), the electrode pad is made of aluminum, and a metal layer alloying with a metal bump is formed on the surface. I do.

The present invention (Claim 6) is characterized in that, in the above-described semiconductor device (Claim 1), at least a tip of the metal bump is made of Au, Sn or a Sn alloy.

The present invention (claim 7) is characterized in that, in the above-mentioned semiconductor device (claim 1), the surface of the bonding electrode is plated with Au or a Sn alloy. According to the present invention (claim 8), in the above-described semiconductor device (claim 1), deformation of the insulating film is prevented in a region outside the semiconductor chip on the semiconductor chip mounting side surface of the tape carrier. A stiffener is provided.

According to the present invention (claim 9), in the above-mentioned semiconductor device (claim 1), the spacer is formed by forming an insulating film on the surface of a semiconductor wafer and being surrounded by the electrode pads of the semiconductor chip by photolithography. The semiconductor chip is formed by patterning the insulating film so as to leave a predetermined portion of the region, and then the semiconductor chip is cut out.

In the semiconductor device of the present invention configured as described above, a spacer made of a synthetic resin is provided in a region surrounded by the electrode pads of the semiconductor chip, and the spacer and the tape carrier are adhered. Since the semiconductor chip and the tape carrier are not bonded to each other, the thermal stress due to the difference in linear expansion coefficient between the semiconductor chip and the circuit board can be easily reduced. That is, the stress due to the thermal expansion of the circuit board is reduced by the deformation of the tape carrier, and as a result, the connection between the circuit board and the semiconductor chip can be realized with high reliability and low cost.

Since the spacer also plays a role of preventing the filling resin from invading, the spacer
Adhesion between the semiconductor chip and the tape carrier by the filling resin can be prevented. Further, by forming the spacer from a thermosetting resin, it is possible to obtain high reliability against high temperatures and thermal cycles.

Furthermore, since metal bumps, for example, solder bumps are formed on the side of the conductor pattern constituting the tape carrier, a metal layer alloying with the metal bumps must be formed on the surface of the electrode pad of the semiconductor chip. Thus, a large number of semiconductor chips can be mounted collectively by a series of steps such as alignment, mounting of semiconductor chips, and reflow heating. The tape carriers on which the semiconductor chips are mounted are thereafter cut out individually. Even when the semiconductor chip is mounted by using a heating tool, since the collective connection is possible, the mounting process can be reduced as compared with the conventional example.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device having a CSP structure according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a part of a semiconductor device having a CSP structure according to an embodiment of the present invention. In FIG.
A thermosetting resin (for example, epoxy resin) in which a tape carrier formed by forming a copper pattern 12 on an insulating film 11 and a bare chip 13 are attached to the bare chip 13 side
Are connected in a state where a spacer 14 made of is interposed therebetween. An electrode pad 15 made of aluminum or the like is arranged around the circuit surface of the bare chip 13, and the electrode pad 15 and the A
A metal bump 16 made of u, Sn, Sn alloy or the like is joined. In addition, on the surface of the electrode pad 15, a metal layer forming an alloy layer with the metal bump 16, for example, Ni / Au
A plating layer is formed, whereby the electrode pad 1 is formed.
5 and the metal bump 16 are joined.

The spacer 14 is attached to a region surrounded by the electrode pad 15 of the bare chip 13, and has a thickness smaller than that of the metal bump 16. The gap between the tape carrier and the bare chip 13 is filled with a thermosetting resin (for example, epoxy resin) 17 and cured. The joining portion between the tape carrier and the bare chip 13 is reinforced by the thermosetting resin 17.

Since the space between the spacer 14 and the tape carrier is not bonded, the tape carrier itself can be deformed, so that the heat applied to the bonding electrode due to the difference in linear expansion coefficient between the bare chip 13 and the tape carrier. Mechanical stress can be reduced.

FIG. 8 is a perspective view of the tape carrier. The upper part of FIG. 8 shows a view from the front side, and the lower part shows a view from the back side. In FIG. 8, the conductor pattern 12 has terminals 41 at locations electrically connected to the conductors of the circuit board in the vertical direction.
A hole smaller in diameter than the terminal 41 is formed in the insulating film 11 below. The solder formed in this hole forms the bonding electrode 18. As shown in FIG. 1, a solder ball 19 is formed on the bonding electrode 18, and is connected to a conductor of a circuit board via the solder ball 19.

The insulating film 11 and the copper pattern 12 constituting the tape carrier have holes 2 for air release.
0a, 209b, the air existing between the spacer 14 and the tape carrier expands due to heat,
This prevents the tape carrier from being destroyed.

With the connection structure between the tape carrier and the bare chip 13 as described above, a semiconductor device (package)
Is obtained. This is mounted on the circuit board via the bonding electrode 18.

The joining electrode 18 can be formed by solder balls or by plating with copper, nickel, solder or the like, and the surface thereof can be plated with Au or Sn alloy.

Further, a stiffener for preventing the insulating film from being deformed can be bonded to a region outside the bare chip on the surface of the tape carrier on which the bare chip is mounted.

As described above, in the semiconductor package according to the present embodiment, a thermosetting resin (for example, an epoxy resin) is formed in a region surrounded by the electrode pads 15 of the bare chip 13.
Since the spacer 14 is bonded and the spacer 14 is not bonded to the tape carrier, the thermal stress applied to the bonding electrode due to the difference in linear expansion coefficient between the bare chip 13 and the circuit board can be easily reduced. I was able to relax. The stress due to the thermal expansion of the circuit board was alleviated by the deformation of the tape carrier. As a result, the connection between the circuit board and the bare chip 13 could be realized with high reliability and low cost.

Next, a method for manufacturing the connection structure between the tape carrier and the bare chip 13 described above will be described.
2 to 4 are cross-sectional views showing a manufacturing process of the semiconductor device having the CSP structure shown in FIG. 1 in the order of steps.

First, as shown in FIG.
A material having a polyimide layer 22 having a thickness of 40 μm on one side of a copper foil 21 having a thickness of μm is prepared. In a portion where a bonding electrode is to be formed, a carbon dioxide laser is used to reach
A hole 23 having a diameter of μm was formed in the polyimide layer 22. The carbon adhering to the hole 23 and its periphery at the time of drilling by the carbon dioxide laser was mechanically removed by blasting.

Next, as shown in FIG. 2B, a negative photosensitive dry film 2 having a thickness of 25 μm was formed on the copper foil surface.
After laminating No. 4, the photosensitive dry film 24 was exposed through a mask 25 in which the conductor circuit had a positive pattern. An ultra-high pressure mercury lamp was used as an exposure light source, and the irradiation amount was 80 mJ / cm ² .

Next, as shown in FIG. 2C, the photosensitive dry film 24 is immersed in 1 wt% Na ₂ CO _{3 at a} liquid temperature of 30 ° C.
Development was performed using an aqueous solution to form a pattern plating resist.

Then, as shown in FIG. 2D, a solder having a composition of tin 9 lead 1 was electroplated to form solder patterns 26a and 26b having a thickness of 4 μm. A for plating bath
An S513 bath (trade name: manufactured by Ishihara Pharmaceutical Co., Ltd.) was used.

Then, as shown in FIG. 3A, the photosensitive dry film 24 was peeled off. As the stripping solution, a 3% NaOH aqueous solution at a liquid temperature of 45 ° C. was used. Then, FIG.
As shown in (b), a thickness of 50 mm is formed on the solder pattern 26a.
A negative photosensitive dry film 27 of μm was laminated. The photosensitive dry film 27 was exposed to light through a mask 28 in which the metal bumps had a positive pattern in order to form metal bumps 29a for connection to semiconductor electrode pads by electroplating. An ultra-high pressure mercury lamp was used as an exposure light source, and the irradiation amount was 160 mJ / cm ² .

Thereafter, as shown in FIG. 3C, the photosensitive dry film 27 was developed. As a developing solution, a 1 wt% aqueous solution of Na ₂ CO _{3 at} a liquid temperature of 30 ° C. was used. Next, as shown in FIG. 3D, a solder having a composition of tin 6 lead 4 was electroplated to form a solder pad 29a having a thickness of 50 μm and a solder pad 29b having a thickness of 40 μm.

Thereafter, as shown in FIG. 4A, the photosensitive dry film 27 was peeled off. As the stripping solution, a 3% NaOH aqueous solution at a liquid temperature of 45 ° C. was used. And FIG.
As shown in (b), the copper foil 21 was alkali-etched using the solder pattern 26a as an etching resist to obtain a desired tape carrier. At this time, the copper foil 21
The hole 20b for air release was formed in this.

Then, as shown in FIG. 4C, the separately prepared bare chip 30 was mounted on the tape carrier described above and shown in FIG. 4B. The bare chip 30 has an aluminum pad 31 in a peripheral portion, and the surface of the aluminum pad 31 is subjected to an electroless Ni / Au plating 32. A spacer 33 made of a thermosetting resin, for example, an epoxy resin and having a thickness of 40 μm is attached to a region surrounded by the aluminum pad 31.

A gap between the bare chip 30 and the tape carrier was filled with a thermosetting resin, for example, an epoxy resin 34, to obtain a connection structure between the tape carrier and the bare chip 30. After that, solder balls (not shown) are formed on the solder pads, and holes 2 for air release are formed in the polyimide layer 22.
0a was formed, and a semiconductor package having a CSP structure was obtained.

In the above manufacturing process, a tape carrier having solder bumps 29a formed on the copper pattern side is used, and Ni, which is alloyed with the solder bumps, is formed on the surface of the aluminum pad.
The bare chips forming / Au can be mounted collectively by a series of steps such as positioning / mounting of bare chips / reflow heating. The tape carrier on which the bare chips are mounted is thereafter cut out individually.

[0040]

As described in detail above, the semiconductor device of the present invention includes a spacer made of a synthetic resin in a region surrounded by the electrode pads of the semiconductor chip.
Since the spacer and the tape carrier are not bonded, thermal stress due to a difference in linear expansion coefficient between the semiconductor chip and the tape carrier can be easily reduced.
Therefore, when this semiconductor device is mounted on a circuit board, as a result, the thermal stress due to the difference in linear expansion coefficient between the semiconductor chip and the circuit board can be easily reduced, and the connection between the circuit board and the semiconductor chip can be reduced. , High reliability and low cost.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a part of a semiconductor device having a CSP structure according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device having the CSP structure shown in FIG. 1 in the order of steps;

FIG. 3 is a sectional view showing a manufacturing process of the semiconductor device having the CSP structure shown in FIG. 1 in the order of steps;

FIG. 4 is a sectional view showing a manufacturing process of the semiconductor device having the CSP structure shown in FIG. 1 in the order of steps;

FIG. 5 is a sectional view showing a conventional semiconductor device having a CSP structure.

FIG. 6 is a cross-sectional view showing a conventional semiconductor device having a CSP structure.

FIG. 7 is a cross-sectional view showing a conventional semiconductor device having a CSP structure.

FIG. 8 is a perspective view showing a tape carrier used in the semiconductor device shown in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Circuit board 2 ... Tape carrier 3, 13, 32 ... Bare chip 4, 19 ... Solder ball 5, 17, 35 ... Filling resin 6 ... Conductor lead 7 ... Elastomer resin 11, 22, 23, 27 ... Insulating film 12 ... Copper Pattern 14, 34 Spacer 15 Electrode pad 18 Joint electrode 20a, 20b Air vent hole 24a, 24b, 24c Protective film 25a, 25b, 28 Mask 26 Solder pattern 29 Solder bump 30 Solder pad 41 Terminal

Claims (9)

[Claims] 1. A semiconductor device comprising a semiconductor chip mounted on a tape carrier, wherein the tape carrier comprises:
An insulating film, a conductor pattern formed on the resin film, and metal bumps formed on the conductor pattern, wherein the semiconductor chip has a plurality of electrodes on a peripheral portion of a surface facing the tape carrier side. A pad is provided, and a spacer made of a synthetic resin is provided in a region surrounded by these electrode pads.The electrode pad is bonded to a metal bump formed on the conductor pattern, and is provided in a gap between the semiconductor chip and the tape carrier. Wherein the spacer is thinner than the height of the metal bump and is not adhered to the tape carrier. 2. The conductive pattern has a terminal for connecting to a circuit board, a hole is provided in the insulating film below the terminal, and a bonding electrode is formed in the hole. 2. The semiconductor device according to claim 1, wherein the conductor pattern and the circuit board are connected via the bonding electrode. 3. The semiconductor device according to claim 1, wherein the tape carrier has a through hole for venting air. 4. The tape carrier according to claim 1, wherein the tape carrier has a larger outer size than the semiconductor chip, and the bonding electrode is located inside or outside a region surrounded by the electrode pads. 13. The semiconductor device according to claim 1. 5. The semiconductor device according to claim 1, wherein the electrode pad is made of aluminum, and a metal layer alloying with a metal bump is formed on a surface of the electrode pad. 6. The method according to claim 6, wherein at least the tip of the metal bump is A
2. The semiconductor device according to claim 1, comprising u, Sn, or a Sn alloy. 7. The semiconductor device according to claim 1, wherein a surface of said bonding electrode is plated with Au or a Sn alloy. 8. A stiffener for preventing deformation of the insulating film is provided in a region outside the semiconductor chip on a surface of the tape carrier on the semiconductor chip mounting side. 2. The semiconductor device according to 1. 9. The spacer is formed by forming an insulating film on a semiconductor wafer surface and patterning the insulating film by photolithography so as to leave a predetermined portion of a region surrounded by the electrode pads of the semiconductor chip. 2. The semiconductor device according to claim 1, wherein the semiconductor chip is formed and then the semiconductor chip is cut out.