JPH11312803A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a semiconductor device on which a silicide layer of low sheet resistance can be formed on the surface of a gate electrode. SOLUTION: A polycrystalline silicon film 4 is formed on a semiconductor substrate 1 via a gate insulating film 3. boron ions are introduced into the polycrystalline silicon film 4. Gate electrodes 4a and 4b are formed by patterning the polycrystalline silicon film 4 and the gate insulating film 3. N-type impurity ions are introduced into the gate electrode 4a, and the gate electrode is formed into an n-type. After a sidewall has been formed on the sidewall of the gate electrodes 4a and 4b, and the natural oxide film on the surface of the gate electrodes 4a and 4b is removed by treating the surface of the gate electrodes 4a and 4b with a chemical solution. After the formation of a metal film on the semiconductor substrate 1 n a state in which the gate electrode is covered, the metal film and the gate electrodes 4a and 4b are made to react with each other, and a silicide layer 10 is formed on the surface layer of the gate electrodes 4a and 4b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a silicide layer on a surface layer of a gate electrode.

[0002]

2. Description of the Related Art When the element structure is miniaturized in accordance with high integration and high functionality of a semiconductor device, in a MOS transistor, a gate electrode becomes thinner and a source / drain diffusion layer becomes shallower. Rises. Therefore, in a semiconductor device in which the element structure has been miniaturized, the increase in the sheet resistance is suppressed by siliciding the surface layers of the gate electrode and the source / drain diffusion layers.

In order to manufacture such a semiconductor device, first, as shown in FIG.
A polycrystalline silicon film 53 is formed thereover via a gate insulating film 52. Next, as shown in FIG. 5B, the polycrystalline silicon film 53 and the gate insulating film 52 are patterned to form a gate electrode 53a. After that, the gate electrode 53a
Is formed on the side wall of the semiconductor substrate 51 and impurities are introduced into the exposed surface layer of the semiconductor substrate 51 and the gate electrode 53a. As a result, the source / drain diffusion layer 55 is formed on the surface layer of the semiconductor substrate 51, and the gate electrode 53 is made conductive. Next, as shown in FIG. 5C, a silicide layer 56 is formed on the gate electrode 53a and the surface layer of the semiconductor substrate 51. In this case, first, a chemical solution treatment is performed as a pre-treatment to remove the natural oxide film on the surface of the gate electrode 53a and the semiconductor substrate 51. Thereafter, a metal film is formed on the semiconductor substrate 51 so as to cover the gate electrode 53a, and the metal film reacts with the gate electrode 53a and the semiconductor substrate 51 to form a silicide layer 56 on these surface layers.
To form Thereafter, as shown in FIG. 5D, an interlayer insulating film 57, a connection hole 58, and an upper wiring 59 are formed to complete the semiconductor device.

[0004]

However, the gate portion of the semiconductor device obtained by the above method has a structure in which a gate insulating film, a polycrystalline silicon film, and a silicide layer are sequentially provided on a semiconductor substrate. Component and a capacitor component. As a result, when the MOS transistor is in the ON state, the polycrystalline silicon portion of the gate electrode is depleted, the capacitance of the gate electrode increases, which is equivalent to an increase in the thickness of the gate insulating film. This causes a reduction in channel current.

Therefore, when a silicide layer is formed on the surface layer of the gate electrode, it is necessary to prevent a decrease in channel current due to the depletion by increasing the impurity concentration in the polycrystalline silicon film. However, increasing the impurity concentration in the polycrystalline silicon film becomes a factor of causing the surface of the polycrystalline silicon film to be rough when introducing impurities. As a result, the thickness of the silicide layer formed on the surface layer of the gate electrode becomes uneven, and it becomes impossible to suppress an increase in sheet resistance. In particular, in a gate electrode into which an n-type impurity is introduced, a silicide layer capable of suppressing an increase in sheet resistance under the above-described depletion-suppressing conditions is formed even when an impurity to be introduced or a metal to be silicided is selected. Can not do.

In addition to the above cases, when the natural oxide film on the surface of the gate electrode removed by the chemical treatment is non-uniform, or when the natural oxide film is removed by etching, , The etching proceeds in a large amount at the crystal grain boundary of polycrystalline silicon, and the surface of the gate electrode becomes rough. The silicide layer formed on the surface layer of such a gate electrode has a non-uniform film thickness and a low effect of suppressing sheet resistance.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing the sheet resistance of a gate electrode.

[0008]

According to the present invention, there is provided a method of manufacturing a semiconductor device in which a silicide layer is provided on a surface layer of a gate electrode. It is characterized by performing. First,
In a first step, a polycrystalline silicon film is formed on a semiconductor substrate via a gate insulating film. In a second step, boron ions or boron-containing compound ions are introduced into the polycrystalline silicon film. Then, in a third step, a gate electrode made of a polycrystalline silicon film is patterned, and in a fourth step, n-type impurity ions are introduced into the gate electrode to make it n-type. Next, in a fifth step, side walls are formed on the side walls of the gate electrode, and activation is performed by heat treatment. After removing the natural oxide film on the surface of the gate electrode by performing a chemical treatment in the sixth step, in the seventh step, a metal film is formed on the semiconductor substrate in a state of covering the gate electrode, and the reaction is performed. A silicide layer is formed on the surface layer.

According to the manufacturing method of the first aspect, by introducing boron as an impurity into the polycrystalline silicon film, the crystal grain size of the polycrystalline silicon film is reduced. For this reason, when performing a chemical treatment with the gate electrode obtained by patterning the polycrystalline silicon film being made n-type, the chemical etching at the interface between the crystal grains does not easily progress in the depth direction of the gate electrode, and the Surface roughness can be suppressed. Therefore, the thickness of the silicide layer formed on the surface layer of the n-type gate electrode can be made uniform.

According to a second aspect of the present invention, there is provided a manufacturing method according to the first aspect,
This is a method in which n-type impurity ions are introduced only into the region where the gate electrode of the type is to be formed. According to this manufacturing method, the gate electrode in a region other than the region where the n-type gate electrode is formed becomes p-type, and a semiconductor device including the n-type gate electrode and the p-type gate electrode is obtained.

Further, the manufacturing method according to claim 4 is characterized in that:
After forming the gate insulating film on the semiconductor substrate in the process, the second
The process is characterized in that a polycrystalline silicon thin film is formed by laminating the polycrystalline silicon thin film on the gate insulating film by repeatedly forming a polycrystalline silicon thin film a plurality of times. Thereafter, in a third step, a gate electrode made of a polycrystalline silicon film is patterned, and in a fourth step, impurity ions are introduced into the gate electrode. To do.

In the manufacturing method according to the fourth aspect, the gate electrode obtained by patterning the polycrystalline silicon film is
A polycrystalline silicon thin film is laminated. Therefore, the polycrystalline silicon film forming the gate electrode has a small crystal grain size in the depth direction. Therefore, when removing the native oxide film of the gate electrode obtained by patterning this polycrystalline silicon film, the chemical solution etching at the interface of the crystal grains does not easily progress in the depth direction of the gate electrode,
The surface roughness of the gate electrode can be suppressed. As a result, the thickness of the silicide layer formed on the surface layer of the gate electrode can be made uniform.

According to a fifth aspect of the present invention, in the second step of the fourth aspect, an oxide thin film is formed on the surface of the polycrystalline silicon thin film during the formation of the polycrystalline silicon thin film. How to In this manufacturing method, the polycrystalline silicon thin films are separated by the oxide thin film, and the progress of the chemical etching in the depth direction can be reliably prevented.

Further, the manufacturing method according to claim 7 is characterized in that:
After forming the gate insulating film on the semiconductor substrate in the process, the second
In the step, an amorphous silicon film is formed on the gate insulating film, and in the third step, the amorphous silicon film and the gate insulating film are patterned to form a gate electrode. Thereafter, in a fourth step, impurity ions are implanted into the gate electrode.
Perform in the same manner as described.

In the manufacturing method according to the seventh aspect, since the gate electrode is obtained by patterning the amorphous silicon film, the oxidation proceeds uniformly on the surface of the gate electrode. Therefore, a natural oxide film having a uniform thickness is formed on the surface of the gate electrode, and the gate electrode obtained by removing the natural oxide film by the chemical treatment has a reduced surface roughness. As a result, the thickness of the silicide layer formed on the surface layer of the gate electrode can be made uniform.

Further, in the manufacturing method according to the first, fourth and seventh aspects, in each of the fourth steps, a silicon nitride film is formed so as to cover the gate electrode, and the gate electrode is formed on the gate electrode via the silicon nitride film. Impurity ions may be introduced. In such a case, since impurity ions are introduced into the gate electrode through the silicon nitride film, the gate electrode is prevented from being roughened due to knock-on of oxygen atoms.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment in which the method of manufacturing a semiconductor device according to the present invention is applied to a method of manufacturing a CMOS in which an n-channel MOS transistor and a p-channel MOS transistor are provided on the same semiconductor substrate. This will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional process view showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention, to which the present invention is applied. A first embodiment of the invention will be described.

First, as shown in FIG. 1A, after an element isolation region 2 is formed on the surface side of a semiconductor substrate 1 made of silicon, a gate insulating film 3 made of silicon oxide is formed on the surface side of the semiconductor substrate 1. Form. Thereafter, for example, CVD (Chemical Vapor) is formed on the element isolation region 2 and the gate insulating film 3.
The polycrystalline silicon film 4 is formed by a Deposition method. The thickness of the polycrystalline silicon film 4 is 200 nm, and an example of conditions for forming the polycrystalline silicon film 4 will be described below. Silane (SiH ₄ ) = 100 sccm, helium (H ₂ ) = 400 sccm, nitrogen (N ₂ ) = 200 sccm, deposition atmosphere pressure: 70 Pa, semiconductor substrate temperature: 610 ° C. Here, sccm is standard cubic centimeter / minutes
It is assumed that

Thereafter, boron ions (B ⁺ ) or compound ions containing boron (for example, boron difluoride ion,
BF ₂ ⁺ ). Here, as an example, B ⁺
The implantation energy is 5 keV and the dose is about 10 ¹⁵ / cm ² .

Next, as shown in FIG. 1B, the polycrystalline silicon film 4 and the gate insulating film 3 are patterned to form gate electrodes 4a and 4b. This patterning is performed by dry etching using a resist pattern (not shown) as a mask, and an example of the dry etching conditions will be described below. Etching gas and flow rate: chlorine (Cl ₂ ) = 75 sccm; oxygen (O ₂ ) = ₂ sccm; hydrogen sulfide (HBr) = 120 sccm; etching atmosphere pressure: 1 Pa; RF power: 60 W; After completion of the dry etching, the resist pattern is removed.

After the above, impurities for forming the LDD diffusion layers 5 and 6 are introduced into the surface layer of the semiconductor substrate 1. Here, a p-channel MOS transistor is formed.
Using a resist pattern (not shown) covering mold region 1b and gate electrode 4a as a mask, an impurity for forming n-type LDD diffusion layer 5 is introduced into n-type region 1a where an n-channel MOS transistor is to be formed. . As an example, arsenic ions (As ⁺ ) are introduced at an implantation energy of 30 keV and at a dose of about 10 ¹³ / cm ² . On the other hand, a resist pattern covering the n-type region 1a (not shown)
And the gate electrode 4b as a mask, an impurity is introduced to form the p-type LDD diffusion layer 6 in the p-type region 1b. As an example, B ⁺ is introduced at an implantation energy of 30 keV and at a dose of about 10 ¹³ / cm ² . The respective impurities are also introduced into the surface layer of the semiconductor substrate 1 and the gate electrodes 4a and 4b serving as masks. After completion of each ion implantation, each of the resist patterns using the mask is removed.

Next, as shown in FIG. 1C, an insulating sidewall 7 is formed on the side walls of the gate electrodes 4a and 4b and the gate insulating film 3. In this case, first, a silicon oxide film (not shown) is formed to a thickness of about 10 nm on the semiconductor substrate 1 so as to cover the gate electrodes 4a and 4b and the gate insulating film 3, and then a silicon nitride film (not shown) ) Is formed to a thickness of about 30 nm. The following is an example of conditions for forming the silicon oxide film and the silicon nitride film by the CVD method. -Silicon oxide film deposition conditions, deposition gas and flow rate: TEOS (tetraethoxy silane) = 50 sccm, deposition atmosphere pressure: 40 Pa, semiconductor substrate temperature: 720 ° C. Film formation conditions of the silicon nitride film, the film forming gas and flow rate: 2 dichlorosilane _{(SiH 2 Cl 2) = 0.05slm} ,; ammonia (NH ₃₎ = 0.20slm,; nitrogen (N ₂₎ = 0.20slm , Film forming atmosphere pressure; 70 Pa; semiconductor substrate temperature; 760 ° C.

After the above, the entire surface of the silicon nitride film is etched back from the front side, leaving the silicon oxide film only on the side walls of the gate electrodes 4a, 4b and the gate oxide film 3, and this is used as a side wall 7. . An example of the above-described overall etch-back condition is shown below. Etching gas: octafluorocyclobutane (C ₄ F ₈ ) = 50 sccm RF power: 1200 W, etching atmosphere pressure: 2 Pa

Next, source / drain diffusion layers 8 and 9 are formed on the surface layer of the semiconductor substrate 1, and impurities for imparting conductivity to the gate electrodes 4a and 4b are introduced by ion implantation. Here, a resist pattern (not shown) covering p-type region 1b, gate electrode 4a and sidewall 7
Is used as a mask to introduce an n-type impurity into the surface layer of the semiconductor substrate 1 in the n-type region 1a and the gate electrode 4a. As an example, As ⁺ is implanted at a dose of 5 × 1 with an implantation energy of 40 keV.
It is introduced at a dose of about 0 ¹⁵ pieces / cm ² . At this time, the n-type source / drain diffusion layers 8 are formed on the surface layer of the semiconductor substrate 1.
Is formed, and the p-type impurity (boron) previously introduced into the gate electrode 4a is canceled out, so that the gate electrode 4a
N-type impurity is introduced in a sufficient amount to make n-type.

On the other hand, a resist pattern (not shown) covering n-type region 1a, gate electrode 4b and side wall 7
Is used as a mask to introduce a p-type impurity into the surface layer of the semiconductor substrate 1 in the p-type region 1b and the gate electrode 4b. As an example, BF ₂ ⁺ is implanted at 3 × with an implantation energy of 20 keV.
It is introduced at a dose of about 10 ¹⁵ / cm ² . As a result, a p-type source / drain 9 is formed, and
The gate electrode 1b becomes p-type. After completion of each ion implantation, each resist pattern is removed.

After the above, a short-time heat treatment at a temperature of about 1000 ° C. is performed, so that the semiconductor substrate 1 and the gate electrodes 4 a and 4
The impurity introduced into b is activated.

Next, using a buffered hydrofluoric acid (BHF) or a dilute hydrofluoric acid (DHF) as an etching solution,
Then, the native oxide film on the exposed surfaces of the gate electrodes 4a and 4b is removed, and silicon is exposed on these surfaces. On this occasion,
When BHF is used, for example, 0.1 wt%
Hydrofluoric acid (HF) at a concentration of 5.0 wt%, 5 wt% to 4 wt%
A mixture of 0 wt% ammonium fluoride (NH ₄ F) is used. In the case of using DHF, one having an HF concentration of 0.5 wt% is used as an example.

Thereafter, as shown in FIG. 1D, a silicide layer 10 is formed on the exposed surfaces of the semiconductor substrate 1 and the gate electrodes 4a and 4b. At this time, first, the gate electrode 4
A metal film (not shown) is formed on the semiconductor substrate 1 so as to cover the a, 4b and the side wall 7. This metal film is, for example, a titanium (Ti) film, a cobalt (C) film.
o) A Ti film is laminated on a film and a Co film (Ti / C
o) A (TiN / Co) film in which a titanium nitride (TiN) film is laminated on a film or a Co film.

The following is an example of conditions for forming these metal films by the sputtering method. -Co film formation conditions, sputtering gas and flow rate; argon (Ar) = 100 sccm, sputtering atmosphere pressure: 0.47 Pa, power: 1 kW, film thickness: 20 nm. -Ti film formation conditions, sputtering gas and flow rate; argon (Ar) = 100 sccm, sputtering atmosphere pressure: 0.47 Pa, power: 0.5 kW, film thickness: 30 nm. After forming a Co film with a thickness of 10 nm under the conditions for forming the Ti / Co film and the conditions for forming the Co film, forming a T film with a thickness of 6 nm under the conditions for forming the Ti film.
An i film is formed continuously. After forming a Co film with a thickness of 10 nm under the conditions for forming the TiN / Co film and the conditions for forming the Co film, a TiN film with a thickness of 20 nm was formed under the following formation conditions.
A film is formed continuously. Argon (Ar) = 100 sccm, sputtering atmosphere pressure: 0.47 Pa, power: 1 kW.

The metal film may be made of, for example, nickel (Ni), platinum (Pt), palladium (Pd), hafnium (Hf), zirconium (Z
r), tungsten (W), molybdenum (Mo), ruthenium (Ru), or a film formed by laminating these.

Next, by rapid thermal processing (RTA), 1
A second heat treatment is performed, and the metal film and the gate electrodes 4a, 4a
b and the semiconductor substrate 1 to react with each other to form the gate electrodes 4a, 4
b and a silicide layer (silicide layer made of Co silicide or Ti silicide) 1 on the surface layer of the semiconductor substrate 1
0 is formed. When forming Co silicide in this heat treatment, a nitrogen gas atmosphere (5 liter / mi) is used.
n) Perform RTA at 550 ° C. for 30 seconds underneath.
In the case of forming Ti silicide, the temperature is set to 650 ° C. under a nitrogen gas atmosphere (5 L / min).
Perform RTA for 0 seconds.

Next, unreacted Co, Ti or TiN is selectively etched away by immersion in a sulfuric acid / hydrogen peroxide mixture.

After that, a second heat treatment by RTA is performed to stabilize the silicide layer 10. In this case, Co
In stabilizing silicide, RTA is performed at about 700 ° C. to 850 ° C. for 30 seconds in a nitrogen gas atmosphere (5 L / min). In stabilizing Ti silicide, a nitrogen gas atmosphere (5 liter / mi) is used.
n) RTA at 800 ° C. for 30 seconds underneath.

After the above, as shown in FIG. 1 (5), an interlayer insulating film 11 made of silicon oxide is formed to a thickness of 600 nm. The following is an example of the conditions for forming the interlayer insulating film 11 by the CVD method. Film formation gas and flow rate; TEOS = 50 sccm, film formation atmosphere pressure: 40 Pa, semiconductor substrate temperature: 720 ° C.

Next, the interlayer insulating film 1 is formed by dry etching using a resist pattern (not shown) as a mask.
1 are formed with connection holes 12. An example of the dry etching conditions is shown below. Etching gas: cyclobutane octafluoride (C ₄ F ₈ ) = 50 sccm, RF power: 1200 W, etching atmosphere pressure: 2 Pa.

Thereafter, with the inner wall of the connection hole 12 being covered,
An adhesion layer 13 formed by laminating a Ti film and a TiN film is formed. An example of conditions for forming the adhesion layer 13 by sputtering will be described. -Ti film formation conditions, sputtering gas and flow rate; argon (Ar) = 100 sccm, sputtering atmosphere pressure: 0.47 Pa, power: 8 kW, film formation temperature: 150 ° C, film thickness: 30 nm. · TiN film conditions formation, the sputtering gas and the flow _{rate; Ar = 40sccm,; N 2} = 20sccm, sputtering atmosphere pressure; 0.47Pa, power; 5 kW, the thickness; 70 nm.

Thereafter, a plug 14 is formed in the connection hole 12 via the adhesion layer 13. Here, first, tungsten (W) having a film thickness of 400 nm is embedded in the connection hole 12.
A film is formed, and then this W film is etched back. An example of a film forming condition and an etch back condition of a W film is shown. W film formation conditions, film formation gas and flow rate; Ar = 2200 sccm; N ₂ = 300 sccm; hydrogen (H ₂ ) = 500 sccm; tungsten hexafluoride (WF ₆ ) = 75 sccm; Film formation temperature: 450 ° C., Etchback conditions for W film, etching gas and flow rate: sulfur hexafluoride (SF ₆ ) = 50 sccm, RF power: 150 W, etching atmosphere pressure: 1.33 Pa.

After the above, the Ti film 1 is formed on the interlayer insulating film 11.
An aluminum (Al) wiring 16a is formed through the metal layer 5. Here, first, a Ti film 15 and an Al film 16 are sequentially formed, and then these films are patterned by etching using a resist pattern (not shown) as a mask. An example of the conditions for forming the Ti film 15, the conditions for forming the Al film 16, and the etching conditions for these films are shown below. -Ti film formation conditions, sputtering gas and flow rate; argon (Ar) = 100 sccm, sputter atmosphere pressure: 0.47 Pa, power: 4 kW, film formation temperature: 150 ° C, film thickness: 30 nm. -Al film formation conditions, sputtering gas and flow rate; argon (Ar) = 50 sccm, sputter atmosphere pressure: 0.47 Pa, power: 22.5 kW, film formation temperature: 150 ° C, film thickness: 0.5 µm. Etching conditions for Al film and Ti film, etching gas and flow rate; boron chloride (BCl ₃ ) = 60 sccm; chlorine (Cl ₂ ) = 90 sccm, RF power: 50 W, microwave power: 1000 W, etching atmosphere pressure; 016 Pa.

As described above, the n-channel MOS transistor 17 and the p-channel MOS transistor 18
Are provided on the same semiconductor substrate to obtain a semiconductor device having a CMOS configuration. The gate electrode 4a of the n-channel MOS transistor 17 becomes n-type, and the gate electrode 4b of the p-channel MOS transistor 18 becomes p-type.

According to the manufacturing method of the first embodiment, as described with reference to FIG.
By introducing boron as an impurity, the crystal grain size of this polycrystalline silicon film 4 becomes smaller. Therefore, FIG.
As described with reference to (3), when performing the chemical treatment on the gate electrodes 4a and 4b obtained by patterning the polycrystalline silicon film 4, the chemical etching at the interface between the crystal grains of the polycrystalline silicon film 4 is performed by the gate electrode. It becomes difficult to progress in the depth direction of the gate electrodes 4a and 4b, and the surface roughness of the gate electrodes 4a and 4b is suppressed. Therefore, in the formation of the silicide layer 10 described with reference to FIG. 1D, the silicide layer 10 is formed on the surface layers of the gate electrodes 4a and 4b having less surface roughness, and the film of the silicide layer 10 is formed. The thickness is made uniform. As a result, it is possible to suppress the sheet resistance of the gate electrodes 4a and 4b including the n-type gate electrode 4a in which the reduction of the sheet resistance is particularly difficult to a stable low value.

(Second Embodiment) FIG. 2 is a sectional process view showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention. The second embodiment of the present invention will be described with reference to FIG. An embodiment will be described. The difference between the second embodiment and the first embodiment lies in a method of forming a polycrystalline silicon film formed on the gate insulating film 3.

That is, first, as shown in FIG.
After a gate insulating film 3 made of silicon oxide is formed on a semiconductor substrate 1 made of silicon, a polycrystalline silicon thin film 2 is formed.
0 is repeated a plurality of times (for example, four times), so that the polycrystalline silicon film 2 is formed by stacking a plurality of (for example, four) polycrystalline silicon thin films 20 on the gate insulating film 3.
Form one. This polycrystalline silicon film 21 is, for example, 5
It is formed to a thickness of 0 nm × 4 layers = 200 nm.

Thereafter, the gate electrode 21a (21b) is formed by patterning the polycrystalline silicon film 21 formed by laminating the polycrystalline silicon thin films 20 and the gate insulating film 3.

The conditions for forming the polycrystalline silicon thin film 20 are as follows:
The patterning of the polycrystalline silicon film 21 and the gate insulating film 3 is performed in the same manner as described in the first embodiment with reference to FIG.

Hereinafter, by carrying out in the same manner as described with reference to FIGS. 1 (2) to 1 (5) in the first embodiment,
As shown in FIG. 2B, a semiconductor device having a CMOS structure in which an n-channel MOS transistor 27 and a p-channel MOS transistor 28 are provided on the same semiconductor substrate 1 is obtained. The gate electrode 21a of the n-channel MOS transistor 27 becomes n-type, and the gate electrode 21b of the p-channel MOS transistor 28 becomes p-type. In FIG. 2A, only one of the n-type region and the p-type region is shown.

In the manufacturing method of the second embodiment, the polysilicon film 21 for forming the gate electrodes 21a and 21b is formed.
Is formed by laminating the polycrystalline silicon thin films 20, and the crystal grains in the depth direction are small. For this reason,
When removing the natural oxide film on the surface of the gate electrode 21a obtained by patterning the polycrystalline silicon film 21, even if the etching reaches the polycrystalline silicon film 21, chemical etching at the interface of the crystal grains is performed by the gate electrode 21a. , 21
b becomes difficult to travel in the depth direction, and the gate electrodes 21a, 2
1b can suppress the surface roughness. Therefore, the silicide layer 10 is formed on the surface layer of the gate electrodes 21a and 21b with less surface roughness, and the silicide layer 10
Is made uniform. As a result, the gate electrodes 21a,
The sheet resistance of 21b can be suppressed to a stable low value.

(Third Embodiment) FIG. 3 is a sectional process view showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention. The third embodiment of the present invention will be described with reference to FIG. An embodiment will be described. As shown in FIG.
The difference between this embodiment and the second embodiment is that, after forming each polycrystalline silicon thin film 20, the surface of each polycrystalline silicon 20 is oxidized to form an oxide thin film 30.

The oxidizing process is performed, for example, by forming the polycrystalline silicon thin film 20 and then exposing the semiconductor substrate 1 to the atmosphere or an oxidizing gas atmosphere. The oxide thin film 30 formed by this oxidation treatment
It is assumed that the film thickness is such that a tunnel current flows (that is, 1 nm or less). Thus, a polycrystalline silicon film 31 having the oxide thin film 30 interposed between the polycrystalline silicon thin films 20 is formed.

Thereafter, the polycrystalline silicon film 31 and the gate insulating film 3 formed by laminating the polycrystalline silicon thin film 20 with the oxide thin film 30 interposed therebetween are patterned to form a gate electrode 31a.
(31b) is formed.

Hereinafter, the same operation as that described in the first embodiment with reference to FIGS. 1 (2) to 1 (5) is performed, thereby forming the n-channel MOS transistor 37 as shown in FIG. 3 (2). A semiconductor device having a CMOS structure in which the p-channel MOS transistor 38 and the p-channel MOS transistor 38 are provided on the same semiconductor substrate is obtained. The gate electrode 31a of the n-channel MOS transistor 37 becomes n-type, and
The gate electrode 31b of the S transistor 38 becomes p-type.
In FIG. 3A, only one of the n-type region and the p-type region is shown.

According to the manufacturing method of the third embodiment, the polycrystalline silicon thin films 20 are separated by the oxide thin films 30. Therefore, when removing the natural oxide film on the surface of the gate electrode 31a, chemical solution etching at the interface between the crystal grains of the polycrystalline silicon film 31 is reliably prevented from progressing in the depth direction of the gate electrode 31a. Therefore, the gate electrodes 31a and 3a are more reliably provided than in the second embodiment.
The surface roughness of 1b is suppressed. As a result, the sheet resistance of the gate electrodes 31a and 31b can be suppressed to a more stable low value.

(Fourth Embodiment) FIG. 4 is a sectional process view showing a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention. The fourth embodiment of the present invention will be described with reference to FIG. An embodiment will be described.

The difference between the fourth embodiment and the first embodiment is that, after forming a gate insulating film 3 on a semiconductor substrate 1 as shown in FIG. The amorphous silicon film 41 is formed on the scale.
The thickness of the amorphous silicon film 41 is 200 nm, and an example of conditions for forming the amorphous silicon film 41 is described below. Silane (SiH ₄ ) = 100 sccm; helium (H ₂ ) = 400 sccm; nitrogen (N ₂ ) = 200 sccm; film-forming atmosphere pressure: 70 Pa; semiconductor substrate temperature: 580 ° C.

Thereafter, the amorphous silicon film 41 and the gate insulating film 3 are patterned to form a gate electrode 41a (4
1b) is formed. The patterning of the amorphous silicon film 41 and the gate insulating film 3 is performed in the first embodiment shown in FIG.
This is performed in the same manner as the patterning of the polycrystalline silicon film and the gate insulating film 3 described with reference to (1).

Hereinafter, the same operation as that described in the first embodiment with reference to FIGS. 1 (2) to 1 (5) is carried out, and as shown in FIG. A semiconductor device having a CMOS configuration in which the p-channel MOS transistor 48 and the p-channel MOS transistor 48 are provided on the same semiconductor substrate is obtained. The gate electrode 41a of the n-channel MOS transistor 47 becomes n-type, and
The gate electrode 41b of the S transistor 48 becomes p-type.
In FIG. 4A, only one of the n-type region and the p-type region is shown.

In the manufacturing method of the fourth embodiment, the amorphous silicon film 41 is patterned to form the gate electrodes 41a,
Since 41b is obtained, oxidation proceeds uniformly on the surfaces of the gate electrodes 41a and 41b having no crystal grain boundaries. Therefore, a natural oxide film having a uniform thickness is formed on the surfaces of the gate electrodes 41a and 41b, and the gate electrodes 41a and 4 obtained by removing the natural oxide film by a chemical solution treatment.
1b is one in which surface roughness is suppressed. Therefore, the silicide layer 10 is formed on the surface layer of the gate electrodes 41a and 41b with less surface roughness, and the thickness of the silicide layer 10 is made uniform. As a result, the sheet resistance of the gate electrodes 41a and 41b can be suppressed to a stable low value.

In the manufacturing method according to the first to fourth embodiments, n-type and p-type impurity ions are implanted after forming the sidewalls 7 described with reference to FIG. Before the process, a pre-treatment for removing a natural oxide film using hydrofluoric acid, a sidewall 7 and gate electrodes 4a, 4
A step of forming a silicon nitride film on the semiconductor substrate 1 in a state of covering b may be performed. This is defined in claim 3,
The method according to claim 6 or claim 8 is applied.

In this case, since impurity ions are introduced into the gate electrodes 4a and 4b through the silicon nitride film, roughening of the gate electrodes 4a and 4b due to knock-on of oxygen atoms is prevented. Therefore, the sheet resistance of the gate electrodes 4a and 4b can be suppressed to a stable low value further than in the above embodiments. In the second to fourth embodiments, the gate electrodes 4a, 4b
Are the gate electrodes 21a and 21b and the gate electrodes 31a and 3
1b or the gate electrodes 41a and 41b.

The manufacturing methods of the second to fourth embodiments may be combined with the manufacturing method of the first embodiment. That is, in the manufacturing methods of the second to fourth embodiments, after forming a film constituting a gate electrode on a gate insulating film, boron ions or compound ions containing boron are introduced into the entire surface of the film. You may do it. By doing so, in the manufacturing methods of the second to fourth embodiments, the effect of the first embodiment can be obtained in addition to the effect of each embodiment, and the sheet resistance of the gate electrode can be further reduced. It is possible to reduce it.

[0061]

As described above, according to the first aspect of the present invention,
According to the method for manufacturing a semiconductor device according to the above, by introducing boron to reduce the crystal grain size of the polycrystalline silicon film constituting the gate electrode, it is possible to prevent the surface of the gate electrode from being roughened by chemical etching. it can. Therefore,
By forming a silicide layer having a uniform thickness on the surface of the gate electrode, the sheet resistance of the gate electrode can be suppressed to a stable low value.

Further, according to the method of manufacturing a semiconductor device according to claim 4 of the present invention, the gate electrode is formed of a polycrystalline silicon film having a reduced crystal grain size by laminating a polycrystalline silicon thin film. Thus, surface roughness of the gate electrode due to chemical solution etching can be prevented. Therefore, it is possible to form a silicide layer having a uniform thickness on the surface of the gate electrode and to suppress the sheet resistance of the gate electrode to a stable and low value.

Further, according to the method of manufacturing a semiconductor device according to the seventh aspect of the present invention, the gate electrode is obtained by patterning the amorphous silicon film, so that the natural oxide film is formed on the surface of the gate electrode having no crystal grain boundaries. Can be uniformly grown, and the surface roughness of the gate electrode obtained by removing the natural oxide film by a chemical solution treatment can be prevented. Therefore, it is possible to form a silicide layer having a uniform thickness on the surface of the gate electrode and to suppress the sheet resistance of the gate electrode to a stable and low value.

[Brief description of the drawings]

FIG. 1 is a sectional process view for explaining a first embodiment.

FIG. 2 is a cross-sectional view illustrating a second embodiment.

FIG. 3 is a cross-sectional view for explaining a third embodiment.

FIG. 4 is a cross-sectional view for explaining a fourth embodiment.

FIG. 5 is a sectional process view for explaining a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 3 ... Gate insulating film, 4, 21, 31 ...
Polycrystalline silicon film, 4a, 4b, 21a, 21b, 31
a, 31b, 41a, 41b gate electrode, 7 sidewall, 10 silicide layer, 20 polycrystalline silicon thin film, 30 oxide thin film, 41 amorphous silicon film

Claims (8)

[Claims] A gate insulating film formed on a semiconductor substrate;
A first step of forming a polycrystalline silicon film on the gate insulating film;
A second step of introducing boron ions or boron-containing compound ions into the polycrystalline silicon film, a third step of patterning the polycrystalline silicon film and the gate insulating film to form a gate electrode, A fourth step of introducing n-type impurity ions into the gate electrode to make the gate electrode n-type, and a fifth step of forming a sidewall on a side wall of the gate electrode.
A step of removing a natural oxide film on the surface of the gate electrode by performing a chemical treatment on the surface of the gate electrode; and after forming a metal film on the semiconductor substrate in a state of covering the gate electrode. And forming a silicide layer on a surface layer of the gate electrode by reacting the metal film with the gate electrode. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the fourth step, n-type impurity ions are introduced only into a region where an n-type gate electrode is to be formed. Manufacturing method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein in the fourth step, a silicon nitride film is formed on the semiconductor substrate so as to cover the gate electrode, and then via the silicon nitride film. Introducing the n-type impurity ions into the gate electrode. 4. A polycrystalline silicon thin film is laminated on the gate insulating film by repeating a first step of forming a gate insulating film on a semiconductor substrate and forming a polycrystalline silicon thin film a plurality of times. A second step of forming a polycrystalline silicon film, a third step of patterning the polycrystalline silicon film and the gate insulating film to form a gate electrode, and a fourth step of introducing impurity ions into the gate electrode. A fifth step of forming a sidewall on a side wall of the gate electrode;
A step of removing a natural oxide film on the surface of the gate electrode by performing a chemical treatment on the surface of the gate electrode; and after forming a metal film on the semiconductor substrate in a state of covering the gate electrode. And forming a silicide layer on a surface layer of the gate electrode by reacting the metal film with the gate electrode. 5. The method of manufacturing a semiconductor device according to claim 4, wherein in the second step, during the formation of the polycrystalline silicon thin film, a surface of the polycrystalline silicon thin film is oxidized to form an oxide thin film. A method for manufacturing a semiconductor device, comprising: 6. The method for manufacturing a semiconductor device according to claim 4, wherein, in the fourth step, a silicon nitride film is formed on the semiconductor substrate in a state of covering the gate electrode, and then via the silicon nitride film. Introducing the impurity ions into the gate electrode. 7. A first step of forming a gate insulating film on a semiconductor substrate, a second step of forming an amorphous silicon film on the gate insulating film, the amorphous silicon film and the gate insulating film A third step of forming a gate electrode by patterning the gate electrode, a fourth step of introducing impurity ions into the gate electrode, and a fifth step of forming a sidewall on a side wall of the gate electrode.
A step of removing a natural oxide film on the surface of the gate electrode by performing a chemical treatment on the surface of the gate electrode; and after forming a metal film on the semiconductor substrate in a state of covering the gate electrode. And forming a silicide layer on a surface layer of the gate electrode by reacting the metal film with the gate electrode. 8. The method for manufacturing a semiconductor device according to claim 7, wherein in the fourth step, a silicon nitride film is formed on the semiconductor substrate in a state of covering the gate electrode, and then via the silicon nitride film. Introducing the impurity ions into the gate electrode.