JPH11307647A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable transistors of both PNP-type and NPN-type to be lessened in collector series resistance by a method, wherein an As-dopes embedded layer and an Sb-doped embedded layer are combined. SOLUTION: First and second epitaxial layers 22 and 23 are formed on a substrate 21. The epitaxial layers 22 and 23 are divided by isolation regions 24 and 25, and a base region 29 and an emitter region 30 are formed on the surface of an island region 26. First and third embedded layers 27 and 32 are formed between the substrate 21 and the first epitaxial layer 22, and second and a fourth embedded layers 28 and 33 are formed between the first and second epitaxial layer 22 and 23. The embedded layers 27 and 32 are formed using arsenic as the dopant, and the second embedded layer 28 is formed using antimony as dopant. An NPN transistor is formed above the first embedded layer 27, and a vertical PNP transistor is formed above the third embedded layer 32.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit in which an NPN transistor and a vertical PNP transistor are integrated, and particularly to a reduction in saturation voltage of both transistors.

[0002]

2. Description of the Related Art An NPN transistor, which is a main element in a bipolar IC, has a vertical P-type transistor which forms a complementary pair with the NPN transistor.
The NP transistor may be integrated. Vertical PNP
The transistor has a configuration in which a collector is formed by a P-type buried layer, an N-type buried layer is formed between the P-type buried layer and the substrate, and both are electrically detected. . At this time, since the collector buried layer is offset by the impurities of the N + buried layer and the collector resistance increases, an example in which a two-stage epitaxial structure is employed to avoid this is described in, for example, JP-A-59-172737. I have.

FIG. 4 is a sectional view showing an integrated circuit including such a vertical PNP transistor. Epitaxial layers 2 and 3 are sequentially stacked on a P-type substrate 1, N + type buried layers 4a and 4b are formed on the surface of the substrate 1, and a P + type buried layer 5 is formed on the surface of the lower epitaxial layer 2. ing. The NPN transistor includes the epitaxial layers 2 and 3
Is formed on the surface of the island region 7 formed by providing the P + isolation region 6 penetrating through the P + base region 8, the N + emitter region 9, and the N + collector contact region 10. The vertical PNP transistor forms a P + collector lead-out region 11 that reaches the P + buried layer 5 from the surface of the island region 7, and has a P-type emitter on its surface based on an N-type region surrounded by the collector lead-out region 11. A region 12 is formed, and an N + base contact region 13 is formed on the surface of the N-type base. The P + buried layer serves as the collector of the vertical PNP transistor.

In this structure, since the P + buried layer 5 is diffused from the surface of the epitaxial layer 2, the peak portion of the impurity concentration is not offset by the N + buried layer 4b, and therefore, the saturation voltage of the vertical PNP transistor is reduced. Can be reduced.

[0005]

The respective buried layers 4a, 4a
Since the impurity concentration of b and 5 is initially diffused to near the solid solution limit and then extended by heat treatment for diffusion, the peak concentration after diffusion is limited to about 1E19 atoms / cm3. Therefore, it has been a limit to decrease the sheet resistance by increasing the impurity concentration of each of the buried layers 4a, 4b, and 5.

[0006] On the other hand, integrated circuits have been miniaturized and the PN junction depth has become shallower due to the recent trend toward lighter and thinner and smaller and higher speed operation.
The thickness of the epitaxial layer also tends to be thin. For this reason, it is becoming difficult to provide a sufficient diffusion depth to each of the buried layers 4a, 4b, 5, and as a result, the diffusion depth becomes small, and the sheet resistance Rs of each of the buried layers 4a, 4b, 5 increases. Thus, there is a disadvantage that the collector series resistance Rc of both the NPN and PNP transistors increases.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems. In an NPN transistor, a first buried layer formed on a substrate surface and a surface of a first epitaxial layer are provided. In the case of a vertical PNP transistor, the P-type fourth buried layer formed on the surface of the first epitaxial layer is opposed to the third buried layer formed on the substrate surface in the vertical PNP transistor. And the second and third buried layers are made of arsenic,
By making the impurity of the buried layer of antimony,
An object of the present invention is to provide a semiconductor integrated circuit in which the series resistance of the collector is dramatically reduced for both the NPN transistor and the vertical PNP transistor.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below.
This will be described in detail with reference to FIG.

In the integrated circuit of the present invention, an N-type first epitaxial layer 22 is formed on a P-type single crystal silicon semiconductor substrate 21 to a thickness of about 5 to 7 μ by a vapor phase growth method.
Further, an N-type second epitaxial layer 23 is formed on the first epitaxial layer 22 to a thickness of about 8 to 11 μ by the same vapor phase growth method, and penetrates the first and second epitaxial layers 22 and 23. P + type isolation regions 24 and 25 are formed to form island regions 26a and 26b in which the first and second epitaxial layers 22 and 23 are junction-separated. One of the island regions 26a is an NPN transistor, and the other is an island region 26b. Is a vertical PNP transistor.

P + separation regions 24 and 25 for junction separation
Are diffused vertically from the surface of the first epitaxial layer 22, reach the surface of the substrate 21 in the downward direction, and are diffused upward in the middle of the second epitaxial layer 23. The P + isolation region 25 is diffused downward from the surface of the second epitaxial layer 23 and is connected to the isolation region 24.

Island region 26 in which an NPN transistor is formed
a, an N + type first buried layer 27 is formed between the substrate 21 and the first epitaxial layer 22;
It is diffused vertically from the boundary. An N + type second buried layer 28 is formed between the first epitaxial layer 22 and the second epitaxial layer 23, and is diffused vertically from a boundary portion. First buried layer 2
Numeral 7 is diffused upward by about 2 to 4 μ and extends halfway through the first epitaxial layer 22. Second buried layer 2
8 are vertically diffused from the surface of the first epitaxial layer 22 by about 4 to 5 μm, respectively.
In the middle of step 2, part of the first buried layer 27 overlaps.

A P-type base region 29 is formed on the surface of the island region 26a, and an N + emitter region 30 is formed on the surface of the base region 29. In addition, an N + collector low-resistance region 31 reaching the second buried layer 28 from the surface of the second epitaxial layer 23 is formed. The boundary between the first and second buried layers 27 and 28 and each epitaxial layer indicates a portion where the impurity concentration profile of each buried layer crosses the impurity concentration profile of the epitaxial layer.

In the island region 26b where the vertical PNP transistor is formed, the substrate 21 and the first epitaxial layer 2
An N + type third buried layer 32 is formed between the buried layer 2 and the second buried layer 32 and is diffused vertically from a boundary portion. A P + type fourth buried layer 33 is formed between the first epitaxial layer 22 and the second epitaxial layer 23, and is diffused vertically from a boundary portion. The third buried layer 32 and the first buried layer 27 are regions formed in the same step. The fourth buried layer 33 is vertically diffused from the surface of the first epitaxial layer 22 by about 5 to 7 μ each, and overlaps a part of the third buried layer 32. On the surface of the first epitaxial layer 22 surrounding the fourth buried layer, a fifth buried layer 28 formed simultaneously with the second buried layer 28 is formed.
Embedded layer 34 is formed.

On the surface of the island region 26b, a P + collector lead-out region 35 extending from the surface of the second epitaxial layer 23 to the P + fourth buried layer 33 is formed. A region 36 is formed. On the surface of the N-type base region 36, a P + -type emitter region 37 and an N + -type base contact region 38 are formed. This transistor is configured using the fourth buried layer 33 as a collector.

Then, as a feature of the present invention, the first and third buried layers 27 and 32 formed on the surface of the substrate 21 are formed.
Is formed using arsenic (As) as an impurity, the second buried layer 28 is formed using antimony Sb, and the fourth buried layer 33 is formed using boron (B). Arsenic is
If the diffusion coefficient is about half of that of antimony and the given thermal history is the same, arsenic has a shallower diffusion depth while maintaining a higher peak concentration. Therefore, the upward diffusion depth of the first and third buried layers 27 and 32 can be reduced.

This contributes to reducing the collector resistance of the vertical PNP transistor. That is, the amount of protrusion above the third buried layer 32 can be made smaller than that of the conventional buried layer formed of antimony, and as a result, the amount of overlap with the P + fourth buried layer 33 is reduced, and the range is extremely wide. By leaving the P-type region, the sheet resistance of the P + buried layer 33 is reduced.

Contrary to the vertical PNP transistor, N
In the PN transistor, the small diffusion depth of the buried layer increases the collector resistance. This problem can be solved by providing the second buried layer 28 made of antimony on the surface of the first epitaxial layer 22. By connecting and overlapping the second buried layer 28 and the first buried layer 27 having a large diffusion depth, the buried layer is formed to be wide, so that the sheet resistance can be greatly reduced. Of the complementary transistors of N
Both the PN type and the PNP type can dramatically reduce the collector series resistance Rc.

Hereinafter, a method of manufacturing the integrated circuit device of the present invention shown in FIG. 1 will be described.

First step: FIG. 2 (A) P-type single-crystal silicon substrate 21 having a specific resistance of several Ω · cm
Prepare Initially oxidize the surface to form an oxide film 40,
Openings are formed in the oxide film 0 by photoetching to serve as a selection mask, and arsenic As, which is an N-type impurity, is initially diffused to form first and third buried layers 27 and 32. For this diffusion, an arsenic ion implantation method is used.
~ 80 KeV, dose 1E14 ~ 1E15 atoms / cm2
Ion implantation under the conditions of
Heat treatment is performed at 000 to 1100 degrees for several hours.

Second step: FIG. 2B After removing the oxide film 40 and cleaning the surface, a first epitaxial layer 22 is formed on the substrate 21 by a vapor phase growth method. The first epitaxial layer 22 is 5-9E15
At an impurity concentration of atoms / cm 3, the film thickness was 5 to 7 μm. After that, an oxide film 41 is formed on the surface of the first epitaxial layer 22, an opening is formed in the oxide film 41 by photoetching to use as a selection mask, and antimony Sb as an N-type impurity is initially diffused to form a second and a second. 5 buried layers 28, 34
To form For this diffusion, an OCD solution (Tokyo Oka: trade name) is used as an impurity source. The solution is spin-on coated, baked to form a diffusion source film, and the substrate is subjected to a predetermined heat treatment to give a predetermined heat treatment to the surface of the substrate 21. After forming the initial diffusion layer, removing the diffusion source film,
Stretch diffusion is performed at 00 to 1100 ° C. for several hours. Subsequently, boron is ion-implanted into the surface of the first epitaxial layer 22 by changing the selection mask, and the P + isolation region 24 and the P + -type fourth buried layer 33 are formed by heat treatment at about 1000 ° C. for several hours. .

Third step: FIG. 3A The surface of the first epitaxial layer 22 is cleaned by removing the oxide film 41, and the second epitaxial layer 23 is formed by a vapor phase growth method. The second epitaxial layer 23 has a thickness of 5
Film thickness of 8-11 with impurity concentration of ~ 9E15 atoms / cm3
μ. Subsequently, an oxide film (not shown) is formed on the surface of the second epitaxial layer 23, a selective mask is formed at a position corresponding to the isolation region 24, phosphorus is selectively diffused, and a predetermined heat treatment is applied. The collector low-resistance region 31 reaching the second buried layer 28 is formed. Further, boron is diffused into the surface of the second epitaxial layer 23 corresponding to the fourth buried layer 33 to form the base region 36 of the vertical PNP transistor.

Fourth step: FIG. 3B An isolation region 25 is formed at a position corresponding to the isolation region 24 to connect them, and boron is diffused into the island region 26b to form an emitter region 37. A base region 29 is formed on 26a, and phosphorus is further diffused to form an N + emitter region 30 and a base contact region 38.

[0023]

As described above, the present invention provides the first
And the third buried layers 27 and 32 are formed of arsenic to reduce the collector series resistance of the vertical PNP transistor, and the second buried layers 27 and 32 are partially overlapped with the first buried layers 27.
By forming the buried layer of antimony with NPN,
The collector series resistance of the transistor can be reduced. This is equivalent to increasing the driving capability of the complementary transistor, and when compared with those having the same driving capability, the occupied area can be reduced and the chip size of the semiconductor integrated circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a cross-sectional view for explaining a manufacturing method.

FIG. 3 is a cross-sectional view for explaining a manufacturing method.

FIG. 4 is a cross-sectional view for explaining a conventional example.

Claims (2)

[Claims] 1. A semiconductor integrated circuit in which complementary transistors are integrated on the same substrate, wherein a first transistor of the opposite conductivity type is formed on a semiconductor substrate of one conductivity type.
And a second epitaxial layer; first and second island regions separating the first and second epitaxial layers; one of the complementary transistors formed in the first island region; A second transistor of the complementary transistor formed in the second island region, and a first buried layer of the opposite conductivity type formed between the substrate and the first epitaxial layer in the first island region ,
And a second buried layer of the opposite conductivity type formed between the first epitaxial layer and the second epitaxial layer; and a second buried layer of the second island region, A third buried layer of the opposite conductivity type formed therebetween,
And a fourth buried layer of one conductivity type formed between the first epitaxial layer and the second epitaxial layer, wherein the fourth buried layer forms a collector of the other transistor. A semiconductor integrated circuit, wherein the first and third buried layers are formed of arsenic, and the second buried layer is formed of antimony. 2. The method according to claim 1, wherein the first and second buried layers overlap,
In addition, the sum of the impurity concentrations at the overlapping portions is at least 1
2. The semiconductor integrated circuit according to claim 1, wherein E18 / cubic centimeter is maintained.