JPH11288376A5 - - Google Patents

Info

Publication number
JPH11288376A5
JPH11288376A5 JP1999000862A JP86299A JPH11288376A5 JP H11288376 A5 JPH11288376 A5 JP H11288376A5 JP 1999000862 A JP1999000862 A JP 1999000862A JP 86299 A JP86299 A JP 86299A JP H11288376 A5 JPH11288376 A5 JP H11288376A5
Authority
JP
Japan
Prior art keywords
code
cache
chunk
memory
portions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP1999000862A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11288376A (ja
Filing date
Publication date
Priority claimed from US09/003,568 external-priority patent/US6112280A/en
Application filed filed Critical
Publication of JPH11288376A publication Critical patent/JPH11288376A/ja
Publication of JPH11288376A5 publication Critical patent/JPH11288376A5/ja
Withdrawn legal-status Critical Current

Links

JP11000862A 1998-01-06 1999-01-06 キャッシュにおけるコ―ド変換方法 Withdrawn JPH11288376A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US003,568 1998-01-06
US09/003,568 US6112280A (en) 1998-01-06 1998-01-06 Method and apparatus for distinct instruction pointer storage in a partitioned cache memory

Publications (2)

Publication Number Publication Date
JPH11288376A JPH11288376A (ja) 1999-10-19
JPH11288376A5 true JPH11288376A5 (enExample) 2006-03-23

Family

ID=21706488

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11000862A Withdrawn JPH11288376A (ja) 1998-01-06 1999-01-06 キャッシュにおけるコ―ド変換方法

Country Status (3)

Country Link
US (1) US6112280A (enExample)
EP (1) EP0930572A3 (enExample)
JP (1) JPH11288376A (enExample)

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US6349363B2 (en) * 1998-12-08 2002-02-19 Intel Corporation Multi-section cache with different attributes for each section
GB2348305A (en) 1999-03-24 2000-09-27 Int Computers Ltd Instruction execution mechanism
US6493800B1 (en) * 1999-03-31 2002-12-10 International Business Machines Corporation Method and system for dynamically partitioning a shared cache
KR19990083691A (ko) * 1999-05-28 1999-12-06 김원선 전극봉식가습제어를포함한항온항습기제어용마이컴컨트롤러
US6591361B1 (en) 1999-12-28 2003-07-08 International Business Machines Corporation Method and apparatus for converting data into different ordinal types
US6859862B1 (en) 2000-04-07 2005-02-22 Nintendo Co., Ltd. Method and apparatus for software management of on-chip cache
US20030009750A1 (en) * 2001-07-09 2003-01-09 Robert Hundt Optimizing an executable computer program having linkage functions
US7904897B2 (en) * 2002-08-08 2011-03-08 Rudelic John C Executing applications from a semiconductor nonvolatile memory
GB2393274B (en) * 2002-09-20 2006-03-15 Advanced Risc Mach Ltd Data processing system having an external instruction set and an internal instruction set
US7124262B2 (en) * 2002-11-20 2006-10-17 Intel Corporation Selectivity pipelining and prefetching memory data
US7117306B2 (en) 2002-12-19 2006-10-03 Intel Corporation Mitigating access penalty of a semiconductor nonvolatile memory
US6781912B2 (en) * 2002-12-31 2004-08-24 Intel Corporation Providing protection against transistor junction breakdowns from supply voltage
US7103723B2 (en) * 2003-02-25 2006-09-05 Intel Corporation Priority-based code cache management
US7805710B2 (en) * 2003-07-15 2010-09-28 International Business Machines Corporation Shared code caching for program code conversion
GB0316532D0 (en) * 2003-07-15 2003-08-20 Transitive Ltd Method and apparatus for partitioning code in program code conversion
US7930486B2 (en) * 2007-04-30 2011-04-19 Hewlett-Packard Development Company, L.P. Cache chunked list concrete data type
US9807468B2 (en) * 2009-06-16 2017-10-31 Microsoft Technology Licensing, Llc Byte range caching
US8516230B2 (en) * 2009-12-29 2013-08-20 International Business Machines Corporation SPE software instruction cache
US8631225B2 (en) 2010-06-25 2014-01-14 International Business Machines Corporation Dynamically rewriting branch instructions to directly target an instruction cache location
US20110320786A1 (en) 2010-06-25 2011-12-29 International Business Machines Corporation Dynamically Rewriting Branch Instructions in Response to Cache Line Eviction
US9459851B2 (en) 2010-06-25 2016-10-04 International Business Machines Corporation Arranging binary code based on call graph partitioning
US8522225B2 (en) 2010-06-25 2013-08-27 International Business Machines Corporation Rewriting branch instructions using branch stubs
US20130140807A1 (en) * 2011-12-06 2013-06-06 Gerald Milroy Van Dusen Clamp with spring loaded bolt to repair broken exhaust manifold flange bolts
CN103150197B (zh) * 2013-02-07 2016-01-20 浙江大学 基于静态划分的代码Cache管理方法
CN114817090B (zh) * 2022-06-09 2023-06-02 远峰科技股份有限公司 低ram消耗mcu通信管理方法及系统

Family Cites Families (7)

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US4382278A (en) * 1980-06-05 1983-05-03 Texas Instruments Incorporated Hierarchial memory system with microcommand memory and pointer register mapping virtual CPU registers in workspace cache #4 and main memory cache
US5420993A (en) * 1991-06-13 1995-05-30 Unisys Corporation Extended address translation system for pointer updating in paged memory systems
DE9212788U1 (de) * 1992-09-23 1992-11-05 Nordischer Maschinenbau Rud. Baader GmbH + Co KG, 2400 Lübeck Fischbearbeitungsmaschine
US5404500A (en) * 1992-12-17 1995-04-04 International Business Machines Corporation Storage control system with improved system and technique for destaging data from nonvolatile memory
US5560013A (en) * 1994-12-06 1996-09-24 International Business Machines Corporation Method of using a target processor to execute programs of a source architecture that uses multiple address spaces
US5619665A (en) * 1995-04-13 1997-04-08 Intrnational Business Machines Corporation Method and apparatus for the transparent emulation of an existing instruction-set architecture by an arbitrary underlying instruction-set architecture
US5870576A (en) * 1996-12-16 1999-02-09 Hewlett-Packard Company Method and apparatus for storing and expanding variable-length program instructions upon detection of a miss condition within an instruction cache containing pointers to compressed instructions for wide instruction word processor architectures

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