JPH11282016A - Electrode wiring substrate provided with countermeasure against static electricity, and display device using this substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the yield by preventing the occurrence of dielectric breakdown in an insulating film between two electrode wirings, which are formed on an insulating substrate in different steps of the production process, in following steps of the production process. SOLUTION: A projection part 46c is formed on the insulating film between both layers in an area, where a projection part which induces discharge of static charge can be formed, on the outside of a picture element electrode forming area or the like to form a step part in one electrode 49A out of electrodes between which the insulating film is interposed, and the electrode shape on the way of the production process is constituted into an electric field concentration type so that discharge in the vertical direction between electrodes facing each other, namely, discharge between both layers may be induced, thus constituting an electrode wiring substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode wiring board having at least two layers of electrode wirings formed with an insulating layer interposed therebetween, and a display device using the same.

[0002]

2. Description of the Related Art In recent years, large-capacity, high-density display devices for liquid crystal display devices, such as television displays and graphic displays, have been actively developed and put into practical use. It is not only a simple matrix type liquid crystal display device that drives a liquid crystal simply by applying a voltage between a display electrode, that is, a counter electrode and a display pixel electrode in a time-division manner. The development of a liquid crystal display device called an active matrix type in which a switching element is incorporated in each case is being promoted and is being put to practical use.

In order to promote the spread of the active matrix type liquid crystal display device, it is necessary to reduce the price by improving the production yield.

There are several means for improving the manufacturing yield, one of which is to reduce the rate of defective display due to electrostatic breakdown in the manufacturing process. Various measures have been taken.

In a conventional active matrix type liquid crystal display device in which a countermeasure against electrostatic breakdown is taken, for example, in which a thin film transistor is used as a switching element, a ring-shaped conductor pattern called a short ring is formed around a display cell forming region. There is known a method in which all the scanning lines are connected to the auxiliary capacitance lines and the signal lines by arranging them.

FIG. 15 is a schematic plan view of a conventional TFT array substrate in a state where a short ring is formed during a manufacturing process. In FIG. 15, on a glass substrate 10, a plurality of scanning lines 11 and an auxiliary capacitance line 12 are formed as the same layer in parallel between the scanning lines 11.

A plurality of pixel electrodes 13 arranged in a matrix are formed on the auxiliary capacitance line 12 with an insulating film interposed therebetween. After the insulating film is formed on the entire surface, the scanning lines 11 and the auxiliary capacitance line are formed. And a plurality of signal lines 14 in a direction orthogonal to
Is formed.

In each of these wirings, a scanning line inspection electrode 15, a power supply electrode 16, and an auxiliary capacitance line inspection electrode 17 are formed outside the pixel electrode formation region.

Further, the scanning line 11, the auxiliary capacitance line 12, and the signal line 14 are electrically connected to each other by a short ring 18 formed around the display cell forming region in this manufacturing process. In addition, this short ring 18
The connection between the scanning line 11, the auxiliary capacitance line 12, and the signal line 14 is cut at the last stage of the manufacturing process.

As described above, by conducting all the scanning lines 11, the auxiliary capacitance lines 12, and the signal lines 14 by the short ring 18, the TFT array substrate of the active matrix type liquid crystal display device manufactured during the manufacturing process can be manufactured. Even if static electricity is charged after the formation of the short ring, a high potential difference between the wirings can be prevented, so that no electrostatic breakdown occurs.

[0011]

However, in practice, static electricity is often generated in the process before the formation of the short ring, and in such a case, a high potential difference is generated between the wirings. Electrostatic breakdown occurs in a wiring structure, an insulating film, and the like formed thereon before the short ring forming step.

For example, the short ring 1 shown in FIG.
In the process before the formation of the scanning lines 11 and the storage capacitance lines 1
2 and the respective test electrodes 15 and 17 connected to these wirings are formed. Thereafter, a resist for performing photo-etching for forming another pattern is applied on the substrate 10, and then heating is performed on a flat stage to evaporate the solvent of the resist.

After the heating step, as shown in FIG. 16, the TFT array substrate 10 is moved while floating above the transport belt 22 on the transport belt 22 having a plurality of transport rollers 21 to perform the next step. Transfer to When floating and transported by the plurality of transport rollers 21, TF
For example, several thousand volts of static electricity is charged between the T array substrate 10 and the transport belt 22 by peeling charging.

At this time, as shown in FIG.
The transfer position of the TFT array substrate 10 is corrected by the metal arm 23 attached to the TFT 2. At this time, the contact between the metal arm 23 and the TFT array substrate 10
The electric charge stored in the array substrate 10 rapidly moves toward the metal arm 23, causing electrostatic damage to the wiring structure and the insulating film of the TFT array substrate 10.

That is, as shown in FIG. 17, while a part of the region 24 of the TFT array substrate 10 is charged with a negative electric charge of several thousand volts, the metal arm 23 grounded thereto is Upon contact, the charged charge rapidly moves between the charged region 24 of the TFT array substrate 10 and the metal arm 23, and discharge occurs.

At this time, for example, the scanning line 11a arranged at a position close to the charged region 24 of the TFT array substrate 10
And the electrostatic charges on the auxiliary capacitance line 12a rapidly move in a discharge state in an insulating film such as an interlayer insulating film or the thin film semiconductor layer 26 through the scanning line 11b arranged between the metal arm 23 and the electrostatic charge. .

Here, in FIG. 17, the position of the signal line 14a to be formed in a subsequent step is shown by a two-dot chain line. Therefore, if such a discharge occurs after the formation of the signal line 14a, the charge may flow from the scanning line 11a or the auxiliary capacitance line 12a to the metal arm 23 through the signal line 14a via the insulating film, As a result, the scanning line 11a
In addition, the insulating film between the auxiliary capacitance line 12a and the signal line 14a is broken.

As a result of this discharge, for example, as shown in FIG. 18, a discharge occurs between the scanning line 11a and the metal arm 23, and the insulating film 25 and the thin film semiconductor layer 26 formed on the scanning line 11a And pinhole-like or crack-like damage 2 due to electrostatic breakdown along the portion where discharge has occurred.
7 results. When the signal line 14a is formed on the damaged portion 27 in a later step as shown in FIG. 19, for example, the signal line 14a and the scanning line 11a are short-circuited through the damaged portion 27. In the display operation described above, a display defect such as a line defect occurs in a pixel column corresponding to this portion.

Further, an active matrix type liquid crystal display device has been proposed in which a discharge projection is formed between electrode wirings adjacent to each other without using a short ring to take measures against electrostatic breakdown.

For example, as disclosed in US Pat. No. 5,677,745, a thin film transistor (hereinafter abbreviated as TFT) is used as a switching element, and a display signal line has a laminated structure including at least a semiconductor layer and a metal layer. ,
The outer shape of each layer is substantially the same, the display pixel electrode is located on the uppermost layer, and the scanning signal line and the inspection electrode of the auxiliary capacitance line are opposed to each other, between the scanning signal line and the auxiliary capacitance line. There is a configuration having a projection for inducing discharge of a charged electrostatic charge.

This example will be described below with reference to FIGS. 20 to 23 in accordance with the manufacturing process shown in FIG.

First, in a first step S1, a Ta film having a thickness of 3000 A is formed on the insulating substrate 31 by a sputtering method, and then the gate electrode G and the scanning signal line are formed by photo-etching as shown in FIG. 32a-32
c, auxiliary capacitance lines 33a to 33c, and an inspection electrode 34a having projections 37a to 371 connected to both wirings and protruding electrostatic discharges at positions facing each other.
To 34c and 36a to 36d are processed into predetermined shapes.

FIG. 21 is a sectional view taken along the line XXI-XXI of FIG. 20 and viewed in the direction of the arrow. In FIG. 21, the gap d between the electrodes 371 and 37m is a portion that operates as a discharge gap, and its size is discharged by a high voltage of several thousand volts due to static electricity generated during the manufacturing process. The value is set so that discharge will not occur at a voltage of at most several tens of volts generated under normal use conditions after shipment.

Next, in step S2, pattern inspection of the scanning signal line and the auxiliary capacitance line is performed, and then in step S3,
In S4, the first insulating film made of SiN is formed to 4000 A (angstrom), and a-S to be a TFT channel region is formed.
i film is 1000A, each of which is CVD (Chemical Vapor D
The entire substrate 31 is coated by an eposition method.

Next, at step S5, the T
After a 2000A film is formed on the FT channel etching protective film in the same manner by the CVD method, only this protective film is processed into a predetermined shape by photo-etching.

Next, in step S6, n +
After a 1000-A type a-Si film is formed and then 5000 A is formed by an Al sputtering method, a-Si and n + type a-Si and A
is processed into a predetermined shape, and the channel, source,
A drain electrode, a display signal line, an auxiliary capacitance line power supply wiring, and other display signal line layers are formed.

Next, the second insulating film made of SiN is
A 2000A film is formed by the method D. Then, step S8
Processing the first and second insulating films into predetermined shapes by photoetching, exposing the power supply electrodes of the scanning signal line, the auxiliary capacitance line, and the display signal line, and connecting the source electrode to the display pixel electrode. And a wiring as a connecting means between the scanning signal line wiring layer and the display signal line layer wiring.

Next, in step S9, the IT
After an O film is formed on the entire surface of the substrate at 1000 A, the display pixel electrode 13 and the pixel electrode layer connection wiring are processed into a predetermined shape by photo-etching. FIG. 23 shows a schematic plan view of the electrode wiring board at this time. Thus, an array substrate is completed.

Further, since the short ring is separated when the array substrate is completed on the way, not after the display device is completed,
After the separation, it is impossible to prevent the occurrence of display failure due to electrostatic breakdown.

The method of forming a discharge projection between the electrode wirings can be relatively easily realized between the electrode wirings formed in the same layer formed in one process. In the case where the electrode wiring is formed in different processes and an interlayer insulating film or the like is interposed therebetween,
It is extremely difficult to make a special electrical connection to prevent electrostatic breakdown due to discharge between the two during manufacturing.

In the case of the conventional manufacturing process shown in FIG. 22, a scanning signal line layer forming step (S1) and an insulating film forming step (S1) are performed.
3), a display signal line layer forming step (S4), a protective film forming step (S5), an insulating film processing step for forming various electrodes, and a display pixel electrode layer forming step (S9). In order to directly connect the scanning signal line layer formed first and the display signal line layer formed later, a conductive film or an insulating film is formed between the two. Difficult for.

For example, in order to electrically connect both layers, it is necessary to pass through the connection wiring of the display pixel electrode layer formed on the uppermost layer in the last step (S9) of the manufacturing process.
For this reason, in the step before the formation of the display pixel electrode layer, the scanning signal line layer and the display signal line layer are in a state of being electrically insulated. As a result, in the steps from the formation of the scanning signal line layer (S1) to the formation of the display pixel electrode layer (S9), the substrate 3
In the case where 1 is charged with static electricity, electrostatic breakdown due to the discharge of the static charge charged between the scanning signal line layer 32a and the display signal line 6 easily occurs.

Therefore, the present invention can prevent the occurrence of dielectric breakdown in an insulating film between two electrode wirings formed on an insulating substrate in different steps of the manufacturing process in a subsequent manufacturing process, thereby reducing the manufacturing yield. It is an object to provide an electrode wiring substrate that can be improved and a display device using the same.

[0034]

According to the present invention, there is provided an electrode wiring board for an electronic component, comprising: an insulating substrate; a first electrode wiring formed on the insulating substrate; and a first electrode wiring formed on the first electrode wiring. An insulating layer, and a second electrode wiring formed on the insulating layer, wherein the first and second electrode wirings each have a discharge portion at a position facing each other with the insulating layer interposed therebetween. Is configured.

Further, the display device of the present invention comprises a plurality of scanning lines formed on an insulating substrate, an insulating layer formed on the scanning lines, and a plurality of scanning lines provided on the insulating layer. Signal lines arranged so as to intersect lines with each other, and pixel electrodes arranged in each grid formed by the plurality of scanning lines and signal lines intersecting with each other via the insulating layer, A display device comprising: a pixel electrode array substrate comprising: a counter substrate facing the pixel electrode array substrate; and a light modulation layer held between the pixel electrode array substrate and the counter substrate. A discharge site is formed in each of the scanning line and a part of the signal line facing each other with an insulating layer interposed outside a region where an electrode is formed.

With the above configuration, two electrode wirings formed on the insulating substrate in different steps of the manufacturing process, for example, the electrostatic charges charged in the process from the formation of the scanning signal line layer to the formation of the display pixel electrode layer are applied to the pixel electrode. Electrostatic breakdown caused by discharge between the scanning signal line layer and the display signal line layer in the formed region can be suppressed, and the manufacturing yield can be improved.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment in which the present invention is applied to a liquid crystal display will be described with reference to the drawings.

FIG. 1 is a plan view showing a part of a semi-finished product in the course of manufacturing an array substrate of the liquid crystal display device of this embodiment. FIG. 2 is a sectional view taken along the line II-II in FIG. FIG.

The scanning signal lines 4 are provided on the surface of the glass substrate 40.
1a, 41b and auxiliary capacitance lines 42a, 42b are formed alternately and in parallel with each other. Scan signal lines 41a, 41b
The scanning signal line inspection electrodes 43a and 43b are provided in the vicinity of one end of each of them. Similarly, auxiliary capacitance line inspection electrodes 44a and 44b are formed at one ends of the auxiliary capacitance lines 42a and 42b. For example, Ta is used for the scanning signal lines 41a and 41b.
Alternatively, it can be formed using MoTa, AlNd, or the like.

A pair of discharge projections 45a to 45j are formed at both ends of the opposing end surfaces of the scanning signal line inspection electrodes 43a and 43b and the auxiliary capacitance line inspection electrodes 44a and 44b, respectively.

The discharge projections 45b, 45d, 45f, 45h, 45 formed on the auxiliary capacitance line inspection electrodes 44a, 44b.
j is formed with an insulating protrusion 46a to 46e corresponding to each. Each of these insulating protrusions 46a to 46e has a substantially rectangular shape with a long cross section extending in a direction crossing a straight line connecting a pair of opposed discharge protrusions.

FIG. 2 shows the scanning signal line inspection electrode 4 shown in FIG.
FIG. 11 is a cross-sectional view taken along a line II-II passing through a discharge protrusion 45e formed in 3b and a discharge protrusion 45f formed in the auxiliary capacitance line inspection electrode 44a. However, the manufacturing process of FIG.
After several steps from the steps of the manufacturing process.

In FIG. 2, the scanning signal line inspection electrode 43b and the auxiliary capacitance line inspection electrode 44a formed on the glass substrate 40 are entirely covered with an insulating SiO film 47. The insulating projection 46c is formed at a portion corresponding to the discharge projection 45f formed on the auxiliary capacitance line inspection electrode 44a. Other insulating protrusions 46a, 4
6b, 46d, and 46e are formed in the same positional relationship corresponding to the discharge projections 45b, 45d, 45h, and 45j.

In FIG. 2, an insulating film 48 is formed so as to cover the insulating protrusion 46c formed on the SiO film 47, and an auxiliary capacitance line power supply wiring 49 is formed thereon. The auxiliary capacitance line power supply wiring 49 has substantially the same width as the auxiliary capacitance line inspection electrodes 44a and 44b.
a, 41b and the auxiliary capacitance lines 42a, 42b are formed continuously in a direction substantially orthogonal to the auxiliary capacitance lines 42a, 42b.

As described above, the insulating protrusions 46a to 46e
Each has a substantially rectangular cross section extending in a direction transverse to a straight line connecting a pair of opposed discharge protrusions, and therefore has a storage capacitor line power supply wiring 49 formed thereon.
The edge portions of the stepped portions are also discharge protrusions 45a, 45c, 45
The portions facing e, 45g, and 45i are longer, and discharge is more likely to occur.

As shown in FIG. 2, the auxiliary capacitance line power supply wiring 4
When the positively charged portion 19 of the static electricity is formed in the pixel electrode formation region as shown in FIG. 1 in the manufacturing process in which the gate electrode 9 is formed, the positive charge is applied to the scanning signal line 41a and the scanning signal line inspection electrode. 43a, the auxiliary capacitance line 42a, and the auxiliary capacitance line inspection electrode 44a.

As a result, the auxiliary capacitance line power supply wiring 49 opposing the auxiliary capacitance line inspection electrode 44a via the insulating film 48.
A negative charge of several thousand volts is generated due to electrostatic induction, and an electric field concentrates on an edge portion of a step formed on the lower surface of the storage capacitor line power supply wiring 49, and the storage capacitor line is inspected via a discharge path C. Discharge occurs between the electrode 44a.

By this discharge, the positively charged portion 19 of the positive static electricity accumulated in the pixel electrode forming region disappears. Since the discharge path C passes through the insulating film 48 and the SiO film 47, a pinhole is formed here. However, since this pinhole is already covered by the auxiliary capacitance line power supply wiring 49, In the manufacturing process, there is no possibility that the conductor enters the pinhole and undesired conductive paths are formed.

As shown in FIGS. 1 and 2, since the auxiliary capacitance line inspection electrode 44a has a positive charge, the discharge projection 45e of the scanning signal line inspection electrode 43b opposed to the discharge projection 45f is also provided. A negative charge appears due to electrostatic induction, and the discharge path D
Discharge occurs via the

As described above, even if static electricity is generated in the pixel electrode forming region during the manufacturing process, these are immediately discharged through the discharge path formed around the pixel electrode forming region, thereby lowering the manufacturing yield. Discharge at such a position can be prevented.

Incidentally, for some reason, the auxiliary capacitance line power supply wiring 4
When static electricity is accumulated in the electrode 9, the electrodes 4 facing the
4a and a high potential difference, and the electrode 43b
, A high potential difference is also generated. For this reason, the electric field concentrates on the edge of the lower end of the step portion 49A of the electrode 49 facing the electrode 43b in FIG.

FIGS. 3 and 4 show a plan view and a cross-sectional view of the wiring electrode substrate in a process further after the manufacturing process shown in FIGS. 1 and 2, respectively.
9 is formed, the entire surface is covered with an insulating protective film 50,
A first contact hole 51 is formed by etching on a part of the surface of the auxiliary capacitance line power supply wiring 49 and corresponding to the auxiliary capacitance line inspection electrodes 44a and 44b.

Further, a second contact hole 52 is formed adjacent to the first contact hole 51 and at a portion corresponding to the auxiliary capacitance line inspection electrodes 44a and 44b. First
The contact hole 51 removes the protective film 50 to expose the surface of the auxiliary capacitance line power supply wiring 49, and the second contact hole 52 removes the insulating film 47 to expose the surface of the auxiliary capacitance line inspection electrode 44b.

After the first and second contact holes 51 and 52 are formed, these contact holes 51 and 52 are formed.
The display pixel electrode layer connection wiring 53 is formed therein. When the process proceeds to this step, the auxiliary capacitance line power supply wiring 49 and the auxiliary capacitance line inspection electrode 44 are connected via the display pixel electrode layer connection wiring 53.
b is connected, and there is no need to use the discharge path C described with reference to FIG.

Through the above steps, an electrode wiring substrate having the structure shown in FIG. 6, that is, an array substrate of a liquid crystal display device is finally formed. In FIG. 6, pixel electrodes 55 arranged in a matrix in a display area on a substrate 40 include a plurality of display signal lines 58a to 58n arranged in a direction orthogonal to the scanning signal lines 41a to 41n and a TFT element. It is connected via 56. The gate G of the TFT element 56 is connected to the scanning signal lines 41a to 41n, and one end thereof is connected to a plurality of pads 57a to 57n formed outside the display area via the scanning signal line inspection electrodes 43a to 43n. . One ends of the plurality of display signal lines 58a to 58n are connected to the plurality of pads 59a to 59n outside the display area.

Here, referring to FIG. 5, FIGS.
A manufacturing process of the electrode wiring board having the configuration described with reference to FIG. 6 will be described.

First, in the first step S11, a Ta film is formed to a thickness of 3000 A on the insulating substrate 40 by the sputtering method, and then, as shown in FIG. 1, the scanning signal lines 41a, 41b, Auxiliary capacitance line 4
2a, 42b, and a projection 45 for inducing a discharge of charged static electricity at positions opposite to each other and connected to both wirings.
Test electrodes 43a to 43c and 44 having a to 45j
a, 44b are processed into a predetermined shape. Here, MoTa or AlNd can be used instead of Ta.

FIG. 2 is a sectional view taken along the line II-II of FIG. 1 and viewed in the direction of the arrow. In FIG. 2, the electrodes 43b and 4
4a is a portion that operates as a discharge gap, and as described above, its size is discharged by a high voltage of several thousand volts due to static electricity generated during the manufacturing process, but is shipped as a product. The voltage is set so that no discharge occurs at a voltage of at most several tens of volts generated in a normal use condition after the battery is used.

In FIG. 2, the scanning signal line inspection electrode 43b and the auxiliary capacitance line inspection electrode 44a formed on the glass substrate 40 are entirely covered with an insulating SiN film 47. Are insulating protrusions 4 corresponding to the discharge protrusions 45f formed on the auxiliary capacitance line inspection electrodes 44a.
6c is formed. Other insulating protrusions 46a, 46b, 4
6d and 46e have the same positional relationship as the discharge protrusion 45.
b, 45d, 45h, 45j.

In FIG. 2, an insulating film 48 is formed so as to cover the insulating protrusion 46c formed on the SiN film 47, and an auxiliary capacitance line power supply wiring 49 is formed thereon. The auxiliary capacitance line power supply wiring 49 has substantially the same width as the auxiliary capacitance line inspection electrodes 44a and 44b.
a, 41b and the auxiliary capacitance lines 42a, 42b are formed continuously in a direction substantially orthogonal to the auxiliary capacitance lines 42a, 42b.

As described above, the insulating protrusions 46a to 46e
Each has a substantially rectangular cross section extending in a direction transverse to a straight line connecting a pair of opposed discharge protrusions, and therefore has a storage capacitor line power supply wiring 49 formed thereon.
The edge portions of the stepped portions are also discharge protrusions 45a, 45c, 45
The portions facing e, 45g, and 45i are longer, and discharge is more likely to occur.

Next, after the pattern inspection of the scanning signal line and the auxiliary capacitance line is performed in step S12, step S1 is performed.
3. In S14, a first gate insulating film made of SiN
Is formed to a thickness of 4000 A, and then an a-Si film serving as a channel region of the TFT is formed to a thickness of 1000 A over the entire substrate 40 by a CVD (Chemical Vapor Deposition) method.

Next, at step S5, the T
After a 2000A film is formed on the FT channel etching protective film in the same manner by the CVD method, only this protective film is processed into a predetermined shape by photo-etching. In the step of forming the etching protection film for the channel, the projection member 46c shown in FIG. The projection member 46c is a pattern for forming a step portion 49A on the auxiliary capacitance line power supply electrode 49 in a subsequent step. The height of the projecting member, that is, the step 46c, is not less than 1000 angstroms, preferably from 2000 angstroms to 3 angstroms.
It is formed with dimensions between 300 Angstroms.

FIG. 1 is a schematic plan view of the insulating substrate 40 on which the projecting members 46a to 46e are formed.

Next, at step S16, n
After forming a + -type a-Si film at 1000 A, and subsequently forming an aluminum film at 5000 A by the Al sputtering method, in step S17, the a-Si film and the n +
The mold a-Si film and the Al film are processed into a predetermined shape, and FIG.
As shown in the figure, the channel of the TFT 56 and the source electrode 5
6a, drain electrode 56b, display signal lines 58a to 58n
Then, the auxiliary capacitance line power supply wiring 49 and other display signal line layers are formed. At this time, as shown in the cross-sectional view of FIG. 2, a step 49A is formed in a part of the auxiliary capacitance line power supply wiring 49.
The display signal line layer is made of Mo / Al / Mo other than Al.
, A single layer of Mo, or AlNd.

Next, the second insulating film made of SiN is
A 2000A film is formed by the method D. Then, step S1
At 8, the first and second insulating films are processed into a predetermined shape by photo-etching, the power supply electrodes of the scanning signal line, the auxiliary capacitance line, and the display signal line are exposed, and the connection between the source electrode and the display pixel electrode is performed. Wiring as means, and wiring as connecting means between the scanning signal line wiring layer and the display signal line layer wiring are formed.

Finally, in step S19, an ITO film, which is a transparent electrode, is formed on the entire surface of the substrate by sputtering to a thickness of 1000A, and then the display pixel electrode 55 and the pixel electrode layer connection wiring 53 are processed into a predetermined shape by photo-etching. This transparent electrode can be formed using InZnO or amorphous ITO in addition to the ITO film. When amorphous ITO is used, oxalic acid that does not attack Al is used as an etching solution for the amorphous ITO. Therefore, it is desirable to use Al also as the display signal line.

Thus, an array substrate is completed.

It is widely known that the charge distribution in a conductor is concentrated on a portion having a small radius of curvature. For this reason, charges between the scanning signal line inspection electrode 43b and the auxiliary capacitance line inspection electrode 44a or between the scanning signal line inspection electrode 43b and the auxiliary capacitance line power supply wiring 49 are concentrated on the respective projecting portions as shown in FIG. As a result, the projections 45e, 45f facing each other,
In addition, a strong electric field is formed between the step portions 49A, and discharge is easily generated.

As a result, as shown in the discharge paths C, D, and E in FIG. 2, between the step portion 49A of the auxiliary capacitance line power supply wiring 49 and the scanning signal line inspection electrode 43b or the auxiliary capacitance line inspection electrode 44a. The discharge of the charged electrostatic charge is likely to occur, and an inadvertent discharge at the opposing portion between the scanning signal line 41b and the auxiliary capacitance line inspection electrode 44a as shown in the discharge path F in FIG. 1 is suppressed.

This is because, as shown in FIGS. 1 and 2, after the formation of the auxiliary capacitance line power supply wiring 49 electrically insulated from the scanning signal line layer 41b, the display pixel electrode layer connection wiring shown in FIG. The same applies to the steps up to the formation of the film 53.

In particular, the stepped portion 4
By forming 9A, as shown in FIG. 2, charges concentrate on the step portion 49A, so that the electric field in the vertical direction on the insulating substrate 40 is strengthened. As a result, FIG.
The discharge easily occurs between the scanning signal line layer 43b and the auxiliary capacitance line power supply wiring 49 as shown in the discharge paths C and E of FIG.

Further, depending on the means for forming the step portion 49A, the quality of the insulating films 47 and 48 of the step portion 49A may be changed.
The electrostatic withstand voltage may be lower than in other places. As a result, discharge between the scanning signal line layer 43b and the auxiliary capacitance line power supply wiring 49 in the step portion 49A is more likely to occur.

Therefore, it is possible to reduce the occurrence of defective display due to interlayer short-circuit due to electrostatic breakdown, and to improve the production yield.

The construction of the embodiment in which the protrusions 46a to 46e are formed by SiN shown in FIG. 1 in a self-alignment type shown in FIG. 1 will be described with reference to FIGS. FIG. 7 is a plan view of the insulating substrate 40 in a step corresponding to FIG. 1. Only the portions of the protrusions 46a to 46e are different from FIG. 1, and in FIG. Only the portion of the portion 46e will be described, but the other portions of FIG. 7 will be assigned the same reference numerals as those of FIG. 1 and detailed description will be omitted.

FIG. 8 is an enlarged view of a circle VIIIA in FIG.
A. In the figure, it is assumed that the short side of the protrusion 46e made of SiN is formed substantially parallel to the oblique side of the protrusion 45j of the auxiliary capacitance line inspection electrode 44b formed therebelow by self-alignment formation. Features.

That is, at the time of manufacture, as shown in FIG.
An a-Si film 61 is formed on the surface of the SiO film 47 corresponding to the projection 45j of the auxiliary capacitance line inspection electrode 44b formed on the surface of the glass substrate 40, and the SiN film 6 is further formed thereon.
Form 2 Thereafter, a mask 63 having a planar shape corresponding to the protrusion 46e is formed using a resist, and etching is performed to remove the SiN film 62 and the a-Si film 61, leaving the protrusion 46e below the mask 63, Finally, the mask 63 is removed. Subsequent steps are the same as in the previous embodiment.

In each of the above two embodiments,
A projection is formed by N, and a step is formed when the auxiliary capacitance line feeding electrode is formed based on the projection. Instead of forming this step, an auxiliary portion is formed as shown in FIG. Edge portion 4 at the lower end of the side surface of capacitance line power supply wiring 49
9E may be arranged so as to be close to the bent portion 45A at the upper end of the projection 45 of the auxiliary capacitance line inspection electrode 44 just below it and to face the projection 45 of the scanning line inspection electrode 43. As a result, a discharge projection is formed substantially without forming a step, and discharge paths C ′ and E ′ are formed.

FIGS. 10 to 12 show still another embodiment of the present invention. In this embodiment, an interlayer discharge path similar to that of the above embodiment is formed in a wiring portion 72 for supplying power from the array substrate 70 outside the image forming portion 71 of the array substrate 70 to a counter electrode on a counter substrate (not shown). is there.

FIG. 11 is an enlarged plan view showing a portion surrounded by a circle XI in FIG. 10, and FIG. 12 is a line XII in FIG.
It is sectional drawing cut | disconnected in -XII and shown in an arrow direction. FIG.
1, in FIG. 12, a first power supply wiring layer 75 of a first layer is formed on the surface of a glass substrate 73. A discharge projection 75A is formed at the tip of the first power supply wiring layer 75. Further, the second power supply wiring layer 76 having a discharge projection 76A at a predetermined distance from the discharge projection 75A is the same as the first power supply wiring layer 76.
Formed in layers. Here, the first power supply wiring layer 75 is formed in the same step as the scanning line.

An interlayer insulating layer 77 is formed on the first and second power supply wiring layers 75 and 76 formed on the first layer. In the interlayer insulating film 77, a contact hole 78 exposing the first power supply wiring layer 75 is formed. The second-layer power supply wiring layers 79 and 80 are formed on the interlayer insulating film 77, and the insulating layer 81 is formed thereon. A contact hole 82 exposing the power supply wiring layer 79 is formed in the insulating layer 81 formed on one power supply wiring layer 79 of the second layer.
Is formed, and the whole is covered with a third-layer conductive film 83 to connect between the contact holes 78 and 82. Here, the second-layer power supply wiring layer 80 is formed in the same step as the signal line, and the third-layer conductive film 83 is formed in the same step as the pixel electrode.

FIG. 12 is a sectional view taken along the line XII-XII of FIG. 11 and viewed in the direction indicated by the arrow.

Here, after the entire structure is covered with the third conductive film 83, the first power supply wiring layer 75 and the second power supply wiring layers 79 and 80 are electrically connected. Therefore, there is no problem even if high-voltage static electricity is charged in the first power supply wiring layer 75 or the second power supply wiring layers 79 and 80 during the manufacturing process.

On the other hand, before being covered by the third conductive film 83, the first power supply wiring layer 75 or the second
When the high voltage static electricity is charged to the power supply wiring layers 79 and 80 of the first layer, the plurality of discharge protrusions 75A and 76A of the first and second power supply wiring layers 75 and 76 formed on the first layer. Discharge occurs or the first and second power supply wiring layers 75 and 76 formed on the first layer and the second power supply wiring layer 79,
Discharge occurs between the gate electrode 80 and the gate electrode 80 via the interlayer insulating layer 77.

For example, in FIG. 12, a first power supply wiring layer 75 formed in the first layer and a second power supply wiring layer 79,
When a high voltage is applied between the power supply wirings 80 and 80, discharge paths F and F 'are formed between the second power supply wiring layers 79 and 80 and the edges of the ends, and the discharge is performed safely. Will be

The present invention also relates to a TFT arranged in each pixel.
This is also effective in the case where each scanning signal line and display signal line are electrically connected to a short ring via a variable resistance element formed in the same manner as described above. This is because the electrical connection between the variable resistive element itself and the variable resistive element and the short ring is performed by forming the display pixel electrode layer. Therefore, the short ring structure is not completed in the process before the formation of the display pixel electrode layer. This is because they do not contribute to preventing electrostatic breakdown.

FIG. 13 shows an unfinished structure of an array substrate in a manufacturing process of another embodiment according to the present invention. In the figure, scanning line power supply electrodes 91a and 91b are connected to scanning lines 95a and 95b via scanning line inspection electrodes 94a and 94b, respectively. The auxiliary capacitance line feeding electrode 92 is commonly used for the auxiliary capacitance line 9.
6a and 96b. FIG. 13 shows the scanning lines 95a, 95
5B shows a state in which a scanning line layer including 5b and gates of the TFTs 93a and 93b is formed. Therefore, the scanning lines 95a,
95b is a short ring TFT 93a, 9 at this stage.
It is not connected to the signal line 97 via 3b. The short ring TFTs 93a and 93b are completed in a later manufacturing process. Therefore, the scanning lines 95a, 95
b and the signal line 97 are not connected to each other at this stage.

In order to prevent undesired dielectric breakdown defects in the manufacturing process at this stage, in the configuration shown in FIG. 13, the auxiliary capacitance line power supply electrode 92 and the scanning line inspection electrodes 94a and 94b are used.
And a discharge projection 98 formed on the substrate. These electrodes 92,
94a and 94b are formed by different manufacturing steps, and an insulating layer (not shown) is formed between these electrodes 92, 94a and 94b.

Therefore, the short ring TFT 93
Until a and 93b are completed, unnecessary charges can be discharged through the discharge projections 98 in the same manner as in the previous embodiment, and a short circuit at the intersection between these electrodes 92, 94a and 94b is effectively prevented. Can be prevented.

FIG. 14 shows an example of the configuration of a TFT switching element connected between a signal line and a pixel electrode of a display device according to the present invention. In the figure, a gate electrode 107 is formed on a glass substrate 100. This gate electrode 10
The scanning line (not shown) connected to 7 is also formed on the same layer. The entire surface of the substrate 100 including the gate electrode 107 is covered with a gate insulating layer 106.
The a-si semiconductor layer 104 is formed thereon.

An ohmic contact layer 105 is formed on the semiconductor layer 104, an etching protection film 102 is formed between the layers 104 and 105 at a portion where an etching hole 108 is formed in a later step, and a source electrode 101 and a drain electrode are formed. 103 are formed on the gate electrode 107. The etching protection film 102 is formed in a step in which the discharge protrusion is formed. Thus, the TFT switching element is formed on the substrate 100.

[0092]

As described in detail above, according to the present invention,
In a region where the scanning signal line layer and the display signal line layer, which are electrically insulated and stacked, overlap each other, for example, in a region where a protrusion for inducing electrostatic discharge is formed, such as outside the pixel electrode formation region. By forming a step in the insulating film between the two layers, a vertical discharge between the opposing electrodes, that is, a discharge between the two layers can be induced. As a result, it is possible to provide an electrode wiring substrate and a display device using the same, which can reduce the occurrence of defective display due to electrostatic breakdown and can improve the production yield.

[Brief description of the drawings]

FIG. 1 is a plan view showing a planar structure during a manufacturing process of an array substrate according to an embodiment of the present invention.

FIG. 2 shows II-II in a step after the step of FIG.
Sectional drawing which shows the cross-section of the array board | substrate cut | disconnected by a line and seen in the arrow direction.

FIG. 3 is a plan view showing a planar structure of an array substrate during a process after the manufacturing process of FIG. 2;

FIG. 4 is a view showing IV-IV in a step after the step in FIG. 3;
Sectional drawing which shows the cross-section of the array board | substrate cut | disconnected by a line and seen in the arrow direction.

FIG. 5 is a diagram showing a flow of a manufacturing process of an array substrate according to one embodiment of the present invention.

FIG. 6 is a configuration diagram schematically showing a planar structure of an array substrate in a final step of the manufacturing process of FIG. 5;

FIG. 7 is a plan view showing a planar structure during a manufacturing process of an array substrate according to another embodiment of the present invention.

FIGS. 8A and 8B are a plan view and a cross-sectional view, respectively, showing the inside of a circle VIIIA in FIG. 7 in an enlarged manner.

FIG. 9 is a diagram showing a partial cross-sectional structure during a manufacturing process of an array substrate according to still another embodiment of the present invention.

FIG. 10 is a plan view showing a planar structure during a manufacturing process of an array substrate according to another embodiment of the present invention.

FIG. 11 is an enlarged plan view showing the inside of a circle XI in FIG. 10;

FIG. 12 is a sectional view taken along line XII-XII of FIG. 11 and viewed in the direction indicated by the arrow.

FIG. 13 is a plan view showing an array substrate during a manufacturing process according to still another embodiment of the present invention.

FIG. 14 is a sectional view showing the structure of a switching element formed in an array substrate according to an embodiment of the present invention.

FIG. 15 is a diagram showing an electrode wiring structure of a conventional array substrate.

FIG. 16 is a perspective view showing a part of a conventional apparatus for manufacturing an array substrate.

FIG. 17 is a diagram showing a state of discharge of static electricity on the array substrate shown in FIG. 16;

FIG. 18 is a cross-sectional view showing a state of discharge breakdown when a discharge occurs between electrodes having a laminated structure.

FIG. 19 is a diagram showing a state in which a conductor has entered a discharge breakdown portion formed in FIG. 18;

FIG. 20 is a plan view of an array substrate showing one conventional method for preventing discharge breakdown.

21 is a sectional view taken along the line XXI-XXI in FIG. 20 and viewed in the direction of the arrow.

FIG. 22 is a flowchart showing a manufacturing process of the array substrate of FIG. 20;

FIG. 23 is a schematic plan view of the array substrate in a final step of the manufacturing process of FIG. 22;

[Explanation of symbols]

 Reference numeral 40: glass substrate 41a, 41b: scanning signal line 42a, 42b: auxiliary capacitance line 43a-43b: scanning signal line inspection electrode 44a, 44b: auxiliary capacitance line inspection electrode 45a-45j: discharge projection 46a-46e: insulating projection 47 ... SiO film 48 ... insulating film 49 ... auxiliary capacitance line power supply wiring

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H05K 1/02 H01L 29/78 612A 623A 626A

Claims (21)

[Claims] An insulating substrate, a first electrode wiring formed on the insulating substrate, an insulating layer formed on the first electrode wiring, and a first electrode formed on the insulating layer. An electrode wiring board for an electronic component, comprising: two electrode wirings, wherein the first and second electrode wirings each have a discharge site at a position facing each other with the insulating layer interposed therebetween. 2. The method according to claim 1, wherein each of the first and second electrode wirings is formed in a strip shape, and a side edge portion thereof is formed as the discharge site in proximity to each other with the insulating layer interposed therebetween. Item 2. An electrode wiring board for an electronic component according to item 1. 3. The electrode wiring board according to claim 1, wherein the first and second electrode wirings have a discharge protrusion for concentrating an electric field on at least one of the discharge sites. 4. A step is formed at a position of the insulating layer corresponding to the discharge site, and the second electrode wiring formed on the insulating layer is formed on a surface of the insulating layer and a side surface of the step. 2. The electrode wiring board for an electronic component according to claim 1, further comprising a protrusion corresponding to the discharge portion formed between the electrodes. 5. A plurality of scanning lines formed on an insulating substrate, an insulating layer formed on the scanning lines, and arranged on the insulating layer and arranged to intersect with the scanning lines. A pixel electrode array substrate comprising: a plurality of signal lines, and a plurality of scanning lines and signal lines, and pixel electrodes disposed in each grid formed to intersect with each other via the insulating layer. A display device comprising: a counter substrate facing the pixel electrode array substrate; and a light modulation layer held between the pixel electrode array substrate and the counter substrate. A display device, wherein a discharge site is formed in each of the scanning line and a part of the signal line opposed to each other with an insulating layer interposed therebetween. 6. The scanning line and the signal line are each formed in a strip shape, and a side edge portion thereof is formed as the discharge site close to each other with the insulating layer interposed therebetween. The display device according to the above. 7. The display device according to claim 5, wherein the scanning line and the signal line have a discharge protrusion on at least one of the discharge portions. 8. A step is formed at a position corresponding to the discharge portion of the insulating layer, and the signal line formed on the insulating layer is provided between a surface of the insulating layer and a side surface of the step. The display device according to claim 5, further comprising a protrusion corresponding to the formed discharge portion. 9. The display device according to claim 8, wherein the height of the projection is not less than 1000 Å. 10. The display device according to claim 9, wherein the height of the protrusion is 2000 Å or more. 11. The switching element according to claim 8, wherein a switching element is formed between the signal line and the pixel electrode, and the projection is formed in the same step as an etching protective film used when forming the switching element. Display device. 12. A plurality of scanning lines and a plurality of auxiliary capacitance lines formed on an insulating substrate, and a layer different from the layer on which the scanning lines and the auxiliary capacitance lines are formed via an insulating layer; A signal line arranged so as to intersect with the scanning line and the auxiliary capacitance line, and a pixel arranged in each lattice formed by intersecting the plurality of scanning lines and the plurality of signal lines with each other A pixel electrode array substrate comprising:
In a display device, comprising: a counter substrate facing the pixel electrode array substrate; and a light modulation layer held between the pixel electrode array substrate and the counter substrate, wherein the scanning lines facing each other with the insulating layer interposed therebetween One or both of the auxiliary capacitance lines and the corresponding signal lines are arranged in a band substantially in parallel with the same process in the same step, and the auxiliary capacitance line power supply wiring for electrically connecting the auxiliary capacitance lines has a discharge A display device, wherein a part is formed. 13. A step is formed at a position of the insulating layer corresponding to the discharge site, and an auxiliary capacitance line power supply wiring formed on the insulating layer is formed between a surface of the insulating layer and a side surface of the step. The display device according to claim 12, further comprising a protruding portion corresponding to the discharge portion formed therebetween. 14. The display device according to claim 13, wherein the height of the protrusion is not less than 1000 Å. 15. The display device according to claim 14, wherein the height of the protrusion is 2000 Å or more. 16. The switching element according to claim 13, wherein a switching element is formed between the signal line and the pixel electrode, and the projection is formed in the same step as an etching protection film used when forming the switching element. Display device. 17. A method according to claim 17, wherein a first contact hole and a second contact hole are formed, and the auxiliary capacitance line power supply line and the auxiliary capacitance line inspection electrode are connected to a pixel electrode layer connection line. The display device according to claim 13. 18. A plurality of scanning lines formed on an insulating substrate and arranged on a layer different from the layer on which the scanning lines are formed via an insulating layer, and arranged so as to intersect with the scanning lines. A pixel electrode array substrate, comprising: a plurality of signal lines; a plurality of scanning lines and a plurality of signal lines; and a pixel electrode disposed in each grid formed to intersect with each other. A display device comprising: a counter substrate having a counter electrode facing the electrode array substrate; and a light modulation layer held between the pixel electrode array substrate and the counter substrate, wherein the pixel electrode array substrate has A power supply line for supplying power to the counter electrode is disposed. The power supply line has first and second power supply wiring layers formed with an interlayer insulating film interposed therebetween. Display device characterized in that discharge is performed in . 19. A plurality of scanning lines formed on an insulating substrate and arranged on a layer different from the layer on which the scanning lines are formed via an insulating layer, and are arranged so as to intersect with the scanning lines. And a pixel electrode disposed at each intersection formed by intersecting the plurality of scanning lines and the plurality of signal lines, wherein the electrode wiring substrate further comprises: A power supply line for supplying power to an external circuit; the power supply line includes first and second power supply wiring layers formed with an interlayer insulating film interposed therebetween;
An electrode wiring board, wherein discharge is performed between second power supply wiring layers. 20. A method according to claim 1, wherein a plurality of scanning lines and a plurality of auxiliary capacitance lines are formed on an insulating substrate, and the scanning is performed on a layer different from a layer on which the scanning lines and the auxiliary capacitance lines are formed via an insulating layer. Forming a signal line so as to intersect the line and the auxiliary capacitance line, and arranging a pixel electrode in each lattice formed by intersecting the plurality of scanning lines and the plurality of signal lines. An active matrix liquid crystal display by forming a pixel electrode array substrate, disposing a counter substrate facing the pixel electrode array substrate, and holding a light modulation layer between the pixel electrode array substrate and the counter substrate; In the method of manufacturing a device, when forming a switching element between the signal line and the pixel electrode, the protrusion is formed in the same manner as an etching protection film used when forming the switching element. Method for manufacturing an active matrix type liquid crystal display device in the so formed. 21. The method of manufacturing an active matrix type liquid crystal display device according to claim 20, wherein the height of the protrusion is formed to be 2000 Å or more.