JPH11272813A - Semiconductor integrated circuit and contactless card - Google Patents

Abstract

PROBLEM TO BE SOLVED: To exclude malfunction of an internal logic circuit by generating a power-ON reset signal at proper timing in an environment wherein the source voltage is varied. SOLUTION: A power-ON reset circuit is constituted by including a diode 11 which receives the output voltage of a power circuit, a transistor 12 which is connected in series with this diode 11, and a logic gate 13 for deciding the logic of the series-connection node of the diode 11 and transistor 12. The series- connection circuit of the diode 11 and transistor 12 functions to check the level of a high-potential-side source voltage Vcc and excludes the assertion of a reset signal in the case that the high-potential-side source voltage Vcc is too low in level. Consequently, the reset signal is generated at proper timing in an environment wherein the source voltage is varied to exclude malfunction of the internal logic circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor integrated circuit,
Further, the present invention relates to an improved technique of a power-on reset circuit, and more particularly to an effective technique applied to a contactless card in which an external terminal is omitted and information can be exchanged with an external device in a non-contact state.

[0002]

2. Description of the Related Art An LSI for an IC card has an internal memory, which may store data with a high security level, for example, money information. For this reason, it is necessary to add a mechanism for preventing malfunctions in the IC card LSI.

[0003] In particular, when an IC card is made contactless and batteryless, and power is supplied to the contactless card by radio waves emitted from an external device, the power supply voltage thus supplied is provided. May greatly fluctuate, and it is essential to detect the power supply voltage level to prevent a malfunction caused by the power supply voltage fluctuation.

As a method of detecting the power supply voltage level, a method of comparing the power supply voltage with a reference voltage is generally used. However, when the reference voltage generation circuit is provided inside the LSI,
Since the power supply voltage of the reference voltage generation circuit itself also fluctuates, it is extremely difficult to form a circuit that generates a reference voltage of a predetermined level in such an environment.

As an example of a document describing a contactless card, a Nikkei microdevice, a special issue issued by Nikkei BP in August 1997, a day when a special feature IC card exceeds DRAM (p. 42-) There is.

[0006]

The inventor of the present application has studied the stabilization of the operation of a contactless card which is made contactless and batteryless and supplies power by radio waves emitted from an external device. However, when the power for operating the internal circuit in the contact card is supplied by radio waves from outside the card, the level of the power supply voltage thus supplied is extremely unstable, so the internal logic circuit Reset signal may be asserted to the internal logic circuit before the power supply voltage is raised to a level at which the device operates stably. Then, since the timing of resetting the internal logic circuit is not appropriate, the internal logic circuit does not operate normally. In this case, the internal storage information may be destroyed.

An object of the present invention is to provide a technique for eliminating a malfunction of an internal logic circuit by forming a power-on reset signal at an appropriate timing in an environment where a power supply voltage fluctuates.

[0008] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, an internal logic circuit (326) and a power supply circuit (3) for forming an operating voltage of the internal circuit.
21) and a power-on reset circuit (322) for power-on resetting the internal logic circuit based on the output voltage of the power supply circuit when a semiconductor integrated circuit is configured. Receiving a diode (11), a transistor (12) connected in series to the diode, and a logic gate (1) for determining the logic of a series connection node of the diode and the transistor.
And (3) the power-on reset circuit (322).
Is configured.

According to the above-mentioned means, as long as the high-potential-side power supply voltage is raised and the voltage between the terminals of the diode does not exceed a predetermined value, the potential of the series connection node is made substantially equal to the low-potential-side power supply voltage level. , The reset signal is not asserted. When the high-potential-side power supply voltage rises and the voltage between the terminals of the diode exceeds a predetermined value, a forward current flows through the diode, and the potential of the series connection node exceeds the logic threshold value of the logic gate. Is asserted. As described above, the series connection circuit of the diode and the transistor is a very simple circuit, and exhibits a function of checking the level of the high-potential-side power supply voltage. Eliminate asserts. This achieves the object of the present invention in that a power-on reset signal is formed at an appropriate timing even in an environment where the power supply voltage fluctuates, and a malfunction of the internal logic circuit is eliminated.

The power-on reset circuit includes a resistor coupled to an output terminal of the power supply circuit, a transistor connected in series with the resistor, and a logic gate for determining logic of a node connected in series with the resistor. Can be included.

[0013] A contactless card includes the semiconductor integrated circuit and an antenna coupled to an input terminal of the power supply circuit and receiving radio waves emitted from an external device in a non-contact state with the external device. can do.

[0014] A clock extraction circuit for extracting a clock signal used for the operation of the internal logic circuit from the signal captured via the antenna, and the internal logic circuit based on the signal captured via the antenna. The contactless card can be configured to include a data demodulation circuit for obtaining data processed by the circuit, and a data modulation circuit for modulating output data of the internal circuit and supplying the data to the antenna.

[0015]

FIG. 3 shows a contactless card according to the present invention.

The contactless card 31 has no external terminals, and allows various types of information to be exchanged with the external device in a non-contact state. The contactless card 31 shown in FIG. 3 has a built-in antenna 33 formed in a card shape and wound with conductive lines, and a semiconductor integrated circuit 32 coupled to the antenna 33.
And it is battery-less. That is, a radio wave emitted from an external device is received by the antenna 33, and a voltage induced by the antenna 33 is rectified and smoothed by an internal power supply circuit to obtain a power supply voltage for operation of the internal circuit.

FIG. 4 shows a configuration example of the semiconductor integrated circuit 32.

Although not particularly limited, the semiconductor integrated circuit 32 shown in FIG. 4 is formed on a single semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

A power supply circuit 321 is provided. The power supply circuit 321 rectifies a high frequency voltage (for example, 13.56 MHz) induced in the antenna 33, a regulator for lowering the rectified output, and Including a smoothing capacitor. The high-potential-side power supply voltage Vcc output from the power supply circuit 321 is connected to the power-on reset circuit 3
22, clock extraction circuit 323, data demodulation circuit 32
4. Data modulation circuit 325, control / arithmetic logic circuit 32
6 and the storage circuit 327. The power supply circuit 3
The low-potential-side power supply voltage Vss 21 is a ground potential common to the power-on reset circuit 322, the clock extraction circuit 323, the data demodulation circuit 324, the data modulation circuit 325, the control / arithmetic logic circuit 326, and the storage circuit 327. You.

The power-on reset circuit 322 detects the high-potential power supply voltage Vcc, and resets the control / arithmetic logic circuit 326 when the high-potential power supply voltage Vcc reaches a predetermined voltage level. Signal RST *
(* Means a low active signal) and outputs it to the control / operation logic circuit 326.

The clock extraction circuit 323 is connected to the antenna 33
A clock signal CLK is extracted from the high-frequency voltage induced in the circuit, and is output to the control / arithmetic logic circuit 326.

The data demodulation circuit 324 demodulates the high-frequency voltage induced in the antenna 33, thereby obtaining the reception data RD.
And outputs it to the control / arithmetic logic circuit 326.

The data modulation circuit 325 modulates the transmission data SD from the control / arithmetic logic circuit 326 and supplies it to the antenna 33.

The control / arithmetic logic circuit 326 outputs the clock signal C extracted by the clock extraction circuit 323.
The arithmetic processing of the output data RD from the data demodulation circuit 324 is performed in synchronization with LK. Further, in this arithmetic processing, information stored in the storage device 327 is referred to. The storage device 327 is a non-volatile memory such as a flash memory, and stores money information or personal information of a person who owns the card 31. Further, the result of the arithmetic processing of the control / arithmetic logic circuit 326 is transmitted data R if necessary.
D is output to the data modulation circuit 325, where it is modulated and transmitted to an external device via the antenna 323.

FIG. 1 shows a configuration example of the power-on reset circuit 322.

The diode 11 and an n-channel MOS transistor (depletion type) are connected in series, and the potential of the series connection node A is input to the inverter 13. The high potential side power supply voltage Vcc is applied to the anode of the diode 11. n-channel type M
The gate electrode and the drain electrode of the OS transistor 12 are coupled. The source electrode of the n-channel MOS transistor 12 is set at the high potential side power supply voltage Vcc level.
A high-potential-side power supply voltage V
cc and the low-potential-side power supply voltage Vss. The output signal of the inverter 13 is supplied to the control / arithmetic logic circuit 326 as a reset signal RST *.

FIG. 2 is a characteristic diagram of the power-on reset circuit 322 shown in FIG.

When the high-potential-side power supply voltage Vcc is near zero volt, no sufficient forward voltage is applied to the diode 11, so that no current flows through the diode 11. For this reason,
The potential of the series connection node A is at the low potential side power supply voltage Vss level, and the output terminal of the inverter 13 is at the high level.

The high-potential-side power supply voltage Vcc further rises,
When the voltage between the terminals of the diode 11 exceeds 0.8 volts, a forward current starts to flow through the diode 11. Then, n
The resistance of the channel type MOS transistor 12 raises the potential of the series connection node A, and when it reaches the logic threshold of the inverter 13, the output logic of the inverter 13 is inverted and the reset signal RST * becomes Asserted low. Thereby, the control / arithmetic logic circuit 326 is reset and a predetermined control / arithmetic operation is started.

Here, the control / arithmetic logic circuit 326 includes:
It includes control logic for sequence control. If the high-potential-side power supply voltage Vcc supplied thereto is too low, normal logic operation cannot be performed. In particular, a logic circuit in which MOS transistors are coupled in a plurality of stages does not operate properly unless a higher power supply voltage is supplied as compared with a circuit in which MOS transistors are not coupled in a plurality of stages. Therefore, when the reset signal RST * is asserted to a low level in a state where the electromotive force at the antenna 33 does not become sufficiently high, such as immediately after the contactless card 31 is set in an external device, the control / operation Logic circuit 326
Although the high-potential-side power supply voltage Vcc is not raised to a level at which normal logic operation can be performed, the control / operation logic circuit 32 is reset by the reset signal RST *.
6, the control / arithmetic logic circuit 326 must be erroneously operated.

For example, when a resistor is provided in place of the diode 11 shown in FIG. 1 and a capacitor is provided in place of the n-channel MOS transistor 12, the terminal voltage of the capacitor gradually increases due to the time constant of CR. When this exceeds the logic threshold value of the inverter 13, the output logic of the inverter is inverted. Since the logic threshold value of the inverter 13 is set to approximately 1/2 of the high-potential-side power supply voltage Vcc, the output logic of the inverter may be inverted even when the high-potential-side power supply voltage Vcc is not sufficiently high. . Then, as described above, the reset signal RST * is asserted in a state where the high-potential-side power supply voltage Vcc does not rise to a level at which the control / operation logic circuit 326 can perform a normal logic operation, and the control / operation operation is performed. Since the operation of the logic circuit 326 is started, the control
The arithmetic logic circuit 326 malfunctions.

On the other hand, in the configuration shown in FIG.
Due to the nature of the diode 11, no current flows through the diode 11 unless the terminal voltage of the diode 11 reaches approximately 0.8 volts, so that the potential of the series connection node A does not rise and the logic inversion of the inverter is prevented. Is done. When the high-potential-side power supply voltage Vcc is increased and the voltage across the terminals of the diode 11 exceeds 0.8 volts, a forward current flows through the diode 11 and the potential of the series connection node A lowers the logical threshold value of the inverter 13. The inverter 13
Is inverted, and the reset signal RST * is asserted. In this state, the high-potential-side power supply voltage Vcc is sufficiently raised, and the control / operation logic circuit 326 operates normally.

As described above, although the series connection circuit of the diode 11 and the MOS transistor 12 has a simple structure itself, it performs the function of checking the level of the high-potential-side power supply voltage Vcc so that the high-potential-side power supply voltage Vcc is set to a predetermined value. Since the reset signal RST * is not asserted unless the value exceeds the value, the control / arithmetic logic circuit 32 is provided by optimizing the assertion timing of the reset signal RST *.
6 can be eliminated.

According to the above example, the following functions and effects can be obtained.

When the high-potential-side power supply voltage Vcc rises and the voltage between the terminals of the diode 11 exceeds 0.8 volts, a forward current starts to flow through the diode 11, and the n-channel type
The resistance of the S transistor 12 raises the potential of the series connection node A, and when it reaches the logic threshold value of the inverter 13, the output logic of the inverter 13 is inverted and the reset signal RST * goes low. Asserted. That is, unless the high-potential-side power supply voltage Vcc is raised and the voltage between the terminals of the diode 11 does not exceed 0.8 volts, the potential of the series connection node A is substantially equal to the low-potential-side power supply voltage Vss level. Signal R
ST * is never asserted low. When the high-potential-side power supply voltage Vcc is increased and the voltage between the terminals of the diode 11 exceeds 0.8 volts, a forward current flows through the diode 11 and the potential of the series connection node A lowers the logical threshold value of the inverter 13. The inverter 13
Is inverted, and the reset signal RST * is asserted. In this state, the high-potential-side power supply voltage Vcc is sufficiently raised, and the control / arithmetic logic circuit 326 operates normally.

Although the invention made by the present inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

For example, a resistor may be provided instead of the diode 11. The high-potential-side power supply voltage Vcc is increased, the drain-source voltage Vds of the n-channel MOS transistor 12 is increased, and the MOS transistor 12 is saturated. The voltage Vcc is divided so that the series connection node A has a predetermined voltage. When the high-potential-side power supply voltage Vcc is further increased and the potential of the series connection node A exceeds the logical threshold value of the inverter 13, the output logic of the inverter 13 is inverted, and the reset signal RST * is asserted. In this state, the high-potential-side power supply voltage Vcc is sufficiently raised, and the control / arithmetic logic circuit 326 operates normally, so that the same operation and effect as in the case shown in FIG. 1 can be obtained.

In the above description, the case where the invention made by the present inventor is mainly applied to a contactless card, which is the field of application as the background, has been described. However, the present invention is not limited to this case. The present invention can be widely applied to various semiconductor integrated circuits that require resetting and devices including the same.

[0039]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the high-potential-side power supply voltage is increased,
As long as the voltage between the terminals of the diode does not exceed a predetermined value, the potential of the series connection node is made substantially equal to the low potential side power supply voltage level. Therefore, the reset signal is asserted in a state where the high potential side power supply voltage Vcc is very low. Never. When the high-potential-side power supply voltage rises and the voltage between the terminals of the diode exceeds a predetermined value, a forward current flows through the diode, and the potential of the series connection node exceeds the logic threshold of the logic gate. Is inverted, and the reset signal is asserted. In this state, the high-potential-side power supply voltage is sufficiently raised, and the control / arithmetic logic circuit operates normally. Thus, a malfunction of the internal logic circuit can be eliminated by forming the power-on reset signal at an appropriate timing in an environment where the power supply voltage fluctuates.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration example of a power-on reset circuit included in a contactless card according to the present invention.

FIG. 2 is a characteristic diagram of the circuit shown in FIG.

FIG. 3 is an explanatory diagram of an overall configuration example of the contactless card.

FIG. 4 is a block diagram illustrating a configuration example of a semiconductor integrated circuit included in the contactless card.

[Explanation of symbols]

 REFERENCE SIGNS LIST 11 diode 12 n-channel MOS transistor 13 inverter 31 contactless card 32 semiconductor integrated circuit 33 antenna 321 power supply circuit 322 power-on reset circuit 323 clock extraction circuit 324 data demodulation circuit 325 data modulation circuit 326 control / arithmetic logic circuit 327 storage circuit

Claims (4)

[Claims] An internal logic circuit; a power supply circuit for forming an operating voltage of the internal circuit; and a power-on reset circuit for power-on resetting the internal logic circuit based on an output voltage of the power supply circuit. Wherein the power-on reset circuit determines a logic of a diode receiving the output voltage of the power supply circuit, a transistor connected in series to the diode, and a serial connection node of the diode and the transistor. And a logic gate for supplying the output signal of the logic gate to the internal logic circuit as a power-on reset signal thereof. 2. An internal logic circuit, a power supply circuit for forming an operating voltage of the internal circuit, and a power-on reset circuit for power-on resetting the internal logic circuit based on an output voltage of the power supply circuit Wherein the power-on reset circuit includes a resistor coupled to an output terminal of the power supply circuit, a transistor connected in series to the resistor, and a logic of a series connection node of the resistor and the transistor. A logic gate for discriminating, wherein an output signal of the logic gate is supplied to the internal logic circuit as a power-on reset signal thereof. 3. A semiconductor integrated circuit according to claim 1, further comprising an antenna coupled to an input terminal of said power supply circuit for receiving radio waves emitted from an external device in a non-contact state with said external device. And a contactless card formed in a card shape. 4. A clock extraction circuit for extracting a clock signal used for the operation of the internal logic circuit from a signal captured via the antenna, and a clock extraction circuit for extracting a clock signal used via the antenna. 4. The contactless card according to claim 3, further comprising a data demodulation circuit for obtaining data processed by an internal logic circuit, and a data modulation circuit for modulating output data of the internal circuit and supplying the data to the antenna.