JP2004078898A - Ic card - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a malfunction, etc., due to a short circuit between power terminals for non-contact operation and to vastly enhance security. <P>SOLUTION: In a dual way type IC card using both non-contact/contact operations, a transistor for separation is provided between a power supply voltage terminal VCC and a contact power supply circuit 15. The non-contact/contact determination switching part 6 turns the transistor OFF and separates the power supply voltage terminal VCC from the contact power supply circuit 15 in detecting that the IC card is the non-contact operation. Thus, when the power supply voltage terminal VCC and a ground terminal GND are short-circuited for the non-contact operation, the malfunctions of the IC card, etc. are surely prevented. Since the power supply voltage terminal VCC becomes a reference potential VSS level in this case, voltage monitor of the power supply voltage terminal VCC is prevented from malfunctions and the security of the IC card is vastly enhanced. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an IC card, and more particularly, to a technology that is effective when applied to improvement of reliability in a dual-way type IC card.
[0002]
[Prior art]
In recent years, IC cards having functions such as credit cards and telephone cards have become widespread. In this IC card, a CPU and a memory are mounted on a card having a shape similar to a magnetic card, and read / write of the memory is managed by the CPU. It has functions and large storage capacity.
[0003]
In addition, as one of information transmission methods with an external device, for example, a non-contact type in which information is transmitted by an information transmission medium such as a contact type having a mechanical coupling means with the external device or an electric wave. Type and contact / non-contact type, so-called dual-way type.
[0004]
In the dual-way type IC card, the power supplied from the contact-type power input terminal and the power supplied from the non-contact type radio wave form a common power line and are supplied to an internal power regulator.
[0005]
In this case, since the power supply line is common, the power supply voltage is also applied to the power supply terminal used during the contact operation during the non-contact operation of the IC card, and the power supply voltage (VDD) terminal is connected to the power supply voltage (VDD) terminal for some reason such as metal contact. When the ground (GND) terminal is short-circuited, malfunction may occur.
[0006]
As a technique for preventing the IC card from malfunctioning due to such a short circuit between the power supply voltage terminal and the ground terminal, for example, as shown in Japanese Patent Application Laid-Open No. 2000-148961, a diode is provided on the power supply line VDD side of the power supply line. It is known to prevent the current from flowing backward from the power supply voltage terminal to the ground terminal.
[0007]
[Problems to be solved by the invention]
However, the present inventor has found that the reverse current prevention technology in the IC card has the following problems.
[0008]
That is, when a diode for preventing reverse current is inserted into the power supply line of the IC card, the power supply voltage supplied to the power supply terminal during the contact operation drops due to the forward voltage (VF) of the diode, and the power supply operation range is reduced. There is a possibility that the size of the IC card becomes narrow and the reliability of the IC card is impaired.
[0009]
Further, the dual-way type IC card has a problem that a change in the power supplied from the antenna during the non-contact operation is monitored from the power supply terminal. The monitoring of the power change cannot be completely prevented even if a diode is inserted into the power supply line. By reading the power change, the internal operation of the semiconductor integrated circuit device of the IC card is analyzed, and the security hole is detected. There is a risk that it will.
[0010]
An object of the present invention is to provide an IC card capable of preventing a malfunction due to a short circuit between power supply terminals during a non-contact operation, and preventing a change in power from being monitored to greatly improve security.
[0011]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0012]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
1. An operation mode detection unit that detects a non-contact operation and outputs a control signal, based on a control signal of the operation mode detection unit. It is provided with separation switch means for separating the contact power supply terminal from the internal power supply.
[0013]
An outline of another invention of the present application will be briefly described.
2. In the first aspect, the contact power supply terminal is at least one of a power supply voltage terminal and a reference potential terminal.
3. In the above-mentioned item (1) or (2), the separation switch means has a configuration in which two P-channel MOS transistors are connected in series.
4. In any one of the above items 1 to 3, the separation switch means is provided near the contact power supply terminal.
5. In any one of the above items 1 to 4, the transistor size of the P-channel MOS transistor is larger than that of a logic MOS transistor.
6. In any one of the above items 1 to 5, the operation mode detection section rectifies a received radio wave to generate a DC voltage, and detects the DC voltage to determine a non-contact operation.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0015]
FIG. 1 is an explanatory diagram of an IC card according to an embodiment of the present invention, FIG. 2 is a block diagram of a semiconductor integrated circuit device built in the IC card of FIG. 1, and FIG. 3 is a semiconductor integrated circuit device of FIG. FIG. 4 is a block diagram of a non-contact RF unit provided in the non-contact RF unit of FIG. 3, FIG. 4 is a configuration explanatory view of a non-contact / contact determination / switching unit provided in the non-contact RF unit of FIG. 3, and FIG. FIG. 6 is an explanatory diagram of a chip layout in the semiconductor integrated circuit device built in the IC card of FIG. 1, and FIG. 7 is a cross section of a transistor provided in the non-contact RF section of FIG. 8 and FIG. 8 are equivalent circuit diagrams of the transistor of FIG. 7, and FIG. 9 is an explanatory diagram comparing the device size with the transistor logic P-channel MOS transistor of FIG.
[0016]
In the present embodiment, the IC card 1 is composed of a so-called dual interface IC card which is both a contact type and a non-contact type. As shown in FIG. 1, the IC card 1 has a semiconductor integrated circuit device 3 embedded in a plastic card 2 having the same shape as a magnetic card.
[0017]
In the vicinity of the outer peripheral portion of the plastic card 2, a coil 4 serving as an antenna is embedded. Both ends of the coil 4 are connected to connection terminals LA and LB (FIG. 2) of the semiconductor integrated circuit device 2.
[0018]
The coil 4 receives electric waves from the card terminal and performs power supply and information communication when the IC card 1 is in a non-contact operation.
[0019]
A plurality of external terminals 3a of the semiconductor integrated circuit device 3 are provided on the surface of the plastic card 2 so as to be exposed. These external terminals 3a perform power supply, information communication, and the like by mechanically contacting the external terminals of the card terminal when the IC card 1 performs a contact operation.
[0020]
Further, as shown in FIG. 2, the semiconductor integrated circuit device 3 includes a clock generation circuit 5, a non-contact / contact determination / switch unit (operation mode detection unit) 6, a non-contact RF unit 7, a non-contact RAM 8, a CPU 9, a ROM 10, and the like. , A RAM 11, an EEPROM 12, an I / O port 13, and the like.
[0021]
The semiconductor integrated circuit device 3 includes, as external terminals 3a, a clock terminal CLK, a power supply voltage terminal (contact power supply terminal) VCC, a reset terminal RES, a ground terminal (contact power supply terminal, reference potential terminal) GND, and an input / output terminal I / O1. , I / O2 are provided.
[0022]
An external clock signal is supplied to the clock terminal CLK. A power supply voltage is supplied to the power supply voltage terminal VCC, and a reset signal is input to the reset terminal RES. The reference potential VSS is connected to the ground terminal GND, and data is input / output to the input / output terminals I / O1 and I / O2.
[0023]
The clock generation circuit 5 generates an internal clock signal from the clock signal supplied from the clock terminal CLK. The non-contact / contact determining / switching unit 6 determines whether or not there is a voltage in the coil 4 during operation of the IC card 1 to determine whether the operation is a contact operation or a non-contact operation, and switches an internal clock signal. And when the IC card 1 is in a non-contact operation, the power supply voltage terminal VCC is electrically disconnected.
[0024]
The non-contact RF section 7 is a high-frequency interface function used when the IC card 1 performs a non-contact operation, and both ends of the coil 4 are connected via connection terminals LA and LB.
[0025]
Further, the non-contact RAM 8, the CPU 9, the ROM 10, the RAM 11, and the EEPROM 12 are mutually connected by the internal bus B. The non-contact RAM 8 is a volatile memory, and temporarily stores data input and output from the IC card 1 during the non-contact operation of the IC card 1.
[0026]
The CPU 9 controls all controls in the IC card based on a program stored in the ROM 10. The ROM 10 is a read-only memory, and stores a control program of the IC card 1 and the like.
[0027]
The RAM 11 is formed of a volatile memory, and temporarily stores data input / output from / to the IC card 1 when the IC card 1 makes a contact operation. The EEPROM 12 is an electrically erasable / rewritable memory, and stores data temporarily stored in the non-contact RAM 8 or the RAM 11. The I / O port 13 is a port for inputting and outputting data from the card terminal.
[0028]
The configuration of the non-contact RF unit 7 will be described with reference to the block diagram of FIG.
[0029]
The non-contact RF unit 7 includes a non-contact power supply circuit 14, a contact power supply circuit 15, an output voltage determination circuit 16, a reference voltage power supply 17, an ASK demodulation circuit 18, an ASK modulation circuit 19, and a clock reproduction circuit 20.
[0030]
The non-contact power supply circuit 14 is a power supply circuit including a rectifier circuit, a regulator, and the like, and generates an internal power supply voltage serving as an operation voltage of the IC card 1. The coil 4 extracts electric power from the radio wave output from the card terminal and supplies the electric power to the non-contact power supply circuit 14.
[0031]
The contact power supply circuit 15 includes a regulator or the like, and generates an internal power supply voltage from a power supply voltage supplied from the power supply voltage terminal VCC when the IC card 1 performs a contact operation. The output voltage determination circuit 16 detects the voltage level of the internal power supply voltage, outputs a reset signal when the voltage level reaches a certain level, and resets the semiconductor integrated circuit device 3.
[0032]
The reference voltage power supply 17 includes, for example, a band gap circuit, generates a reference voltage from an internal power supply voltage, and supplies the reference voltage to the non-contact power supply circuit 14, the contact power supply circuit 15, the output voltage determination circuit 16, the ASK demodulation circuit 18, and the like. .
[0033]
The ASK demodulation circuit 18 demodulates the data of an ASK (Amplitude Shift Keying) signal in which the amplitude of the carrier received by the coil 4 is changed according to the input digital signal, and outputs the demodulated data to the non-contact RAM 8.
[0034]
The ASK modulation circuit 19 performs ASK modulation on the data output from the non-contact RAM 8 and transmits the data from the coil 4. The clock recovery circuit 20 generates an internal clock signal of about 13.56 MHz from the clock signal received by the coil 4 and outputs the generated internal clock signal as an operation clock signal of the semiconductor integrated circuit device 3.
[0035]
The connection configuration of the non-contact / contact determination / switching unit 6 will be described with reference to FIG.
[0036]
The non-contact / contact determination / switching unit 6 includes diodes D1 and D2, resistors R1 to R4, a capacitor C1, P-channel MOS transistors (separation switch means) T1 and T2, inverters Iv1 and Iv2, a NAND circuit ND, and a NOT circuit. The circuit includes OR circuits NR1 and NR2, a voltage detection circuit DK, delay circuits DL1 to DL3, and a determination latch HR.
[0037]
A connection terminal LA to which one end of the coil 4 is connected is connected to an anode of the diode D1 and one input portion of the non-contact power supply circuit 14, respectively. The connection terminal LB to which the other end of the coil 4 is connected is connected to the anode of the diode D2 and the other input portion of the non-contact power supply circuit 14, respectively.
[0038]
The cathodes of the diodes D1 and D2 are connected to one connection of the resistor R2 and the input of the inverter Iv1, and these diodes D1 and D2 rectify and output the power taken in from the coil 4.
[0039]
The output of the non-contact power supply circuit 14 is connected to one connection of the resistor R 1, the other connection of the transistor T 2, the input of the voltage detection circuit DK, and the input of the contact power supply 15. The non-contact power supply circuit 14 rectifies, stabilizes, and outputs the power taken from the coil 4.
[0040]
The other connection of the resistor R1 is connected to one connection of the capacitor C1 and the input of the delay circuit DL1, and the other connection of the capacitor C1 is connected to the reference potential VSS. . A time constant circuit is formed by the resistor R1 and the capacitor C1.
[0041]
The other input of the NAND circuit ND is connected to the output of the delay circuit DL1, and the voltage detection signal of the voltage detection circuit DK is input to one connection of the NAND circuit ND. Connected so that
[0042]
The output of the NAND circuit ND is connected to the input of the delay circuit DL2 and the reset terminal of the decision latch HR composed of a flip-flop. The input of the delay circuit DL3 and the other input of the NOR circuit NR1 are connected to the output of the delay circuit DL2, and one input of the NOR circuit NR1 is connected to the delay circuit DL2. The output of DL3 is connected.
[0043]
The output terminal of the NOR circuit NR1 is connected to the clock terminal of the determination latch HR. Then, a signal output from the output unit of the determination latch HR is a determination signal of the non-contact / contact determination / switch unit 6. The other input of the NOR circuit NR2 is connected to the output of the determination latch HR.
[0044]
The power supply voltage terminal VCC is connected to one connection of the resistor R3 and one connection of the transistor T1. One connection of the transistor T2 is connected to the other connection of the transistor T1, and one connection of the resistor R4 and the output of the inverter Iv2 are connected to the gates of the transistors T1 and T2, respectively. Have been.
[0045]
These transistors T1 and T2 are switches for separating the power supply voltage terminal VCC from an internal power supply line such as the contact power supply circuit 15. The transistors T1 and T2 are turned on when the IC card 1 performs a contact operation, and when the IC card 1 is in a non-contact operation, the transistors T1 and T2 are turned off and the power supply voltage terminal VCC and the internal power supply line are connected as described above. Is electrically disconnected.
[0046]
As a result, the power supply voltage terminal VCC is fixed at the reference potential VSS level by the resistor R3.
[0047]
A reference potential VSS is connected to the other connection of the resistors R3 and R4, and an output of the NOR circuit NR2 is connected to an input of the inverter Iv2.
[0048]
The other connection of the resistor R2 is connected to the reference potential VSS, and the output of the inverter Iv1 is connected to the data terminal of the decision latch HR and one input of the NOR circuit NR2. I have.
[0049]
Next, the operation of the non-contact / contact determination / switch unit 6 in the present embodiment will be described with reference to the timing chart of FIG.
[0050]
In FIG. 5, from the top to the bottom, the primary power supply (node a in FIG. 4) output from the non-contact power supply circuit 14, the determination detection voltage rectified by the diodes D1 and D2 (node b in FIG. 4), the delay The startup detection voltage (node c in FIG. 4) input to the circuit DL1, the reset signal (node d in FIG. 4) output from the NAND circuit ND, and the latch pulse output from the NOR circuit NR1 (FIG. 4) , A determination signal (node f in FIG. 4) output from the determination latch HR, an output signal (node g in FIG. 4) output from the inverter Iv1, and a control signal (FIG. 4) for driving the transistors T1 and T2. At the node h) of FIG.
[0051]
In FIG. 5, the signal timing during the non-contact operation is indicated by a solid line, and the signal timing during the contact operation is indicated by a dotted line. Here, a non-contact operation of the IC card 1 will be described.
[0052]
First, when the coil 4 receives the radio wave from the card terminal, the primary power is output from the non-contact power supply circuit 14, and the determination detection voltages output from the diodes D1 and D2 similarly rise to the Hi level.
[0053]
At this time, a reset signal (Hi level) is output from the NAND circuit ND, and the determination latch HR is reset. When the activation detection voltage (node c) attains the Hi level with a certain time constant, the delay circuit DL1 delays the Hi level signal by a certain time and outputs it. The NAND circuit ND receives the Hi-level signal output from the delay circuit DL1, and turns to a Lo-level signal.
[0054]
Further, since the determination detection voltage is at the Hi level as described above, the signal (node g) output from the inverter Iv1 is at the Lo level, and the control signal output from the inverter Iv2 is at the Hi level.
[0055]
Then, the reset signal output from the NAND circuit ND is delayed by a certain time by the delay circuit DL2, is input to the other input part of the NOR circuit NR1, and the signal output from the delay circuit DL2 is delayed. The signal is further delayed by the circuit DL3 and input to one input of the NOR circuit NR1.
[0056]
The NOR circuit NR1 outputs a latch pulse during the delay time between the delay circuits DL2 and DL3. Based on the latch pulse, the determination latch HR latches the output signal (node g) of the inverter Iv1. Output as a determination signal (node f). Here, since the non-contact / contact determination / switching unit 6 uses the DC voltage rectified by the diodes D1 and D2 as the detection signal, the detection time can be shortened.
[0057]
At this time, since the output of the inverter Iv1 is at the Lo level and the determination signal is also at the Lo level, a Hi-level signal is output from the output section (node h) of the inverter Iv2, and the transistors T1 and T2 are turned off. Thus, the power supply voltage terminal VCC is at the level of the reference potential VSS.
[0058]
Therefore, even if the power supply voltage terminal VCC and the ground terminal GND are short-circuited, a reverse current is prevented from flowing.
[0059]
Further, a chip layout of the semiconductor integrated circuit device 3 will be described with reference to FIG.
[0060]
In FIG. 6, a non-contact RF section 7 is located above the semiconductor chip CH, and connection terminals LA and LB are provided above the non-contact RF section 7, respectively. Further, a non-contact RAM 8 and a non-contact ROM 10 a which is a part of the ROM 10 are provided below the non-contact RF unit 7.
[0061]
In the shaded area in the figure, the logic including the ROM 10, the RAM 11, the EEPROM 12, the CPU 9, the clock generation circuit 5, and the non-contact / contact determination / switching unit 6 includes the non-contact RAM 8 and the non-contact ROM 10a. A circuit is configured.
[0062]
Around the semiconductor chip CH, there are a clock terminal CLK, a power supply voltage terminal (contact power supply terminal) VCC, a reset terminal RES, a ground terminal (contact power supply terminal, reference potential terminal) GND, and input / output terminals I / O1 and I / O2. Is provided.
[0063]
Further, by providing the transistors T1 and T2 near the power supply voltage terminal VCC, the impedance can be reduced, and the voltage drop can be suppressed.
[0064]
Here, a cross-sectional view of the transistors T1 and T2 is shown in FIG.
[0065]
In FIG. 7, for example, an N-well Wn on HK is formed on a semiconductor substrate HK made of a P-type silicon single crystal substrate, and transistors T1 and T2 are formed on this N-well Wn.
[0066]
As shown in FIG. 8, the transistors T1 and T2 have parasitic diodes Dk1 to Dk4 formed on the semiconductor substrate HK. By connecting the transistors T1 and T2 in series, the parasitic diode Dk1 of the transistor T1 is formed. , Dk2 are connected in the forward direction and the reverse direction, respectively.
[0067]
Further, the parasitic diodes Dk3 and Dk4 of the transistor T2 are similarly connected in the forward and reverse directions. Thus, it is possible to prevent a voltage from being generated at the power supply voltage terminal VCC via the parasitic diodes Dk1 to Dk4.
[0068]
FIG. 9 is an explanatory diagram comparing the device sizes of the transistor T1 (, T2) and a general logic P-channel MOS transistor Tp.
[0069]
As shown in the figure, the transistor T1 (, T2) is, for example, about 700 times or more in area ratio as compared with the transistor Tp in order to reduce the ON resistance. In this case, n P-channel MOS transistors t are connected in parallel to form one transistor T1 (, T2).
[0070]
Thus, according to the present embodiment, during the non-contact operation of the IC card 1, the transistors T1 and T2 are turned off, and the power supply voltage terminal VCC is at the level of the reference potential VSS, so that the power supply voltage terminal VCC and the ground terminal GND are connected to each other. , The malfunction of the IC card 1 can be reliably prevented.
[0071]
Further, at the time of the non-contact operation of the IC card 1, the power supply voltage terminal VCC is at the reference potential VSS level, so that the analysis of the internal operation by monitoring the power supply voltage terminal VCC can be prevented. Security can be greatly improved.
[0072]
As described above, the invention made by the inventor has been specifically described based on the embodiment of the invention. However, the invention is not limited to the embodiment, and can be variously modified without departing from the gist of the invention. Needless to say, there is.
[0073]
For example, in the above-described embodiment, a case has been described in which the transistors for fixing the power supply voltage terminal to the reference potential VSS level are formed of P-channel MOS transistors, but these transistors may be N-channel MOS transistors.
[0074]
In this case, as shown in FIG. 10, the non-contact / contact determination / switching unit 6 is provided with an N-channel MOS transistor (separation switch means) T3 instead of the transistors T1 and T2 (FIG. 4). The configuration is such that a booster circuit 21 for driving T3 is newly provided.
[0075]
By using the N-channel MOS transistor T3, the influence of the parasitic diode can be eliminated.
[0076]
The power supply voltage terminal VCC is connected to one connection of the transistor T3, and the other connection of the transistor T3 is connected to the output of the non-contact power supply circuit 14. The gate of the transistor T3 is connected to a reference potential via a resistor R4.
[0077]
The gate of the transistor T3 is connected so that the boosted voltage generated by the booster circuit 21 is input, and the control terminal of the booster circuit 21 is connected to the output of the NOR circuit NR2. .
[0078]
The booster circuit 21 starts the boosting operation based on the signal output from the output unit of the NOR circuit NR2, and outputs the generated boosted voltage to the gate of the transistor T3.
[0079]
Further, other configurations and connections in the non-contact / contact determination / switching unit 6 are the same as those in FIG.
[0080]
Therefore, by using the N-channel MOS transistor T3, the ON resistance can be reduced as compared with the transistors T1 and T2 (FIG. 4).
[0081]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0082]
(1) By providing the separation switch means, even if the contact power supply terminal is short-circuited during the non-contact operation, malfunction of the IC card can be prevented.
[0083]
(2) Further, by separating the contact power supply terminal and the internal power supply during the non-contact operation, the security of the IC card during the non-contact operation can be greatly improved.
[0084]
(3) Further, according to the above (1) and (2), the reliability of the IC card can be improved.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of an IC card according to an embodiment of the present invention.
FIG. 2 is a block diagram of a semiconductor integrated circuit device built in the IC card of FIG. 1;
FIG. 3 is a block diagram of a non-contact RF unit provided in the semiconductor integrated circuit device of FIG. 2;
FIG. 4 is a configuration explanatory diagram of a non-contact / contact determination / switching unit provided in the non-contact RF unit of FIG. 3;
FIG. 5 is a signal timing chart of each unit in the non-contact RF unit of FIG. 4;
6 is an explanatory diagram of a chip layout in a semiconductor integrated circuit device built in the IC card of FIG. 1;
FIG. 7 is a cross-sectional view of a transistor provided in a non-contact RF section in FIG.
FIG. 8 is an equivalent circuit diagram of the transistor in FIG. 7;
9 is an explanatory diagram comparing the device size with the transistor logic P-channel MOS transistor of FIG. 7;
FIG. 10 is a block diagram of a non-contact RF unit provided in a semiconductor integrated circuit device built in an IC card according to another embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 IC card 2 Plastic card 3 Semiconductor integrated circuit device 3a External terminal 4 Coil 5 Clock generation circuit 6 Non-contact / contact determination / switching unit (operation mode detecting unit)
7 Non-contact RF section 8 Non-contact RAM
9 CPU
10 ROM
10a Non-contact ROM
11 RAM
12 EEPROM
13 I / O port 14 Non-contact power supply circuit 15 Contact power supply circuit 16 Output voltage determination circuit 17 Reference voltage power supply 18 ASK demodulation circuit 19 ASK modulation circuit 20 Clock regeneration circuits LA and LB Connection terminal CLK Clock terminal VCC Power supply voltage terminal (contact power supply Terminal)
RES Reset terminal GND Ground terminal (contact power supply terminal, reference potential terminal)
I / O1, I / O2 I / O terminals D1, D2 Diodes R1-R4 Resistance C1, Capacitors T1, T2 Transistor (separation switch means)
Iv1, Iv2 Inverter ND NAND circuit NR1, NR2 NAND circuit DK Voltage detection circuits DL1 to DL3 Delay circuit HR Judgment latches Dk1 to Dk4 Parasitic diode B Internal bus

Claims (6)

A dual-way IC card that combines a contact type and a non-contact type,
An operation mode detection unit that detects a non-contact operation and outputs a control signal,
An IC card comprising: a separation switch for separating a contact power supply terminal from an internal power supply based on a control signal of the operation mode detection unit. 2. The IC card according to claim 1, wherein the contact power supply terminal is at least one of a power supply voltage terminal to which a power supply voltage is supplied and a reference potential terminal to which a reference potential is connected. 3. The IC card according to claim 1, wherein said separation switch means has a configuration in which two P-channel MOS transistors are connected in series. 4. The IC card according to claim 1, wherein said separation switch means is provided near said contact power supply terminal. 5. The IC card according to claim 1, wherein a transistor size of the P-channel MOS transistor is larger than a logic MOS transistor. 6. 6. The IC card according to claim 1, wherein the operation mode detection unit rectifies a received radio wave to generate a DC voltage, and determines the non-contact operation by detecting the DC voltage. 7. An IC card, characterized in that:

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