JPH1127080A - Ceramic device wafer and its production - Google Patents

Ceramic device wafer and its production

Info

Publication number
JPH1127080A
JPH1127080A JP19522897A JP19522897A JPH1127080A JP H1127080 A JPH1127080 A JP H1127080A JP 19522897 A JP19522897 A JP 19522897A JP 19522897 A JP19522897 A JP 19522897A JP H1127080 A JPH1127080 A JP H1127080A
Authority
JP
Japan
Prior art keywords
resin layer
device wafer
ceramic
characteristic function
cover resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP19522897A
Other languages
Japanese (ja)
Inventor
Takaaki Domon
孝彰 土門
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP19522897A priority Critical patent/JPH1127080A/en
Publication of JPH1127080A publication Critical patent/JPH1127080A/en
Withdrawn legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a ceramic device wafer and its production method which can improve the quality and yield of a chip intermediate by contriving the print pattern of a cover resin layer when a chip ceramic electronic parts is produced. SOLUTION: When plural electrical characteristic function parts Q are formed in print patterns on the surface of a ceramic substrate 1 to serve as the individual elements, the print patterns of cover resin layers 6A covering the parts Q are separated from each other for each part Q and also not extended to a cutting part where the parts Q are cut into the individual elements. Then the formed layers 6A are separated from each other for each part Q.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、高周波レゾネータ
等のチップセラミック電子部品を製造するのに適用され
るセラミックデバイスウェハー及びその製造方法に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic device wafer used for manufacturing chip ceramic electronic components such as a high-frequency resonator, and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来、高周波レゾネータ等のチップセラ
ミック電子部品に適用するセラミックデバイスウェハー
の製造は、図10の一例で示すように、一対の貫通孔2
を複数設けた同図(A)のセラミック基板1(大板)に
電極形成工程で銅膜の電極3をスパッタリングで同図
(B)の如く形成するとともに同図(C)のように貫通
孔2の孔埋めを行い、前記貫通孔2を除く所定領域に同
図(D)のように印刷にてレジスト皮膜4を形成し、そ
の上面に更に、同図(E)の如く前記レジスト皮膜を取
り出す抜き孔5を設けた熱硬化性カバー樹脂層6を印刷
形成し、前記レジスト皮膜4を抜き孔5より除去した後
に、全体を被覆保護する封止樹脂層7を重印刷すると共
に前記抜き孔5を充填して硬化させることにより行って
おり、これにより図11(A)の如き電極3が基板1を
挟んで対向している部分に空洞部8を形成したセラミッ
クデバイスウェハーを得ている(図11中、図10と同
一部分に同一符号を付した。)。
2. Description of the Related Art Conventionally, a ceramic device wafer applied to a chip ceramic electronic component such as a high-frequency resonator is manufactured by a pair of through holes 2 as shown in an example of FIG.
In the electrode forming step, a copper film electrode 3 is formed on the ceramic substrate 1 (large plate) of FIG. 1A by sputtering as shown in FIG. 2B and through holes are formed as shown in FIG. 2, a resist film 4 is formed by printing as shown in FIG. 4D in a predetermined area excluding the through hole 2, and the resist film 4 is further formed on the upper surface thereof as shown in FIG. A thermosetting cover resin layer 6 provided with a hole 5 to be taken out is formed by printing, and after removing the resist film 4 from the hole 5, a sealing resin layer 7 for covering and protecting the whole is overprinted. This is performed by filling and curing, thereby obtaining a ceramic device wafer in which a cavity 8 is formed in a portion where the electrodes 3 are opposed to each other across the substrate 1 as shown in FIG. In FIG. 11, the same parts as those in FIG. It was.).

【0003】そして、図10(F)の切断工程におい
て、封止樹脂層7等の硬化後にダイシングソー(切断装
置)で、セラミックデバイスウェハーを略4.3mm×
3.0mmの大きさのチップ素子(チップセラミック電子
部品)10へ切断する。
In the cutting step shown in FIG. 10F, after the sealing resin layer 7 and the like are hardened, the ceramic device wafer is cut into approximately 4.3 mm × by a dicing saw (cutting device).
It is cut into chip elements (chip ceramic electronic parts) 10 having a size of 3.0 mm.

【0004】図12は大板のセラミック基板1に対して
印刷形成した熱硬化性カバー樹脂層6のパターンを示す
もので、多数のチップ素子部分に熱硬化性カバー樹脂層
6が連続したパターンで形成されている。
FIG. 12 shows a pattern of a thermosetting cover resin layer 6 formed on a large ceramic substrate 1 by printing. The thermosetting cover resin layer 6 is continuous with a large number of chip element portions. Is formed.

【0005】[0005]

【発明が解決しようとする課題】ところで、図11
(A)及び図12の例のように熱硬化性カバー樹脂層6
と封止樹脂層7とからなる被覆層がセラミック基板1に
連続的に全面塗布されるパターンの場合、図12中ダイ
シングソーによる切断部分(A−A,B−B,C−Cに
沿った部分の全て)は電気的特性機能部分Q(銅膜及び
空洞形成部分)と同一印刷パターンであるため、セラミ
ックデバイスウェハーの一部の断面図である図11
(A)のように熱硬化性カバー樹脂層6と封止樹脂層7
は隣接する切断部分(図11中のP)にも連続して被覆
されていることになり、ダイシングソーで切断してチッ
プ化する際、切断部分Pを樹脂積層状態の上から切断刃
(ブレード)9を当てて切断している。このため、切断
した際に切断応力でセラミック基板1と樹脂接着面との
接着強度が低下し前記特性機能部分Qの樹脂層、特に特
性機能を左右する前記カバー樹脂層6が図11(B)の
如く剥離してしまい、切断後、前記特性機能部分Qの銅
膜3や空洞部8又はセラミック基板1の露出が生じるこ
とになる。このために、特性が悪く歩留まりも悪い欠点
を有していた。
However, FIG.
(A) and the thermosetting cover resin layer 6 as in the example of FIG.
In the case of a pattern in which a coating layer composed of the resin layer 7 and the sealing resin layer 7 is continuously applied to the entire surface of the ceramic substrate 1, the cut portions (AA, BB, and CC along the cuts by the dicing saw in FIG. 11) is a cross-sectional view of a part of the ceramic device wafer because all of the portions have the same print pattern as the electrical characteristic function portion Q (the portion where the copper film and the cavity are formed).
(A) Thermosetting cover resin layer 6 and sealing resin layer 7
Is also continuously coated on the adjacent cut portion (P in FIG. 11), and when cutting with a dicing saw into chips, the cut portion P is cut from the resin laminated state on the cutting blade (blade). ) 9 is cut. For this reason, the cutting strength reduces the adhesive strength between the ceramic substrate 1 and the resin bonding surface due to the cutting stress, and the resin layer of the characteristic function portion Q, particularly the cover resin layer 6 which determines the characteristic function, is formed as shown in FIG. After the cutting, the copper film 3, the cavity 8, or the ceramic substrate 1 of the characteristic function portion Q is exposed. For this reason, it has the disadvantage that the characteristics are poor and the yield is poor.

【0006】特に、前記レジスト皮膜4を抜き孔5より
除去した後に生じる空洞部8を確保するカバー樹脂層6
が切断によって剥離してしまうことは、前記電気的特性
機能部分Qが決定的に悪くなってしまう問題を生ずる。
In particular, a cover resin layer 6 for securing a cavity 8 formed after removing the resist film 4 from the hole 5.
Is peeled off by cutting, there arises a problem that the electrical characteristic function portion Q is definitely degraded.

【0007】本発明は、上記の点に鑑み、高周波SMD
TレゾネータやPHS用10.75MHzチップセラミ
ックフィルター等のチップセラミック電子部品を製造す
るに際して、カバー樹脂層の印刷パターンを工夫するこ
とで、チップ中間体の品質及び歩留まりを改善可能なセ
ラミックデバイスウェハー及びその製造方法を提供する
ことを目的としている。
[0007] In view of the above, the present invention provides a high frequency SMD.
When manufacturing chip ceramic electronic components such as a T resonator and a 10.75 MHz chip ceramic filter for PHS, a ceramic device wafer capable of improving the quality and yield of a chip intermediate by devising a printing pattern of a cover resin layer, and the like. It is intended to provide a manufacturing method.

【0008】本発明のその他の目的や新規な特徴は後述
の実施の形態において明らかにする。
[0008] Other objects and novel features of the present invention will be clarified in embodiments described later.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するため
に、本発明のセラミックデバイスウェハーは、セラミッ
ク基板面上に個別素子となるべき電気的特性機能部分を
複数設けた構成において、各電気的特性機能部分を覆う
カバー樹脂層が、個々の電気的特性機能部分毎に分離さ
れて形成され、かつ切断部分には存在していないことを
特徴としている。
In order to achieve the above object, a ceramic device wafer according to the present invention has a structure in which a plurality of electric characteristic function portions to be individual elements are provided on a ceramic substrate surface. It is characterized in that the cover resin layer covering the characteristic function part is formed separately for each individual electric characteristic function part and does not exist in the cut part.

【0010】また、本発明のセラミックデバイスウェハ
ーの製造方法は、セラミック基板面上に個別素子となる
べき電気的特性機能部分を印刷パターンで複数形成する
場合において、各電気的特性機能部分を覆うカバー樹脂
層の印刷パターンが個々の電気的特性機能部分毎に分離
しかつ個別素子にチップ化するための切断部分に延在し
ていない印刷パターンとなっていることを特徴としてい
る。
Further, in the method of manufacturing a ceramic device wafer according to the present invention, in the case where a plurality of electric characteristic function portions to be individual elements are formed on a ceramic substrate surface by a printing pattern, a cover covering each electric characteristic function portion is provided. It is characterized in that the printed pattern of the resin layer is a printed pattern that is separated for each individual electrical characteristic function portion and does not extend to a cut portion for chipping into individual elements.

【0011】[0011]

【発明の実施の形態】以下、本発明に係るセラミックデ
バイスウェハー及びその製造方法の実施の形態を図面に
従って説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a ceramic device wafer and a method for manufacturing the same according to the present invention will be described below with reference to the drawings.

【0012】図1は本発明の実施の形態に係るセラミッ
クデバイスウェハーを、図2は個別のチップ素子(チッ
プセラミック電子部品)となるべき部分の空洞部及びカ
バー樹脂の配置を、図3乃至図7はセラミックデバイス
ウェハーの製造過程をそれぞれ示す。また、図8はチッ
プ素子の電気的特性機能部分を覆う(カバーする)カバ
ー樹脂層用印刷パターンの1個分のブロックパターンを
拡大したものであり、図9は図8のブロックパターンを
一対配置として複数箇所形成した全体の印刷パターン図
の一例であり、A−A,B−B,C−Cの線は切断され
る部分でその一部を示している。
FIG. 1 is a diagram showing a ceramic device wafer according to an embodiment of the present invention, and FIG. 2 is a diagram showing the arrangement of a cavity and a cover resin in a portion to be an individual chip element (chip ceramic electronic component). Reference numeral 7 denotes a process for manufacturing a ceramic device wafer. FIG. 8 is an enlarged view of one block pattern of the print pattern for the cover resin layer that covers (covers) the electrical characteristic function portion of the chip element, and FIG. 9 shows a pair of block patterns of FIG. Is an example of an overall print pattern diagram in which a plurality of portions are formed, and lines AA, BB, and CC are cut portions and some of them are shown.

【0013】図3乃至図7で製造過程を説明する。図3
に示すように、まず貫通孔2を設けたセラミック基板1
(大板)に電極形成工程で所定パターンの銅膜の電極3
をスパッタリングで形成するとともに貫通孔2の孔埋め
を行い、前記貫通孔2を除く所定領域(図2の空洞部8
に対応する領域で、セラミック基板1、電極3と熱硬化
性カバー樹脂層との間)に図4のように印刷にてレジス
ト皮膜4を形成する。このレジスト皮膜4の印刷塗布は
レジストが前記所定領域に印刷されるような印刷パター
ンが用いられる。
The manufacturing process will be described with reference to FIGS. FIG.
As shown in FIG. 1, first, a ceramic substrate 1 provided with a through hole 2 is provided.
(Large plate) Electrode 3 of copper film of predetermined pattern in electrode forming process
Is formed by sputtering, and the through-hole 2 is filled to form a predetermined region (the cavity 8 in FIG. 2) excluding the through-hole 2.
The resist film 4 is formed by printing on the ceramic substrate 1, the electrodes 3 and the thermosetting cover resin layer in a region corresponding to (2) as shown in FIG. 4. The print coating of the resist film 4 uses a print pattern such that the resist is printed on the predetermined area.

【0014】前記レジスト皮膜4が乾燥して硬化した後
に、図5の如く熱硬化性カバー樹脂層6Aが所定位置に
印刷形成されるよう印刷パターンを用いるが、この印刷
パターンは、切断部分Pには印刷塗布しないように、ま
た、前記レジスト皮膜4が除去できる抜き孔5を設ける
ように構成されている。つまり、図8に示す熱硬化性カ
バー樹脂層6Aの印刷パターンの素子1個分の拡大平面
図、及び図9の大板のセラミック基板1に対する熱硬化
性カバー樹脂層6Aの印刷パターン全体図からわかるよ
うに、チップ素子の電気的特性機能部分Qを覆う熱硬化
性カバー樹脂層6Aの印刷パターンは、個々の素子の電
気的特性機能部分毎に分離しかつ個別素子にチップ化す
るための切断部分に延在していない印刷パターンとなっ
ている。換言すれば、図9に示すダイシングソーによる
切断部分(A−A,B−B,C−Cに沿った部分の全
て)には熱硬化性カバー樹脂層6Aの印刷パターンが存
在していないブロックパターン(相互にブロックとして
分離したパターン)となっている。
After the resist film 4 is dried and cured, a printing pattern is used so that the thermosetting cover resin layer 6A is printed at a predetermined position as shown in FIG. Is formed so as not to be applied by printing and to form a hole 5 from which the resist film 4 can be removed. That is, from the enlarged plan view of one element of the print pattern of the thermosetting cover resin layer 6A shown in FIG. 8 and the entire print pattern of the thermosetting cover resin layer 6A for the large ceramic substrate 1 of FIG. As can be seen, the printed pattern of the thermosetting cover resin layer 6A covering the electrical characteristic function part Q of the chip element is cut for separating the individual electric characteristic function part of each element and forming the chip into individual elements. The printed pattern does not extend to the portion. In other words, the block where the print pattern of the thermosetting cover resin layer 6A does not exist in the cut portion (all along AA, BB, CC) by the dicing saw shown in FIG. It is a pattern (a pattern separated from each other as a block).

【0015】従って、前記熱硬化性カバー樹脂層6Aを
加熱により硬化させた後、揮発性溶剤にてレジスト皮膜
4を抜き孔5より除去し、空洞部8を形成した後に、図
6の如く全面を被覆保護する封止樹脂層7Aを重ねて印
刷することで、切断部分Pのセラミック基板1の露出部
分を被覆する共に前記抜き孔5を充填閉鎖して硬化させ
ることにより、図1及び図7のように切断部分Pに熱硬
化性カバー樹脂層6Aが存在しないセラミックデバイス
ウェハーが得られる。
Therefore, after the thermosetting cover resin layer 6A is cured by heating, the resist film 4 is removed from the hole 5 with a volatile solvent to form a cavity 8, and then the entire surface as shown in FIG. 1A and 7B by coating and sealing the exposed portion of the ceramic substrate 1 in the cut portion P and filling and closing the cutout hole 5 to cure the resin. As described above, a ceramic device wafer having no thermosetting cover resin layer 6A in the cut portion P is obtained.

【0016】なお、封止樹脂層7Aは紫外線硬化樹脂系
で有るため室温程度で硬化し、強度は前記カバー樹脂層
6Aよりも低いので、図1のようにセラミックデバイス
ウェハーを切断刃9で個別チップ素子に切断分離しよう
とする際、切断作業は容易となると共に前記カバー樹脂
層6A迄は切断応力が掛からないので、前記セラミック
基板1とカバー樹脂層6Aの接着強度は低下せず剥離が
生じることはない。
Since the sealing resin layer 7A is made of an ultraviolet curable resin, it cures at about room temperature, and has a lower strength than the cover resin layer 6A. Therefore, as shown in FIG. When the chip element is to be cut and separated, the cutting operation is facilitated and no cutting stress is applied to the cover resin layer 6A, so that the peeling occurs without reducing the adhesive strength between the ceramic substrate 1 and the cover resin layer 6A. Never.

【0017】この実施の形態によれば、次の通りの効果
を得ることができる。
According to this embodiment, the following effects can be obtained.

【0018】(1) 図1に示すように、熱硬化性カバー
樹脂層6Aを電気的特性機能部分Qのみを覆うように形
成した後、封止樹脂層7Aを塗布するので、熱硬化性カ
バー樹脂層6Aは個別の電気的特性機能部分Q毎に独立
して形成されることになり、カバー樹脂層6Aは切断部
分Pには形成されず、切断部分Pにおいては封止樹脂層
7Aのみがセラミック基板1上に塗布された構成とな
る。従って、切断刃9で図1のセラミックデバイスウェ
ハーを切断する際は、熱硬化性カバー樹脂層6Aを切断
しないで処理される。このために、前記電気的特性機能
部分Qに悪影響を与えずにチップ素子である電子部品中
間体を特性よく均一な品質を維持した状態で大量製造す
ることができる。
(1) As shown in FIG. 1, after the thermosetting cover resin layer 6A is formed so as to cover only the electrical characteristic function portion Q, the sealing resin layer 7A is applied. The resin layer 6A is formed independently for each individual electric characteristic function portion Q, and the cover resin layer 6A is not formed at the cut portion P, and only the sealing resin layer 7A is formed at the cut portion P. The structure is applied on the ceramic substrate 1. Therefore, when cutting the ceramic device wafer of FIG. 1 with the cutting blade 9, the processing is performed without cutting the thermosetting cover resin layer 6A. For this reason, it is possible to mass-produce an electronic component intermediate which is a chip element with good characteristics and uniform quality without adversely affecting the electrical characteristic function part Q.

【0019】(2) 製造設備として比較的安価な印刷機
に適用できるので、トータルコストの削減を図ることが
できる。
(2) Since the present invention can be applied to a relatively inexpensive printing machine as a manufacturing facility, the total cost can be reduced.

【0020】なお、本発明は、図1のような1個の空洞
部を有するチップ素子の製造に適用可能であるだけでな
く、複数個の空洞部や複数個の貫通孔を有するチップ素
子の製造にも適用可能であることは明白である。
The present invention is applicable not only to the manufacture of a chip device having one cavity as shown in FIG. 1, but also to a chip device having a plurality of cavities and a plurality of through holes. Obviously, it is also applicable to manufacturing.

【0021】また、熱硬化性カバー樹脂層が1層の場合
を示したが、熱硬化性カバー樹脂層が複数層で構成され
ている場合にも本発明は適用可能である。
Although the case where the number of thermosetting cover resin layers is one has been described, the present invention can be applied to the case where the number of thermosetting cover resin layers is plural.

【0022】以上本発明の実施の形態について説明して
きたが、本発明はこれに限定されることなく請求項の記
載の範囲内において各種の変形、変更が可能なことは当
業者には自明であろう。
Although the embodiments of the present invention have been described above, it is obvious to those skilled in the art that the present invention is not limited to the embodiments and that various modifications and changes can be made within the scope of the claims. There will be.

【0023】[0023]

【発明の効果】以上説明したように、本発明に係るセラ
ミックデバイスウェハー及びその製造方法によれば、従
来の印刷パターンがカバー樹脂層が切断部分まで全面連
続したものであったから、切断時にセラミック基板より
カバー樹脂層が剥離し、空洞部等に水分等が浸入して特
性を劣化させる欠点を有していたのであるが、カバー樹
脂層の印刷パターンを工夫して、切断部分にはカバー樹
脂層を印刷塗布しなくしたので、極めて均一で特性品質
の良いチップ電子部品を実現可能である。また、設備的
に比較的安価な印刷機に適用できるのでトータルコスト
の削減も図ることができる。
As described above, according to the ceramic device wafer and the method of manufacturing the same according to the present invention, since the conventional printed pattern is one in which the cover resin layer is entirely continuous up to the cut portion, the ceramic substrate is cut at the time of cutting. The cover resin layer peeled off, and moisture and the like penetrated into the cavity and the like, and had the disadvantage of deteriorating the characteristics.However, by devising the print pattern of the cover resin layer, the cut resin layer Is not printed and coated, it is possible to realize a chip electronic component having extremely uniform and excellent characteristic quality. Further, since the present invention can be applied to a relatively inexpensive printing machine, the total cost can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係るセラミックデバイスウェハー及び
その製造方法の実施の形態であって、セラミックデバイ
スウェハーを切断刃で切断している工程を示す断面図で
ある。
FIG. 1 is an embodiment of a ceramic device wafer and a method for manufacturing the same according to the present invention, and is a cross-sectional view showing a step of cutting a ceramic device wafer with a cutting blade.

【図2】前記セラミックデバイスウェハーの個々のチッ
プ素子となるべき部分であって封止樹脂層を省略した平
面図である。
FIG. 2 is a plan view of a portion to be an individual chip element of the ceramic device wafer, in which a sealing resin layer is omitted.

【図3】実施の形態における電極形成工程を示す断面図
である。
FIG. 3 is a cross-sectional view showing an electrode forming step in the embodiment.

【図4】同じくレジスト印刷工程を示す断面図である。FIG. 4 is a sectional view showing a resist printing step.

【図5】同じく熱硬化性カバー樹脂層の印刷工程を示す
断面図である。
FIG. 5 is a cross-sectional view showing a printing step of a thermosetting cover resin layer.

【図6】同じく封止樹脂の印刷工程を示す断面図であ
る。
FIG. 6 is a sectional view showing a printing step of the sealing resin.

【図7】実施の形態により得られたセラミックデバイス
ウェハーを切断する工程を示す断面図である。
FIG. 7 is a sectional view showing a step of cutting the ceramic device wafer obtained according to the embodiment.

【図8】実施の形態によるセラミックデバイスウェハー
の電気的特性機能部分を覆うカバー樹脂層用印刷パター
ンの1例であって、1個のブロックパターンの拡大平面
図である。
FIG. 8 is an enlarged plan view of one block pattern, which is an example of a print pattern for a cover resin layer covering an electrical characteristic function portion of a ceramic device wafer according to an embodiment.

【図9】カバー樹脂層用印刷パターンの全体平面図であ
る。
FIG. 9 is an overall plan view of a print pattern for a cover resin layer.

【図10】従来のセラミックデバイスウェハーの製造工
程概要説明図である。
FIG. 10 is a schematic diagram illustrating a conventional manufacturing process of a ceramic device wafer.

【図11】従来のセラミックデバイスウェハーにおける
チップ素子化への切断時の断面説明図である。
FIG. 11 is an explanatory sectional view of a conventional ceramic device wafer when it is cut into chip elements.

【図12】従来のカバー樹脂層用印刷パターンを示す全
体平面図である。
FIG. 12 is an overall plan view showing a conventional print pattern for a cover resin layer.

【符号の説明】[Explanation of symbols]

1 セラミック基板 2 貫通孔 3 電極 4 レジスト皮膜 5 抜き孔 6,6A 熱硬化性カバー樹脂層 7,7A 封止樹脂層 8 空洞部 9 切断刃 10 チップ素子 DESCRIPTION OF SYMBOLS 1 Ceramic substrate 2 Through hole 3 Electrode 4 Resist film 5 Drilled hole 6, 6A Thermosetting cover resin layer 7, 7A Sealing resin layer 8 Cavity 9 Cutting blade 10 Chip element

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 セラミック基板面上に個別素子となるべ
き電気的特性機能部分を複数設けたセラミックデバイス
ウェハーにおいて、各電気的特性機能部分を覆うカバー
樹脂層が、個々の電気的特性機能部分毎に分離されて形
成され、かつ切断部分には存在していないことを特徴と
するセラミックデバイスウェハー。
In a ceramic device wafer provided with a plurality of electric characteristic function portions to be individual elements on a ceramic substrate surface, a cover resin layer covering each electric characteristic function portion is provided for each electric characteristic function portion. A ceramic device wafer, wherein the ceramic device wafer is formed so as to be separated from the substrate and does not exist in the cut portion.
【請求項2】 セラミック基板面上に個別素子となるべ
き電気的特性機能部分を印刷パターンで複数形成したセ
ラミックデバイスウェハーの製造方法において、各電気
的特性機能部分を覆うカバー樹脂層の印刷パターンが個
々の電気的特性機能部分毎に分離しかつ個別素子にチッ
プ化するための切断部分に延在していない印刷パターン
となっていることを特徴とするセラミックデバイスウェ
ハーの製造方法。
2. A method for manufacturing a ceramic device wafer in which a plurality of electrical characteristic function portions to be individual elements are formed on a ceramic substrate surface by a print pattern, wherein a print pattern of a cover resin layer covering each electrical characteristic function portion is formed. A method for manufacturing a ceramic device wafer, wherein a printed pattern is formed so as to be separated into individual electric characteristic function portions and not to extend to a cut portion for forming a chip into individual elements.
JP19522897A 1997-07-07 1997-07-07 Ceramic device wafer and its production Withdrawn JPH1127080A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19522897A JPH1127080A (en) 1997-07-07 1997-07-07 Ceramic device wafer and its production

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19522897A JPH1127080A (en) 1997-07-07 1997-07-07 Ceramic device wafer and its production

Publications (1)

Publication Number Publication Date
JPH1127080A true JPH1127080A (en) 1999-01-29

Family

ID=16337614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19522897A Withdrawn JPH1127080A (en) 1997-07-07 1997-07-07 Ceramic device wafer and its production

Country Status (1)

Country Link
JP (1) JPH1127080A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009100436A (en) * 2007-09-27 2009-05-07 Citizen Finetech Miyota Co Ltd Method of manufacturing piezoelectric device
JP2010147627A (en) * 2008-12-17 2010-07-01 Epson Toyocom Corp Piezoelectric vibrator and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009100436A (en) * 2007-09-27 2009-05-07 Citizen Finetech Miyota Co Ltd Method of manufacturing piezoelectric device
JP2010147627A (en) * 2008-12-17 2010-07-01 Epson Toyocom Corp Piezoelectric vibrator and method for manufacturing the same

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