JPH1126751A - Mos semiconductor element and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the distance between the source and the drain, by depositing a semiconductor substrate on the main surface so that a part of a semiconductor thin film layer is in contact with a gate insulating film, and thereby making it possible to provide a semiconductor film which becomes source/drain electrodes so as to come into contact with gate electrode. SOLUTION: An oxide film 104 having the thickness of about 5 nm is formed by a wet oxidation method. A polycrystalline silicon film is formed thereon and processed into a gate electrode 102. Then, after an impurity region 105 is formed by ion implantation method for a source region and a drain region, the oxide film 104 on the source region and the drain region is removed. Here, a silicon germanium film 101 is selectively formed in the source region and the drain region. That is to say, crystal grow the is performed under the conditions wherein the crystal grown on the silicon substrate 100 but the crystal is hard to grow on the oxide film 104 at the same time. The silicon germanium film 101, which becomes the source/drain electrodes, is formed so as to come into contact with the gate electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device (transistor, FET), and in particular, to a high performance MO capable of operating at high speed with a short distance between a source and a drain.
The present invention relates to an S-type semiconductor device and a method for manufacturing a MOS-type semiconductor device which requires fewer steps than conventional manufacturing processes and can reduce the manufacturing cost.

[0002]

2. Description of the Related Art Highly integrated semiconductor elements have been manufactured by a method of manufacturing a large number of transistors by repeatedly diffusing impurities and forming polycrystalline silicon on a silicon wafer. In MOS transistors, FIG.
As shown in FIG.
Region 10 where impurities are diffused for manufacturing a type semiconductor
5, a gate oxide film 104, a polysilicon 102 serving as a gate electrode on the gate oxide film are manufactured by a method such as CVD, and a source and a drain on the other side (hereinafter abbreviated as source / drain) are further formed. 101 is manufactured by forming a film of silicon germanium, and one F
Manufacturing ET. By simultaneously manufacturing these FETs in units of thousands or tens of thousands at a time, a highly integrated semiconductor device is manufactured.

As shown in FIG. 2, a polycrystalline silicon 102 having a rectangular cross section processed by dry etching or the like is formed on a gate oxide film 104 of a MOSFET, and insulating film spacers 107 are formed on both sides thereof. Is done. This insulating film spacer is provided to prevent a short circuit between the polycrystalline gate 102 and the source / drain when silicon is deposited as the stacked source / drain 101 provided in the adjacent region.

Further, in the method shown in FIG. 3 described in JP-A-3-50771, a gate polysilicon 10
2 is not masked with an insulating film, the gate oxide film layer 104 is not masked.
Source / drain 101
By reducing the film thickness of the source / drain 10
1 and the polycrystalline silicon 107 deposited on the gate polycrystalline silicon 102 are not short-circuited.

[0005]

In a method of manufacturing a MOS FET semiconductor device, it is desirable that a short circuit between a gate and a source / drain can be prevented, and that the device can be manufactured by a simpler process. As shown in the enlarged view of FIG. 4, when the insulating film spacer 106 is provided to prevent a short circuit between the gate 102 and the source / drain 101 in the related art, the distance between the source and the drain is twice the film thickness d. It is necessary to design a long distance.

[0006] MOS transistor semiconductor elements perform various operations by controlling the amount of electrons supplied from the source to the drain with a voltage applied to the gate. in this case,
If the distance between the source and the drain is long, it takes a longer time for electrons to move, that is, a problem arises in that high-speed operation cannot be performed. Therefore, in a semiconductor that requires a high-speed switching operation or the like, it is desirable to minimize the distance between the source and the drain. However, when the insulating film spacer is provided, the distance between the source and the drain cannot be reduced by that much, and therefore, there is a limit in increasing the speed of the device.

Further, when the spacer is thick, the source / drain impurity region does not diffuse to the lower portion of the gate insulating film due to thermal diffusion or the like, and the parasitic capacitance increases. In the conventional selective growth technique, monocrystalline silicon and polycrystalline silicon are similarly deposited on the single-crystal substrate surface of the source and drain regions and the polycrystalline surface of the gate, respectively. It is necessary to use an insulating film mask. Since the insulating film is usually a nitride film, diffusion of impurities due to heat of forming the nitride film and a photolithography process are increased. By increasing the thickness of the gate oxide film to several tens of nm, the performance of the transistor is degraded, and a high degree of controllability for preventing the source / drain electrodes and the gate from being short-circuited is required.

Further, in the method described in Japanese Patent Application Laid-Open No. 3-50771, there is a limitation on the manufacturing process, such as a longer process time due to a thicker gate oxide film.

A first object of the present invention is to provide a MOS type semiconductor device which can operate at high speed because it is not necessary to provide an insulating film spacer around a gate electrode.

A second object of the present invention is to provide a method of manufacturing a MOS type semiconductor device which can simplify the manufacturing process of the MOS type semiconductor device and can reduce the manufacturing cost.

[0011]

Means for Solving the Problems To achieve the first object of the present invention, a first invention of the present invention provides a gate insulating film formed on a main surface of a semiconductor substrate, and the gate insulating film. Forming a source / drain diffusion layer having a gate electrode formed thereon and two diffusion layers of one conductivity type formed on a main surface of the semiconductor substrate with the gate electrode interposed therebetween; A semiconductor thin film layer is selectively deposited on a main surface of the semiconductor substrate, and a part of an edge of the semiconductor thin film layer is provided so as to be in contact with the gate insulating film. It is intended to provide a MOS type semiconductor device.

"A part of the edge of the semiconductor thin film layer is in contact with the gate insulating film" means that the semiconductor thin film layer 101 cannot grow on the surface of the insulating film 104 as shown in the enlarged view of FIG. Main surface of substrate 100 and gate insulating film 10
4 shows that the semiconductor thin film 101 has grown only up to the boundary line 4, and the thickness d of the spacer 106 in FIG.

According to the above structure, the semiconductor film (which becomes the source / drain electrodes) can be provided so as to be adjacent to the gate electrode. Therefore, the distance between the source and the drain of the semiconductor element can be reduced, and the speed can be increased. Operable M
An OS type semiconductor element can be provided.

In the first invention, it is preferable that the semiconductor thin film layer contains germanium. Since the semiconductor thin film containing germanium has good selective growth and is difficult to grow on the gate insulating film, it is not necessary to provide an insulator spacer around the gate electrode.

Further, in the first invention, the gate electrode is made of a polycrystalline film, and the crystal has an average grain size of 50 nm.
It is preferable that it is above.

According to the above configuration, it is possible to effectively prevent a semiconductor film from growing on the gate electrode.

In order to achieve the second object, a second invention of the present invention comprises a step of providing an oxide film on a main surface of a semiconductor substrate, a step of providing a polycrystalline semiconductor film on the oxide film, and Providing a gate electrode by processing the crystal film, providing an oxide film to cover the gate electrode, processing the oxide film provided to cover the gate electrode, and forming an oxide film spacer around the gate electrode. Forming a source / drain region by diffusing impurities around the gate electrode, removing the oxide film spacer, and depositing a source gas containing silicon atoms and germanium on the source / drain region. Providing source and drain electrodes by a chemical vapor deposition method using a source gas containing a source gas including a carrier gas, and a gas having an etching action as needed. There is provided a method of manufacturing a MOS type semiconductor device according to symptoms.

According to the above configuration, the MO can be improved compared to the conventional process.
Since the manufacturing process of the S-type semiconductor element can be simplified, the semiconductor manufacturing cost can be reduced.

In the second invention, when the average crystal grain size of the polycrystalline gate electrode is 50 nm or less, germanium and a source gas containing silicon atoms in the source gas used for the chemical vapor deposition method are included. The volume ratio of the source gas is around 4: 1, and the average crystal grain size of the gate electrode is 5
When it is larger than 0 nm, it is preferable to increase the ratio of the source gas containing germanium, and when the average crystal grain size is smaller than 50 nm, it is preferable to decrease the ratio of the source gas containing germanium.

The crystal grain size of the gate electrode changes depending on the substrate temperature, the supply amount of the source gas, and the like during the vapor phase growth process. By optimizing the composition of the semiconductor film in the source gas used for the chemical vapor deposition method according to the average crystal grain size of the gate electrode, the process can be optimized.

In the second invention, the mixing amount of the etching gas in the source gas used in the chemical vapor deposition method is
It is preferable to adjust according to the volume ratio of the source gas containing silicon atoms and the source gas containing germanium.

The semiconductor thin film can be formed by changing the mixing amount of the etching gas in the source gas used in the chemical vapor deposition method, in addition to the average crystal grain size of the gate electrode, in addition to the average crystal grain size of the gate electrode. Optimum conditions can be adjusted so as not to grow on the electrode. That is, the semiconductor manufacturing process can be optimized only by changing the composition in the source gas used in the chemical vapor deposition method according to the specifications of the semiconductor manufacturing apparatus to be used (without considering other conditions). is there.

Hereinafter, the principle of the present invention will be described.

Silicon germanium or germanium has a higher selectivity for a substrate to be deposited than silicon. Here, the growth with selectivity means that it grows on the crystal substrate but hardly grows on the amorphous insulating film at the same time. In other words, it is easy to obtain a growth condition that grows on a single crystal or polycrystalline substrate but does not grow on an oxide film or a nitride film at the same time. The present inventors have found through experiments that a film can be grown not only on an insulating film but also on a polycrystal, as shown in FIG. Was.

Polycrystalline silicon is an aggregate of crystal grains,
It is considered that the crystal grains are composed of two phases, that is, a crystal part and a grain boundary part. The crystal part is a silicon single crystal, but the grain boundaries have many silicon dangling bonds,
The structure makes it easy to take in impurities such as oxygen and moisture. By changing the grain size of the crystal grains, the ratio of these two phases can be changed. In the present invention, when the polycrystalline grain size is reduced and the ratio of the grain boundary portion is set to a value larger than a certain value, even when the silicon germanium or germanium is grown on the polycrystalline substrate, it behaves similarly to the insulating film. I understood. The critical value of the particle size that satisfies this condition varies depending on the germanium concentration, the proportion of the etching gas and the like, but it has been found by experiments that the average particle size is about 50 nm. That is, it is possible to selectively grow the silicon germanium and germanium films only on the single crystal substrate and not on the insulating film and the polycrystal at the same time.

By utilizing this, since it is not necessary to form the side wall of the insulating film in the gate portion, the source / drain can be formed without being sandwiched between the gate oxide film and the gate oxide film. Since it is not necessary to interpose an insulating film spacer between the stacked source / drain films, the distance between the source / drain can be reduced. As a result, the speed of the device can be increased. Further, steps such as deposition, patterning, and processing of a spacer insulating film can be omitted.
In addition, since the source / drain impurity region is diffused just below the gate oxide film, the parasitic resistance can be reduced.
Further, since the germanium and silicon germanium films always have facets formed at the boundary with the insulating film, and do not deposit on the gate polycrystalline film, there is no fear of short-circuit between the gate and the source / drain electrodes.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION

 (Embodiment 1) Hereinafter, Embodiment 1 of the present invention will be described.

A well-known LOC is formed on the surface of a substrate 201 which is a part of a p-type silicon wafer having a (100) crystal orientation.
An oxide film 202 for element isolation was formed in the periphery of the element formation region by the OS method. The thickness of the oxide film is 350 nm. In the above steps, the structure shown in FIG. 6 was obtained.

Next, an oxide film 203 having a thickness of 5 nm was formed by wet oxidation, and a polycrystalline silicon film 204 having a thickness of 200 nm was formed on the oxide film 203 by low pressure chemical vapor deposition. The structure described in FIG. 7 was obtained in the above steps.

Next, the gate electrode was manufactured by processing the polycrystalline silicon film 204 by a known photolithography technique. The width of the gate electrode 205 made of a polycrystalline silicon film is 0.2 μm. The structure described in FIG. 8 was obtained by the above steps.

Next, the oxide film 206 is formed by a low pressure chemical vapor deposition method.
Was formed. Oxide film 206 has a thickness of 300 nm.
The structure described in FIG. 9 was obtained in the above steps.

Next, oxide film 2 is formed by anisotropic etching.
06 was etched to form an insulating film spacer 207. The structure described in FIG. 10 was obtained in the above steps.

Next, arsenic was implanted into the source region 208 and the drain region 209 by ion implantation to form an n-type impurity region 210. The conditions for ion implantation are an acceleration voltage of 40 keV and a dose of 2 × 10 ¹⁵ / cm ² . The structure described in FIG. 11 was obtained in the above steps.

Next, the oxide film 203 and the insulating film spacer 207 on the source region 211 and the drain region 212 were removed by immersion in a hydrofluoric acid solution. The structure described in FIG. 12 was obtained by the above steps.

Next, a silicon germanium film 213 was selectively formed on the source region 211 and the drain region 212 in a low pressure chemical vapor deposition apparatus. The conditions for forming the silicon germanium film 213 are as follows: growth temperature 650 ° C., growth pressure 1
It is formed by adding a flow rate of 18 cc / min of toll and monosilane gas, a flow rate of 10 cc / min of hydrogen chloride gas, a flow rate of 1 liter / min of hydrogen gas, a flow rate of 2 cc / min of germane gas, and a flow rate of 0.1 cc / min of phosphine gas. In this case, in order to more completely achieve the selective formation of the silicon germanium film 213, when the average crystal grain size of the polycrystalline silicon film as the gate electrode 205 is larger than 50 nm, the flow rate of the germane gas is increased. When the flow ratio of monosilane / germane gas is smaller than 4/1, on the other hand, when it is smaller than 50 nm, it is desirable to reduce the flow rate to be larger than 4/1.
Further, it is desirable to experimentally optimize a flow rate range in which the silicon germanium film 213 can be selectively formed as an addition flow rate of the hydrogen chloride gas.

The thickness of the silicon germanium film 213 formed under the above conditions is 100 nm. The sheet resistance of silicon germanium is 100Ω / □. The structure described in FIG. 13 was obtained by the above steps.

Next, an impurity diffusion layer 214 is formed by a heat treatment at 1000 ° C. for 20 seconds. In this step, the structure shown in FIG. 14 was obtained. This structure is the same as FIG. 1 showing the basic structure of the present invention, although the numbers of the respective parts are different.

Next, an oxide film having a thickness of 1 μm is deposited on the entire surface by a low pressure chemical growth method, an SOG (Spin On Glass) film is further deposited, and an oxide film 215 having a flat surface by a well-known etch-back method is removed. Formed. The structure described in FIG. 15 was obtained by the above steps.

Next, a contact hole is formed on the oxide film by photolithography, a tungsten film is buried, and the source electrode 2 is formed by photolithography.
16, a gate electrode 217 and a drain electrode 218 were formed. Through the above steps, the nMOSFET shown in FIG. 16 was obtained.

As a result of evaluating the electrical characteristics of the fabricated nMOSFET, the mutual inductance was 200 mS / mm at a power supply voltage of 1.5 V.

In this embodiment, a silicon single crystal wafer is used as the substrate 201, but an SOI wafer may be used.

By changing the conductivity type of the substrate, the impurity element of the silicon germanium film and the element for ion implantation, p
MOSFET can be manufactured. Also, an nMOSFET and a pMOSFET can be simultaneously manufactured to manufacture a CMOSFET.

[0043]

According to the first aspect of the present invention, a semiconductor film (which becomes a source / drain electrode) can be provided so as to be adjacent to a gate electrode. It is possible to provide a MOS semiconductor device which can be reduced in size and can operate at high speed.

According to the second aspect of the present invention, the manufacturing process of the MOS type semiconductor device can be simplified as compared with the conventional process, so that the semiconductor manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a view showing a state in which a single crystal is selectively grown only on an exposed portion of a single crystal substrate formed on a polycrystalline substrate.

FIG. 2 is a diagram showing a conventional method.

FIG. 3 is a diagram showing a conventional method.

FIG. 4 is a diagram showing a conventional method.

FIG. 5 is a diagram showing a structure of a semiconductor device of the present invention.

FIG. 6 is a view showing one step of the manufacturing process of the present invention.

FIG. 7 is a view showing one step of the manufacturing process of the present invention.

FIG. 8 is a view showing one step of the manufacturing process of the present invention.

FIG. 9 is a view showing one step of the manufacturing process of the present invention.

FIG. 10 is a view showing one step of the manufacturing process of the present invention.

FIG. 11 is a view showing one step of the manufacturing process of the present invention.

FIG. 12 is a view showing one step of the manufacturing process of the present invention.

FIG. 13 is a view showing one step of the manufacturing process of the present invention.

FIG. 14 is a view showing one step of the manufacturing process of the present invention.

FIG. 15 is a view showing one step of the manufacturing process of the present invention.

FIG. 16 is a view showing one step of the manufacturing process of the present invention.

[Explanation of symbols]

100, 201: silicon substrate, 101: silicon germanium or germanium, 102, 205: gate electrode, 103: silicon oxide film, 104: gate oxide film, 105, 210: impurity added region, 106: source / drain, 107, 207 ... insulating film spacer, 108
... polycrystalline silicon, 202, 203, 206, 215 ...
Oxide film, 204 ... polycrystalline silicon film, 208, 211 ...
Source region, 209, 212 ... drain region, 213 ...
High-concentration impurity-doped silicon germanium, 214: impurity diffusion layer, 216: source electrode, 217: gate electrode, 218: drain electrode.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Toshio Ando 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd.

Claims (6)

[Claims] A gate insulating film formed on a main surface of the semiconductor substrate; a gate electrode formed on the gate insulating film; and a gate electrode formed on the main surface of the semiconductor substrate with the gate electrode interposed therebetween. A semiconductor thin film layer is selectively deposited on a main surface of the semiconductor substrate on which the source / drain diffusion layers are formed, and an edge of the semiconductor thin film layer Characterized in that it has a structure in which a part thereof is provided in contact with the gate insulating film. 2. A MOS semiconductor device according to claim 1, wherein the semiconductor thin film layer contains germanium. 3. The MOS type semiconductor device according to claim 2, wherein the gate electrode is made of a polycrystalline film, and the crystal has an average particle diameter of 50 nm or more. A step of providing an oxide film on the main surface of the semiconductor substrate; a step of providing a polycrystalline semiconductor film on the oxide film; and a step of processing the polycrystalline film to provide a gate electrode; and covering the gate electrode. Forming an oxide film so as to cover the gate electrode, forming an oxide film spacer around the gate electrode, and diffusing impurities around the gate electrode to form a source / drain. Forming a region, removing the oxide film spacer, having a source gas containing silicon atoms, a source gas containing germanium, and a carrier gas on the source / drain regions, and further having an etching action as required. Providing source / drain electrodes by a chemical vapor deposition method using a source gas containing a gas.
A method for manufacturing an S-type semiconductor device. 5. The method according to claim 4, wherein when the average crystal grain size of the polycrystalline gate electrode is 50 nm or less, germanium and a source gas containing silicon atoms in the source gas used for the chemical vapor deposition method are used. When the volume ratio of the raw material gas containing is around 4: 1, and the average crystal grain size of the gate electrode is larger than 50 nm, the ratio of the raw material gas containing germanium is increased. Characterized in that the proportion of the source gas containing germanium is reduced.
A method for manufacturing an OS type semiconductor device. 6. A method according to claim 4, wherein a mixing amount of said etching gas in a source gas used for said chemical vapor deposition is adjusted according to a volume ratio of said source gas containing silicon atoms and said source gas containing germanium. M characterized by doing
A method for manufacturing an OS type semiconductor device.