JPH11259324A - Main storage device copying system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the reduction of reliability and the pressure of throughput as little as possible during the copy period of stored contents in a main storage device concerning a main storage device copying system for a duplex controller. SOLUTION: Concerning a duplex controller 10 provided with a duplexed central controller 100, main storage device 200 and channel controller 300, a pseudo input/output device 310 provided for testing the function of each channel controller 300 and equipped with a DMA function is provided with a memory copy command accepting means 320 for receiving/identifying a command to request the copy of stored contents in the main storage device of an active system to the main storage device of the other system. The copying system is also provided with a memory copy action control means 330 for successively extracting unit data stored at the respective addresses of the active system main storage device when the memory copying command is received from the central controller of the active system, continuously executing the data copy action for storing these data at the same addresses of the main storage device of the other system over all the storage areas of the main storage device and reporting the completion of copy to the central controller of the active system later.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main storage device copying method, and more particularly to a main storage device copying method in a redundant control device having a duplicated central control device, main storage device, and channel control device.

[0002]

2. Description of the Related Art FIG. 6 is a diagram exemplifying a conventional duplex control device, and FIG. 7 is a diagram exemplifying a main storage device copying process in FIG.

For example, as shown in FIG. 6, a control unit of an information processing system, such as an electronic exchange, whose operation cannot be interrupted is a dual central control unit (CC) 1 [individual central control unit (CC)]. is referred to as 1 ₀ and 1 _1,
The same applies to the following.), A main memory (MM) 2 and a channel controller (CHC) 3.

A pseudo input / output device (PIO) 31 is provided in each channel control device (CHC) 3 for the purpose of diagnosing the function of the channel control device (CHC) 3. It has nothing to do with the copying process of the main storage device in the device 10.

[0005] The central controller (CC) 1 ₀ are connected via a system bus 11 ₀ to the main memory (MM) 2 _0, 2 ₁ and channel control unit _{(CHC) 3 0, 3 1} , also The central control unit (CC) ₁₁ also has a system bus 1
It is connected to the respective main memory (MM) 2 _0, 2 ₁ and channel control unit (CHC) 3 _0, 3 ₁ through 1 _1.

[0006] Each channel control device (CHC) 3
Each is connected to an input / output device (IO) 4 via a C bus 12. The central controller (CC) 1 _0, main memory (MM) 2 ₀ and channel control unit (CHC) 3 ₀
Referred to configured control unit and 0-based controller 10 _0, the addition central controller (CC) 1 _1, a main memory (M
M) 2 ₁ and channel control unit (CHC) 3 refers to a control device composed of _one and one system controller 10 _1.

[0007] Normally, whereas [e.g. 0-based controller 10 _0]
There runs as the working system and the other [1 system controller 10 _1] are waiting as a spare system, when an abnormality in the 0-system control unit 10 ₀ becomes inoperable occurred immediately 1 system controller 10 ₁ maintains the continuity of the operation to start the operation as new active system, 0-based controller 10 ₀ was Kakasawa after making diagnosis and repair disconnect from the working, to wait as the standby system.

[0008] In the 0-system control device 10 ₀ in the running,
The central controller (CC) 1 ₀ is the main memory of its own system (MM)
Extracts the required data from the 2 ₀ executes the required processing, the data of the processing result main memory of its own system (MM) 2 ₀
Not only, also simultaneously stored in the main memory (MM) 2 ₁ spare system, to match always memory data (D _MM) stored in the main memory (MM) 2 ₀ and 2 ₁ of both systems by placing Te, the backup system control device 10 ₁ is to ensure continuity at the time of running as working system.

Further, the redundant control device 10 periodically (for example, once a day) disconnects the standby system from the active system and executes a diagnosis of the standby system, thereby detecting a failure before starting operation. ing.

A system that has been disconnected from the active system and has been diagnosed
[For example, 1 system] main memory (MM) 2₁Stored in
Memory data (D_MM) Is the active main memory (M
M) 2 ₀Memory data (D_MM) Is not
Because it is the same, start operation as a standby system
Prior to the operation, the main memory (MM) 2 of the active system is used.₀Memory Day
(D_MM) To the main storage device (MM) 2₁Need to be copied to
There is.

For this purpose, each main memory (MM)
The 2, the central controller (CC) 1 ₀ became active system,
Memory copy program for executing such main memory copy process shown in FIG. 7 (P _MC) is stored, after connecting the main memory (MM) 2 ₁ to the working system controller 10 _0, the central control unit (CC) 1 ₀ When entering the memory copy instruction to the central controller (CC) 1 ₀ a main memory device (MM) 2 ₀ to already stored in the memory copy program (P
_MC0 ) starts execution.

[0012] The first central controller (CC) 1 _0, the unexpected shown control register (R _1), main memory (MM) 2
The start address (a _B ) of ₀ is stored [FIG.
1], the next unexpected shown control register (R _2), and stores the main memory (MM) 2 ₀ of the last address (a _E) [Step S2].

[0013] Then the central controller (CC) 1 ₀ by executing the load instruction, the main memory (MM) with reference to the 2 _0, control register (R ₁₎ to the accumulation already address (a
₁ = a _B ) Copy the data stored in the corresponding area to the copy data (d
_a1 ) and stores it in a control register (R ₃ ) (not shown) [step S3].

[0014] Then the central controller (CC) 1 ₀ by executing a store instruction, after extracting the accumulated already replicated data (d _a1) to the control register (R _3), main memory (MM) Referring to 2 ₀ and 2 _1, accumulation already addresses control register _{(R 1) (a 1 =} a B) to the corresponding region, the extracted copy data (d _a1) storing each [step S4].

[0015] Then the central controller (CC) 1 ₀ includes a control register (R ₁₎ to the accumulation already addresses (a ₁ = a _B),
The address [a ₂ = stored in the control register (R ₂ )
a _E ] [Step S5], and the two do not match [a _B
When it is confirmed that ≠ is a _E] [step S6], the control register (R ₁₎ to the accumulation already address [a ₁ = a _B)
[A ₁ = a _B +1] [Step S
7], step S3 and subsequent steps are repeatedly executed.

In the course of repeatedly executing steps S3 to S7, the central control unit (CC) 10 _sets the control register (R
Accumulation already addresses ₁₎ and (a _1), control registers (R
As a result of comparing the address [a ₂ = a _E ] stored in ₂ ) with the address [a ₂ = a _E ] [Step S5], if it is confirmed that the two match [a ₁ = a _E ] [Step S6], the main memory (MM)
2 ₀ of the start address (a _B) from the final address (a _E)
Until the already stored the entire replicated data (d _a1) [i.e. memory data (D _MM)] is also it becomes possible stored in the same area of the main memory (MM) 2 _1, and terminates the copy processing.

[0017] Thereafter the control unit 10 ₁ is enabled operated as the standby system.

[0018]

It is clear from the above description.
As described above, in the conventional redundant control device 10,
Control device 10 after₁To start operation as a standby system
In addition, the active central control unit (CC) 1₀Is a memory copy
Program (P_MC) And the main memory (MM) 2 ₀of
Copy data (d) stored in each address (a)_a1), In order
Secondary main memory (MM) 2₁The same address (a₁)
The main storage device (MM) 2₀Stored in
Memory data (D_MM) To the main memory (MM) 2₁Copy to
And spend a lot of time in the copying process.
In the meantime, the redundant control device 10 is operated in a single configuration.
And the reliability is reduced, and
Central control unit (CC) 1₀Processing capacity of memory copy program
Ram (P_MC) Could be overwhelmed.

SUMMARY OF THE INVENTION It is an object of the present invention to minimize a decrease in reliability of a storage content of a main storage device in a duplication control device during a copying period and a reduction in processing capacity.

[0020]

FIG. 1 is a diagram illustrating the principle of the present invention. In FIG. 1, reference numeral 10 denotes a duplex control device to which the present invention is applied, 100 denotes a central control device, 200 denotes a main storage device, and 300 denotes a channel control device, each of which is duplicated.

Reference numeral 310 denotes a pseudo input / output device provided for each channel control device 300 for a function test, and has a direct memory access (DMA) function. 32
Numeral 0 is a memory copy command receiving means provided in the pseudo input / output device 310 according to the present invention.

330 is a pseudo input / output device 3 according to the present invention.
10 is a copy operation control means. Memory copy command accepting unit 320, a main storage memory contents of device 200 ₀ of the active system, receiving and identifying the memory copy command requesting copied to main memory 200 ₁ of the other system.

The copy operation control unit 330, a memory copy instruction receiving unit 320, if the central controller 100 ₀ of the primary system receives a memory copy instruction is stored in the main storage device 200 each address ₀ of the active system sequentially extracting unit data is, data copying operation to be stored in the main storage device 200 ₁ at the same address of the other system, after executing continuously concerning the entire storage area of the main memory 200, the memory copying operation the execution completion, notifies the central controller 100 ₀ of the active system. [The above is related to the present invention (claim 1)] Note that the copy operation control means 330 is the main storage device 2 of the active system.
It is considered that each unit data already stored at a plurality of consecutive addresses of 00 is continuously extracted and stored at a plurality of corresponding addresses of the main storage device 200 of the other system. [Present invention (claim 2) Related] Furthermore each copying operation control unit 330 ₀ and 330 ₁ of each pseudo input device 310 ₀ and 310 _1, comprising a channel control unit 300 ₀ and 300 ₁ of both systems, each The partial storage area provided by dividing the entire storage area of the main storage apparatus 200 into two parts is shared, and the data stored in each assigned partial storage area of the active main storage apparatus 200 is transferred to another main storage apparatus 200. Is considered in parallel to the corresponding partial storage areas. [Related to the Present Invention (Claim 3)] Further, the copying operation control means 330 is provided in the main storage device 2 of the active system.
It is considered that each unit data extracted from each address of 00 is stored in parallel at the same address of the main storage devices 200 of both systems. [Regarding the Present Invention (Claim 4)] Therefore, in the dual control device, the copy operation time of the contents stored in the main storage device is greatly reduced, so that the single operation time is reduced, and the central control during copying is performed. There is no danger that the processing capacity of the apparatus will be squeezed, and the reliability and processing capacity of the redundant control device can be greatly improved.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing a redundant control device according to an embodiment of the present invention, FIG. 3 is a diagram illustrating a pseudo input / output device in FIG. 2, and FIG. 4 is a main storage device copy sequence (single address) in FIG. FIG. 5 is a diagram exemplifying a main storage device copy sequence (each multiple address) in FIG. The same reference numerals indicate the same objects throughout the drawings.

The redundant control device 10 shown in FIG.
Like the existing redundant control device 10 (see FIG. 6),
Central control unit (CC) 1₀And 1₁, Main storage
(MM) 2₀And 2₁, And the channel control device (C
HC) 3₀And 3₁, Each with 0 system control
Apparatus 10₀And 1-system control device 10₁Make up
However, the difference from the conventional redundant control device 10 is that each channel
Pseudo input / output provided in the channel control device (CHC) 3
Memory copy command received by force device (PIO) 31
Section (CCR) 32 and memory copy operation control section (MC
C) 33 is the memory copy command receiving means 32 in FIG.
0 and provided as copy operation control means 330
At the same time, a memory copy program is stored in each main storage device (MM) 2.
Program (P _MC) Is not stored.

Each pseudo input / output device (PIO) 31 is provided for diagnosing the interface to the C bus 12 of the channel control device (CHC) 3 to which the conventional dual control device 10 belongs. The C bus 12 is connected to the channel control device (CHC) 3 by an internal bus 34 and operates in a program mode or a direct memory access (hereinafter abbreviated as DMA) mode based on a command from the channel control device (CHC) 3.
Data is transferred to / from the central control unit (CC) 1 via the interface, the channel control unit (CHC) 3, and the system bus 11, and when the DMA transfer is completed, the DMA transfer control is performed on the C bus 12 interface. When an abnormality or a program abnormality is detected, an interrupt is made to the central control unit (CC) 1 to report the abnormal state.

The simulated input / output device (PIO) 31 has a configuration as shown in FIG. 3, and if only those related to the description of the embodiment of the present invention are mentioned, the control unit (CTL) 3
Reference numeral 11 denotes a circuit for controlling a diagnostic mode. A command register (CMR) 312 is a register for accumulating a DMA transfer start command, and a memory address register (MAR).
313 is a main memory (MM) 2 for executing DMA transfer
Address [hereinafter forwarding address (a _T) and referred] a register for storing the transfer byte number register (BC
R) 314 is a register for storing the amount of data to be DMA-transferred [hereinafter referred to as the number of transfer bytes (n _T )].
The data buffer register (DBR) 315 is a register for storing transfer data.

The data buffer register (DBR) 3
₁₅₀ is 1 in the embodiment of the present invention (claim 1).
In the embodiment of the present invention (claim 2), a plurality (four in FIG. 2) is provided.

In the embodiment of the present invention, the control unit (C
Using the DMA transfer function which includes the TL) 311, working system main storage (MM) 2 ₀ other system main storage memory data (D _MM) of (MM) add features as to copy the 2 ₁ In the control unit (CTL) 311, the memory copy command receiving unit (CCR) 32 and the memory copy operation control unit (MCC) 33 are provided, and burst transfer control units (BTC) 316 and 317 are provided. Are arranged in parallel in a memory address register (MAR) 313 and a transfer byte number register (BCR) 314, respectively.

Memory address register (MAR) 3
13 and the transfer byte number register (BCR) 314
In the embodiment of the present invention, in order to be able to copy the memory data (D _MM ) of the entire storage area of the main storage device (MM) 2 (that is, from the start address (a _B ) to the end address (a _E )). The number of digits of the storable address and the transfer amount (the number of bytes) are expanded.

In this state, the control that is operating as the active system
Apparatus 10₀The control device 10 that has completed the diagnosis₁Main memory
(MM) 2₁Connected to the main memory (MM) 2₀To
All the stored memory data (D_MM), The main storage
(MM) 2₁When a request to execute a copy occurs,
System central control unit (CC) 1₀Is the system bus 11₀To
Channel control device (CHC) 3 via₀See, within
Department bus 34₀Pseudo input / output device (PIO) 31 via
₀Memory address register (MA
R) 313₀And a main storage device (MM) 2₀Of storage space
Start address (a_B) To the transfer address (a_T)
And a pseudo input / output device (PIO) 31₀Provided within
Transferred byte count register (BCR) 314₀To
Memory data (D_MM) Total storage capacity (n_MM) Transfer by
Number (n_T), And then a pseudo input / output device (PI
O) 31₀Command register (CMR) provided in
312 ₀To the memory copy command (cm_MC) To accumulate.

In the simulated input / output device (PIO) 31 ₀ , the control unit (CTL) 311 ₀ sends a command register (CM)
R) extracts 312 ₀ stored command to (cm), and transmits a memory copy command accepting unit (CCR) 32 _0.

Memory copy command receiving unit (CCR) 32
₀ analyzes the transmitted command (cm), when identifying that is other than the memory copy command (cm _MC) is returned to its as one likes controller (CTL) 311 _0, similar to the conventional operation Is executed, but when it is determined that the command is a memory copy command (cm _MC ), the memory copy operation control unit (MCC) 33
Start ₀ .

The activated memory copy operation control unit (MC
C) 33 ₀ is in such order as shown in FIG. 4, to perform the copy operation of the memory data (D _MM). The various signals shown in FIG. 4 are sent and stopped in synchronization with a system bus clock (not shown).

First, a memory copy operation control unit (MCC) 33
_0, the central controller (CC) 1 ₀ through the control line 31F ₁ of system bus 11 in _0, bus request signal for requesting the right to use the system bus 11 ₀ (BUSR
Q).

The central controller (CC) 1 ₀ receives the pseudo input device (PIO) 31 ₀ sent to the system bus 11 ₀ from the bus request signal (BUSRQ),
Analyzing the state of use of the system bus 11 ₀ confirms that it is in the unused state, the pseudo input device via the control line 31F ₂ system bus 11 in the ₀ (PIO) 31
₀ and returns a bus access permit signal to permit the right to use the system bus 11 ₀ (BROK).

[0037] In the pseudo input device (PIO) 31 _0, the control unit memory copying operation controller in the _{(CTL) 311 0 (MCC)} 33 0 is the central controller (CC) 1 ₀ from the system bus 11 in the ₀ Upon receiving the bus access allowable signal sent back via the control line 31F ₂ of (brok),
The transfer address (a _T = a _B ) stored in the memory address register (MAR) 313 ₀ is extracted, and the transmission bus 31E _A0 and the internal bus 34 are read as the read address (A _R ).
_The signal is transmitted to the system bus 110 via _0, and at the same time, a read signal (READ) is transmitted.

The main memory (MM) 2 ₀ receives the pseudo input device (PIO) 31 ₀ sent to the system bus 11 ₀ from the bus access permitted signal (brok), the pseudo input device (PIO) receiving a delivery completion of the read address _{(a R = a T = a} B) from 31 ₀ to the system bus 11 _0,
Received read address _{(A R = a T = a} B) to read out the unit data already stored (d _aT), sent as read data (D _R) on the system bus 11 _0, at the same time acknowledge signal (M
OK) and a response signal (ASW).

The transmitted read data (D _R = d _aT )
Channel control unit (CHC) 3 ₀ and the internal bus 34 ₀
By way of arriving at the pseudo input-output device (PIO) 31 _0. Pseudo output device (PIO) in 31 _0, the memory copy operation control unit (MCC) 33 ₀ is the central controller (CC) by sending Stop 1 ₀ bus access permit signal (brok), the response signal (ASW) , Read data (D _R = d
Create an acquisition timing of the _aT), the read data arriving from the internal bus _{34 0 (D R = d aT} ), receiving bus 31D _A0
Via the data buffer register (DBR) 315 ₀
To be stored.

It should be noted the central controller (CC) 1 ₀ After issuing the system bus 11 ₀ to the bus use right acceptable signal (brok), detects that the acknowledge signal (MOK) is sent to the system bus 11 ₀ sends stop bus access permit signal during transmission to the system bus 11 ₀ (bROK).

[0041] In the pseudo input device (PIO) 31 _0, the memory copy operation control unit (MCC) 33 ₀ is the central controller (CC) 1 ₀ from the system bus 11 ₀ bus use right in the back via Upon detecting the return stop allowable signal (brok), a system bus 11 ₀ to the read address during transmission and (a _R) and a read signal (rEAD) sends stop, main memory (MM) 2 ₀ in the start address ( It ends the extraction processing of the unit data (d _aT) from a _B).

The memory copy operation control unit (MCC) 33
₀Is a burst transfer control unit (BTC) 316₀And 3
17₀And a memory address register (MAR) 3
13 ₀The transfer address (a_T= A_B) Is a step
And the transfer byte number register (BC
R) 314₀The number of transfer bytes stored in (n_T= N_MM) Is
The value is kept as it is without subtraction.

Subsequently, a memory copy operation control unit (MCC) 3
3 _0, the central controller (CC) 1 ₀ through the control line 31F ₁ of system bus 11 within _0, the system bus 11 ₀
Bus use request signal (BUSR) for requesting the use right of
Q).

Central control unit (CC) 1₀Is the same as above
And a pseudo input / output device (PIO) 31 ₀The bus sent from
System request signal (BUSRQ), the system
Mbus 11₀Analyze the usage status of the
Is confirmed, the system bus 11₀Inside control line 31F
_TwoPseudo input / output device (PIO) 31 via₀To the cis
Tembus 11₀Bus use permission signal that grants the right to use
(BROK) is returned.

Pseudo input / output device (PIO) 31₀At
Is a memory copy operation control unit (MCC) 33₀But central system
Control device (CC) 1₀From system bus 11₀Control line inside
31F_TwoBus use right permission signal (B
ROK), the memory address register (MA)
R) 313₀The transfer address (a_T= A_B)
Extract and write address (A_W), The transmission bus 31E
_A0And internal bus 34 ₀Via the system bus 11₀
To send to.

At the same time, the memory copy operation control unit (MCC) 3
3 ₀ extracts unit data in stored in the data buffer register _{(DBR) 315 0 (d aT} ), transmit bus 31E
The system bus 11 via the _D0 and the internal bus 34 _{0 0}
The sends out a write data (D _W), via the control line 31F ₁ of system bus 11 within ₀ to a main memory (MM) 2 _0, and sends a write signal (WRITE).

The main memory (MM) 2 ₀ and 2 ₁ receives the central controller (CC) 1 ₀ sent to the system bus 11 ₀ from the bus access permitted signal (brok),
Pseudo output device (PIO) 31 ₀ from the system bus 11
The write address (A _W = a _T = a _B ) and the write data (D _W = d _aT ) that have been transmitted to ₀ are received, and the received unit data (d _aT ) is written into the write address (A _W). = A _T = a _B ), and sends an acknowledge signal (MOK) and a response signal (ASW).

[0048] Note that the central controller (CC) 1 ₀ After issuing the system bus 11 ₀ to the bus use right acceptable signal (brok), detects that the acknowledge signal (MOK) is sent to the system bus 11 ₀ sends stop bus access permit signal during transmission to the system bus 11 ₀ (bROK).

[0049] In the pseudo input device (PIO) 31 _0, the memory copy operation control unit (MCC) 33 ₀ is the central controller (CC) 1 ₀ from the system bus 11 ₀ bus use right in the back via Upon detecting the return stop allowable signal (brok), it sends stops a write address during transmission to the system bus 11 ₀ (a _W) and write signal (wRITE),
Get the response signal (ASW), main memory (MM) 2 ₀
And the unit data (d) to the address ₁ (a = a _B )
_aT ), the burst transfer control unit (B
TC) 316 ₀ and 317 ₀ to advance the transfer address (a _T = a _B ) stored in the memory address register (MAR) 313 ₀ by one step [a _T = a _T + 1 = a
_B + 1] and the transfer byte number register (BCR) 31
4 ₀ to the number of bytes transferred during the accumulation of the (n _T) to one subtracted [n
_{T = n T -1 = n MM} -1 ].

Thus, the pseudo input / output device (PIO) 31
₀Is the main storage device (MM) 2₀Start address in
(A_B) Is stored in the unit data (d_aT), The main storage
(MM) 2₁Within the same address (a_B)
And a pseudo input / output device (PIO) 31₀Notes in
Readdress register (MAR) 313₀Is the transfer address
Su (a_T), The main memory (MM) 2₀Storage area
The second address from the beginning (a _B+1) is accumulated,
The transfer byte number register (BCR) 314₀Forward to
Number of bytes (n_T), The main memory (MM) 2₀All of
Storage capacity (n_MM) Minus one (byte) less bytes
(N_MM-1) is accumulated.

Next, a memory copy operation control unit (MCC) 3
3 ₀ executes the process similar to that described above, the central controller (CC) 1 ₀ after acquiring the right to use the system bus 11 from _0, the read address _{(A R = a T = a} B +1)
And sends a read signal (READ) to the system bus 11 _0, main memory (MM) 2 ₀ forwarding addresses (a _T = a
_B +1) to extract the unit data already stored (d _aT), after storing the data buffer register (DBR) 315 _0,
The system bus 11 from the central controller (CC) 1 ₀ again ₀
After obtaining the right to use, the write address (A _W = a _T = a
And _B +1), and write data (D _W = d _aT), sends a write signal (WRITE) to the system bus 11 _0, main memory (MM) 2 ₀ and other system main storage (MM) 2 ₁
By storing the stored unit data (d _aT ) at the transfer address (a _T = a _B +1) of the main storage device (MM)
The second address (a _B +1) to store already unit data from the beginning of the 2 ₀ (d _aT), becomes that copied to main memory (MM) the same address 2 in ₁ (a _B +1), the pseudo input device memory address register (PIO) 31 in the ₀ (MAR) 313 ₀ the transfer address (a _T)
As, as a main memory device (MM) 2 ₀ from the beginning third address of the storage area of (a _B +2) is stored, also the transfer byte number register (BCR) 314 number of transfer bytes to ₀ (n _T), main memory (MM) 2 ₀ in the total storage capacity (n _MM) from the secondary (bytes) reduced the number of bytes (n _MM -
2) is accumulated.

Similarly, the main memory (MM) 2₀
Transfer address (a_T) Is stored in the unit data (d_aT)
To the main memory (MM) 2₁Each time you copy
Dress register (MAR) 313₀Forwarding address within
(A_T) By one step [a_T= A_T+1]
Transmission byte number register (BCR) 314₀Transfer bytes in
Number (n_T) Minus one [n_T= N_T-1]
Less (a_T) Is the last address (a_EReached), transfer by
Number (n_T) Becomes one byte, and the main storage device
(MM) 2₀Last address (a_EUnit data stored in)
Data (d_aT) To the main memory (MM) 2₁Finished copying on
After that, the transfer byte number register (BCR) 314 ₀Transfer within
Number of bytes (n_T) Is subtracted by one, and the number of transfer bytes (n
_T) Reaches zero bytes, the memory copy operation control unit (M
CC) 33₀Is the main storage device (MM) 2₀Total storage capacity of
(N_MM) Memory data (D_MM) To the main storage device (M
M) 2 ₁It is determined that the copying has been completed, and the control unit (CTL) 3
11₀To that effect.

The control unit (CTL) 311 ₀ is center creates an interrupt signal indicating completion of execution of a memory copy command (cm _MC) as an interrupt cause, via the control line 31F ₁ of system bus 11 within ₀ controller (CC) is sent to the 1 _0.

The central control unit (CC) 1 ₀ is a pseudo output device (PIO) 31 ₀ receives and analyzes the interrupt signals sent to the system bus 11 from _0, the memory copy command (c
Having identified the execution completion notification m _MC), to wait for the control unit 10 ₁ as a standby system.

As is apparent from the above description, the present invention is implemented.
According to the embodiment, the channel control device (CHC) 3₀Inside
Pseudo input / output device (PIO) 31₀In the past,
Channel controller (CHC) 3₀DMA transfer for diagnosis
After adding the memory copy function to the transfer function,
Control device (CC) 1₀Is a pseudo input / output device (PIO) 31
₀Memory copy command (cm_MC), Pseudo-in / out
Force device (PIO) 31 ₀Is the main storage device (MM) 2₀of
Total storage capacity (n_MM) Stored in memory data (D_MM)
To the main memory (MM) 2₁Execute the copying process
Central control unit (CC) 1₀Performs other processing,
Waiting for the reception of an interrupt signal for copying completion notification
You.

The pseudo input / output device (PIO) 31₀By
The copying execution time is the same as that of the conventional duplex control device 10.
And the central control unit (CC) 1₀Is a memory copy program
(P _MC0) Has been shortened compared to the case of executing

FIGS. 2 to 4 are merely an embodiment of the present invention, and various other modifications are considered. For example, in an embodiment of the present invention (Claim 2), as shown in FIG. 5, to extract the memory copy operation control unit (MCC) 33 ₀ is main memory (MM) read data from the 2 ₀ (D _R) In this case, the read address (A _R ) is changed to the transfer address (a
_T ) to (a _T +3) are sequentially advanced to continuously extract four unit data (d _aT ) stored in the transfer addresses (a _T ) to (a _T +3), and a plurality of data are provided. after storing in the data buffer register (DBR) 315 ₀ and, when stored in the main memory (MM) 2 ₀ and 2 _1, the write address (a _W), the transfer address (a _T) to again ( by sequentially incremented in a _T +3), four unit data extraction already (d _aT), by storing in succession to the same transfer address (a _T) to (a _T +3), copying execution The time can be further reduced.

[0058] In an embodiment of the present invention (claim 3) also bisects the main memory (MM) 2 ₀ in the entire storage area [start address (a _B) from the final address (a _E) up],
Channel control unit (CHC) pseudo input device 3 in the ₀ (PIO) 31 ₀ to one half region [for example causes the charge of the copying from the start address (a _B) until the intermediate address (a _M), the channel controller (CHC) 3 pseudo input device in ₁ (PIO) 31 ₁ in the other half region [for example causes the charge of the copying from the intermediate address (a _M) to a final address (a _E), both the pseudo input device ( The PIOs 31 ₀ and 31 ₁ copy the stored memory data (D _MM ) in their respective areas while competing for the right to use the system bus 11, thereby further reducing the required copying time. It becomes possible. Further, the duplexing control device to which the present invention is applied is not limited to the illustrated one, and various other modifications may be considered, but the effect of the present invention does not change in any case.

[0059]

As described above, according to the present invention, in the redundant control device, the copying operation time of the contents stored in the main storage device is greatly shortened, so that the single operation time is shortened, and the central processing unit is operated during copying. There is no danger that the processing capacity of the control device will be squeezed, and the reliability and the processing capacity of the redundant control device can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a redundant control device according to an embodiment of the present invention.

FIG. 3 is a pseudo input / output device in FIG. 2;

FIG. 4 is a diagram illustrating a main storage device copy sequence (for each single address) in FIG. 2;

FIG. 5 is a diagram exemplifying a main storage device copy sequence (each multiple address) in FIG. 2;

FIG. 6 shows a conventional dual control device.

7 is a process of copying a main storage device in FIG. 6;

[Explanation of symbols]

1, 100 Central control unit (CC) 2, 200 Main storage unit (MM) 3, 300 Channel control unit (CHC) 4 Input / output unit (IO) 10 Duplex control unit 11 System bus 12 C bus 31, 310 Pseudo input / output Device (PIO) 32 Memory copy command receiving unit (CCR) 33 Memory copy operation control unit (MCC) 34 Internal bus 311 Control unit (CTL) 312 Command register (CMR) 313 Memory address register (MAR) 314 Transfer byte number register ( BCR) 315 data buffer register (DBR) 316, 317 burst transfer controller (BTC) 31D _A, 31D _D receive bus 31E _A, 31E _D transmit bus 31F _1, 31F ₂ control lines 320 a memory copy instruction accepting unit 330 copying operation control means

Claims (4)

[Claims] 1. A duplicate control device comprising a duplicated central control device, a main storage device and a channel control device, each of which is provided for a function test of each of the channel control devices and has a direct memory access (DMA) function. Memory copy command receiving means for receiving / identifying a memory copy command requesting copying of the storage contents of the active main storage device to another system main storage device; and the memory copy command receiving means When the memory copy command is received from the active system central control device, the unit data stored in each address of the active system main storage device is sequentially extracted, and the same unit data as the other system main storage device is extracted. After the data copy operation to be stored at the address is continuously performed on all the storage areas of the main storage device, the completion of the memory copy operation is determined by the current And a memory copying operation control means for notifying a central control device of the system. 2. The copying operation control means continuously extracts each unit data stored at a plurality of continuous addresses of the active main storage device and corresponds to each of the other main storage devices. 2. The main storage device copying method according to claim 1, wherein the data is stored continuously at a plurality of addresses. 3. The copying operation control means in each of the pseudo input / output devices provided in the channel control devices of the two systems shares a partial storage area provided by dividing the entire storage area of each of the main storage devices into two. The data stored in each assigned partial storage area of the active main storage device is copied in parallel to each corresponding partial storage area of the other main storage device. Item 2. The main storage device copying method according to Item 1. 4. The copying operation control means according to claim 1, wherein each of the unit data extracted from each address of the active main storage device is
2. The main storage device copying method according to claim 1, wherein the data is stored in parallel at the same address of the main storage devices of the two systems.