JPH11259320A - Fault detecting system for data buffer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely detect the single cell fault occurrence of any arbitrary memory cell when constituting a data buffer by using the memory cells of multi-bit width. SOLUTION: For each data security unit WD<X, 0.3> (X=0 to 3), a parity generating means 14 adds correspondent parity data WD<X, 4> to data WD<0-3, 0-3> to be written through a data bus 25 for write to a data buffer 6 by a data transfer means 13 and the bits consisting of these data check units WD<X, 0.4> are stored in mutually different memory cells 17, 18, 19, 20 and 21. In the data read, a parity check means 15 performs checks these memory cells for each data check unit. Thus, since the bits consisting of the data check unit are read out of different memory cells, the fault of any arbitrary one cell becomes a one-bit error within the data check unit without fail and the single cell fault is surely detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improving the reliability of a data buffer constituted by using a plurality of storage elements having a multi-bit width. More specifically, the present invention relates to the distribution of data and parity information to storage elements and the distribution thereof. It relates to a circuit configuration to be realized.

[0002]

2. Description of the Related Art To ensure the reliability of a data buffer at present, parity data is generated for each data security unit of data to be written, written to the data buffer at the same time as data, and read data is read simultaneously when data is read from the data buffer. A method of checking with read parity data is often used.

[0003]

In the above prior art,
It is not considered how the write data and the parity data are stored in the storage elements forming the data buffer. For this reason, when the data buffer is configured using a storage element having a multi-bit width, if the size of one data security group including valid data and parity data is smaller than the bit width of the storage element, they are stored in the same storage element. Will be stored. For this reason, when one element failure occurs in the storage element constituting the data buffer, the data error in the data security group extends to many bits, and the data security by the parity data having only one-bit data error detection capability. The method has a problem that a data error due to the one-element failure may not be detected.

[0004]

SUMMARY OF THE INVENTION In a computer system having a data buffer according to the present invention, the data buffer comprises a plurality of storage elements having a multi-bit width. The code that guarantees data is parity data for each data security unit as in the conventional method, but the data bus that connects the storage element that forms the data buffer and the circuit that controls data transfer is the data bus that makes up the data security group. The bits are stored in different storage elements. Since each bit constituting the data security group is stored in a different storage element, when one element failure occurs in any storage element, the data read from the data buffer by the circuit for controlling data transfer is stored in the data security group. Always within 1
Since a bit error occurs, by checking the read data with the parity data, a data error due to a failure of one of the storage elements can be always detected.

[0005]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram showing an example of the configuration of a disk control device to which the present invention is applied. Disk control device 1
Is connected to the system bus 2 and the disk drive 3 and is a control processor CPU 4; data transfer means 5 for executing data transfer between the system bus and the disk drive in accordance with instructions from the CPU 4; It comprises a data buffer 6 for absorbing a speed difference between a system bus and a disk drive, a system bus interface circuit 7, a drive interface circuit 8, and internal buses 9, 10, 11, and 12 connecting these.

The data transfer means 5 includes a data transfer control circuit 13 for controlling the data transfer means, a parity generation means 14 for generating parity data which is a data security code when data is written to the data buffer, and a data transfer control circuit 13 for reading data from the data buffer. It comprises a parity check means 15 for checking the validity of the read data using the parity data.

Regardless of whether the sender of the data is the system bus or the disk drive, the data is once stored in the data buffer 6 and synchronized with the sender and the receiver by the data transfer control means 13. The data transfer to the receiver side is performed. The validity of the data at this time is determined by adding parity data to the data to be written to the data buffer 6 by the parity generation means 14 and using the parity data to read the data from the data buffer. Confirm by inspection. If the data inspection determines that the data is abnormal, the result is reported to the data transfer control means 13 and the CPU 4 by the data error report signal 16 (hereinafter referred to as DATAERR). Judge and retry the data transfer.

FIG. 2 shows the details of the connection of the data transfer control means, the data buffer, the parity generation means, and the parity check means. The data buffer unit 6
bit × 1 kw semiconductor memory elements 17, 18, 19,
20, 21 (hereinafter referred to as RAMs 0, 1, 2, 3, 4)
It consists of.

Each RAM stores data transfer control means 13 and W
write Enable signal 22 (hereinafter WE), Rea
d Enable signal 23 (hereinafter referred to as RE), Address
Signals 24 (hereinafter referred to as ADR <0-9>) are connected by three kinds of control signals, which are controlled by the data transfer control means 13.

The data transfer control means 13 and the data buffer section 6 are connected by a write data bus 25 and a read data bus 26, and transmit and receive data to and from the data buffer through these buses. The write data bus 25 is connected to the parity generation means 14, and the read data bus 26 is connected to the parity check means 15.

FIG. 3 shows the details of the parity generation means 14. Hereinafter, the connection between the write data bus and the data buffer will be described in detail with reference to FIGS.

The write data bus 25 has WD00, W
D01, WD02, WD03, WD10 ... WD2
3, 16bi represented by WD31, WD32, and WD33
t (hereinafter referred to as WD <0-3, 0-3).
Notation> ). The write data bus 25 is WD <
4b represented by X, 0-3> (X = 0, 1, 2, 3)
It is the unit of data security. Each data line constituting the data security unit has a different RAM.
Connected to enter the input of That is, RAMY (Y
Are 0, 1, 2, 3) for the write data bus line WD <
0-3, Y> are connected.

The parity generation means 14 has an odd parity generation circuit 29 corresponding to each data security unit. Each odd parity generation circuit 29 is connected to a 4-bit bus WD <X, 0-3> constituting a data security unit. Are connected to generate corresponding odd parity data. Further, each odd parity generation circuit 29 has WD04, WD14, WD2 corresponding to each data security unit.
4 and WD 34 are connected to the input of the RAM 421 by four write parity data lines 27 (hereinafter referred to as WD <0-3, 4>). Note that the configuration of the odd-number parity generation circuit 29 has been described in Document 1, and thus description thereof is omitted here.

FIG. 4 shows the details of the parity check means 15. The details of the connection between the read data bus 26, the data buffer unit 6, and the parity check unit 15 will be described below with reference to FIGS.

The read data bus 26 has RD00, R
D01, RD02, RD03, RD10 ... RD2
16bi represented by 3, RD31, RD32, and RD33
t (hereinafter referred to as RD <0-3, 0-3>). This read data bus signal line
Each of the signal lines WD <0-
3,0-3>. That is, the read data bus line RD <0-3, Y> is connected to the RAM Y (Y is 0, 1, 2, 3) so as to correspond to the write data bus line.
Can read the contents written in the data buffer through the write data bus correctly through the read data bus.

The parity check means 15 is connected to the RAMs 0 to 3 by the read data bus 26 and the four read data parity lines 28 corresponding to each data security unit.
It is connected to the RAM 4 by RD <0-3,4>. The parity check means 15 is composed of four parity check circuits 30 corresponding to each data security unit. Each parity check circuit has a 4-bit read data line RD <X, 0-3> constituting the data security unit. And the read data parity line RD <X, 4> (X = 0, 1, 2,
3) is connected to check the read data.

FIG. 5 shows how parity is added to one cycle of write data to the data buffer 6 and data is stored in each RAM by the circuit configuration described above. . Hereinafter, it will be described with reference to FIG. 5 that the failure of any one element of the RAM can be detected by the present invention.

The write data bus is 16 bits wide, and the write data for one cycle to the data buffer 6 is D00, D01, D02, D03, D13,.
D23, D30, D31, D32, D33 (hereinafter D <0
−3, 0-3>). Here, XX of DXX corresponds to the write data bus line.

With the above-described circuit configuration, this write data is 4-bit data of D <X, 0-3> (X = 0, 1, 2, 3).
Are the data security units 31, and the odd parity data 32 corresponding to each is generated by the parity generation means 14. Then, the 4-bit data constituting the data security unit 31 is written to different RAMs, and the odd-number parity data 32 is written to the RAM 4. On the other hand, when data is read from the data buffer 6, the data read from the RAM is checked by the parity check unit 15 for each parity check unit 33 and the validity of the read data is confirmed by the above-described circuit configuration.

By performing the data storage and the read data check in this manner, the data read from the data buffer unit 6 is parity data regardless of what type of failure occurs in any one element of the RAM. 5 bit parity check unit 33 including 1 bit
In this case, a one-bit error always occurs, so that the parity check means 15 can always detect an abnormality in the read data.

[0022]

As described above, according to the present invention, in a computer system having a data buffer constituted by a storage element having a multi-bit width, a data error due to a failure of an arbitrary storage element constituting the data buffer is always detected. There is an effect of providing a data security method.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing details of connection between a data transfer control unit and a storage element forming a data buffer in the embodiment shown in FIG. 1;

FIG. 3 shows details of a parity generation unit shown in FIG. 1;

FIG. 4 shows details of a parity check unit shown in FIG. 1;

FIG. 5 is a diagram showing how parity is added to write data and data is distributed to and stored in each storage element in the embodiment shown in FIG. 1;

[Explanation of symbols]

D <0-3>: a bundle of signal lines named D0, D1, D2, D3; D <X, 0-3>: a bundle of DX0, DX1, DX2, DX3, D <0-3 , 0-3>... D00, D01, D02, D0
3, D10, D11, D12, D13,... D2
3, a bundle of D30, D31, D32 and D33.

Claims (4)

[Claims] A data buffer for holding data; a data transfer means for writing and reading data to and from the data buffer; a bus connecting the data buffer and the data transfer means; In a computer system comprising a microprocessor for controlling means, the computer system writes / reads M × N bits of valid data in one cycle of data transfer to / from a data buffer. The transfer circuit is configured by a plurality of memory elements of × L words (M and L are integers), and the transfer circuit can transfer M × (N + 1) bits (N is an integer) in one transfer cycle. It has a bus width of M × (N + 1) bits, and is used for one cycle of valid data written to the data buffer. , A parity bit, which is a data security code, is added to each N bits, and the parity bit is used as a data security unit. The N bits of the valid data and the 1 bit of the parity bit which constitute the security unit do not overlap each other so that they do not overlap.
A computer system characterized in that data is separately distributed and written in +1 memory elements. 2. The computer system according to claim 1, wherein when reading data from the data buffer,
A computer system for verifying the validity of data distributed and stored in the (N + 1) memory elements by checking parity for each security unit. 3. A means for notifying a microprocessor controlling the data transfer means when it is determined as a result of the data validity check according to claim 2 that the data is abnormal. Computer system. 4. A data storage system comprising a computer system and data storage means according to claim 1 and 2, wherein data transfer between an external data source and data storage means is performed by ON THE FLY according to an instruction of said microprocessor. A data storage system that ensures data reliability by the above data security method.