JPH11251120A - Manufacture of laminated chip varistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form glass insulating films having little variations in thickness on the four side faces of laminated varistor elements with few number of processes, and at the same time, to reduce the manufacturing cost of a laminated chip varistor. SOLUTION: While a holding plate 40 holds a plurality of laminated varistor elements 12, the plate 40 is dipped into a glass paste 42, from one side of the exposed surfaces of the internal electrodes of the varistor elements 12. After being dipped, the elements 12 are pulled up and the glass paste 42 adhering to the exposed surfaces of the internal electrodes is wiped off with filter paper, and then the exposed surfaces are dried. Then the paste for external electrode is applied to the exposed surface of the internal electrodes and the glass paste 42 and the paste for external electrode are baked to the elements 12. At the baking of the paste, the varistor elements 12 are housed in the cavity of a plate for baking in standing states.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a multilayer chip varistor, and more particularly to a method for manufacturing a multilayer chip varistor used for surge absorption, for example.

[0002]

2. Description of the Related Art FIG. 10 is a perspective view showing an example of a laminated chip varistor, and FIG. 11 is a schematic sectional view thereof. The multilayer chip varistor 10 includes a multilayer varistor element 12. The multilayer varistor element 12 includes a ceramic layer 14 formed of, for example, a zinc oxide-based material and a plurality of internal electrodes 16.
As a laminate. The internal electrodes 16 are formed so as to be alternately exposed at both ends in the longitudinal direction of the multilayer varistor element 12. External electrodes 18 are formed on both end surfaces of the multilayer varistor element 12 where the internal electrodes 16 are exposed. Therefore, the internal electrodes 16 are alternately connected to these external electrodes 18. Further, on the side surface of the laminated varistor element 12 where the external electrode 18 is not formed, the glass insulating film 2 is formed.
0 is formed. The external electrode 18 includes an electrode layer 22 formed of Ag or the like, and a plating layer 24 is formed of Sn, Ni, or the like in order to prevent solder cracking that occurs at the time of soldering.

[0003] Such a multilayer chip varistor 10 is a voltage non-linear resistor whose resistance rapidly decreases when the voltage rises. It plays an important role as a surge absorber that protects equipment. Above all, a multilayer chip varistor can be surface-mounted, and a device with a low varistor voltage can be stably manufactured by thinning and high stacking, and a small device with a large surge current resistance can be manufactured. For this reason, electronic devices have begun to be widely used in recent years due to the trend of miniaturization, surface mounting, and low voltage of electronic devices.

However, when the glass insulating film 20 is not provided, the multilayer chip varistor 10 is susceptible to acid and alkali,
There is a problem in that surface leakage occurs due to the flux reducing action at the time of soldering. Further, since the resistor used in the multilayer chip varistor 10 is a semiconductor, the electrical resistance is lower than that of the insulator, and when plating the external electrode 18, the resistance of the multilayer varistor element 12 without the external electrode 18 is increased. There is a problem that a plating layer is also formed on the side surface. Therefore, in order to solve such a problem, a glass insulating film 20 is formed as a protective film on the side surface of the laminated varistor element 12 where the external electrode 18 is not formed.

In order to manufacture the laminated chip varistor 10, a ceramic green sheet to be used as a material of a resistor having voltage non-linearity is prepared. On this ceramic green sheet, print the electrode paste that will be the internal electrode,
A plurality of ceramic green sheets on which the electrode paste is printed are laminated and pressed. The laminated and pressed ceramic green sheets are cut into chips so that the electrode pastes for the internal electrodes are alternately exposed at both ends. Then, by firing the obtained chip, the laminated varistor element 12 is obtained.

In order to form the glass insulating film 20 on the laminated varistor element 12, as shown in FIG. 12, a glass paste is printed on one side A of the laminated varistor element 12 by screen printing. Then, the glass paste printed on the multilayer varistor element 12 is dried. Such a process is equivalent to the other three steps of the multilayer varistor element 12.
The operations are sequentially performed on the three side surfaces B, C, and D. In other words, by printing and drying the glass paste four times,
A glass paste layer is formed on the side of the multilayer varistor element 12 where the internal electrodes 16 are not exposed. Further, an external electrode paste is applied to the surface of the multilayer varistor element 12 where the internal electrodes 16 are exposed. Then, the electrode layer 22 and the glass insulating film 20 are formed by baking the external electrode paste and the glass paste on the laminated varistor element 12. Further, the plating layer 24 is formed on the electrode layer 22.
Are formed to form the external electrodes 18 and the multilayer chip varistor 10 is completed.

Further, as shown in FIG. 13, a glass paste may be transferred to the side surface of the multilayer varistor element 12.
In this case, a glass paste layer 28 is formed on the transfer pad 26 and pressed against the side surface of the multilayer varistor element 12, whereby the glass paste layer 28 is transferred. At this time, since the transfer pad 26 is pressed so as to surround the multilayer varistor element 12, a glass paste layer 28 is formed over three side surfaces of the multilayer varistor element 12, as shown in FIG. Then, the glass paste layer 28 formed on the multilayer varistor element 12 is dried. Such a process is performed on the opposite side surface of the multilayer varistor element 12, and the four side surfaces of the multilayer varistor element 12 are covered with the glass paste layer 28 as shown in FIG. Next, as shown in FIG. 16, an external electrode paste 30 is applied to the surface of the multilayer varistor element 12 where the internal electrodes 16 are exposed. And paste 3 for external electrodes
0 and the glass paste layer 28 are laminated with the varistor element 12
The electrode layer 22 and the glass insulating film 20 are formed by baking. Further, the plating layer 2 is formed on the electrode layer 22.
4, the external electrodes 18 are formed, and the multilayer chip varistor 10 is completed.

[0008]

However, when a glass paste layer is formed by screen printing, since the glass paste must be printed on the four surfaces of the laminated varistor element, this printing and drying process is repeated four times. Need to be made, which causes an increase in cost. When the glass paste layer is formed by transfer, the glass paste layers can be formed on four surfaces of the multilayer varistor element by two transfers. However, when the chip size of the multilayer varistor element increases, the glass paste layer becomes There is a problem that the wraparound to the side surface is not stable, the transfer amount of the glass paste layer on the side surface varies, and the film thickness defect and the appearance defect increase.

Further, in any of the methods, since the glass paste is applied while the laminated varistor elements are laid on a plate, the occupied area occupied by one laminated varistor element is large, and the number that can be processed at one time is large. Less,
This was causing cost increase.

Therefore, a main object of the present invention is to form a glass insulating film having a small variation in thickness on the four side surfaces of a laminated varistor element in a small number of steps, and to reduce the manufacturing cost. An object of the present invention is to provide a method for manufacturing a chip varistor.

[0011]

According to the present invention, there is provided a step of preparing a laminated varistor element having internal electrodes exposed at both ends, and immersing the laminated varistor element in a glass paste from one side of the internal electrode exposed surface of the laminated varistor element. The glass paste adhered to the exposed surface of the multilayer varistor element, the step of drying the glass paste adhered to the laminated varistor element, and the step of drying the glass paste adhered to the laminated varistor element for the external electrode. By applying the paste and baking the glass paste and the external electrode paste on the laminated varistor element, the external electrode connected to the internal electrode is formed on the varistor element, and the glass insulating film is formed on the surface other than the external electrode forming portion. Is a method for manufacturing a laminated chip varistor. In this method for manufacturing a multilayer chip varistor, in the step of dipping the multilayer varistor element in a glass paste,
When the distance between the two internal electrode exposed surfaces is L and the dimension of the external electrode formed on the side surface other than the internal electrode exposed surface of the multilayer varistor element is e, the immersion depth D of the multilayer varistor element in the glass paste is D May be in the range of Le−D <L. Further, after the step of drying the glass paste, a step of dipping the laminated varistor element in the glass paste from the other side of the internal electrode exposed surface of the laminated varistor element, and a step of immersing the glass paste adhered to the internal electrode exposed surface of the laminated varistor element. A wiping step and a step of drying the glass paste adhered to the laminated varistor element, wherein the distance between the two internal electrode exposed surfaces of the laminated varistor element is L, and the immersion depth of the laminated varistor element in the glass paste D may be in the range of D ≧ L / 2. Further, in order to bake the glass paste and the external electrode paste on the laminated varistor element, it is preferable to store the laminated varistor element coated with the glass paste and the external electrode paste in a cavity formed in the baking plate so as to stand. .

By immersing the laminated varistor element in the glass paste from one of the exposed surfaces of the internal electrodes, the glass paste can be adhered to the exposed surfaces of the internal electrodes and the side surfaces on which the internal electrodes are not exposed. Then, by wiping off the glass paste attached to the exposed surface of the internal electrode, an electrical connection between the external electrode and the internal electrode can be obtained. By immersing the laminated varistor element in the glass paste, a glass insulating layer having a stable thickness can be formed regardless of the chip size. The immersion depth D of the laminated varistor element in the glass paste is L
By setting the range of −e <D <L, the glass paste can be adhered to the side surface of the laminated varistor element by one immersion except for the portion where the external electrode is formed. Further, the immersion depth D of the laminated varistor element in the glass paste is defined as D ≧
By setting the range of L / 2, a glass insulating layer having a stable thickness can be formed on the side surface of the laminated varistor element by immersing in the glass paste from both sides of the two internal electrode exposed surfaces. Further, the laminated varistor element is stored in the cavity of the baking plate in an upright position, and the glass paste and the external electrode paste are baked, so that the area occupied by one laminated varistor element on the baking plate is reduced. Can increase the amount of multilayer chip varistors that can be manufactured.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to manufacture a laminated chip varistor 10 shown in FIGS. 10 and 11, a laminated varistor element 12 is immersed in a glass paste, and the glass paste adhered to an exposed surface of an internal electrode is wiped off. An example of a method for manufacturing the multilayer chip varistor 10 according to such a method will be described below.

[0015]

EXAMPLES (Example 1) First, as a raw material for the ceramic layer 14 of the multilayer varistor element 12, against _{ZnO100, Bi 2 O 3 1.0mol%} , MnO0.5mol
%, CoO 0.5 mol%, SiO ₂ 1.0 mol%,
B ₂ O ₃ 0.1 mol%, Sb ₂ O ₃ 0.5 mol%,
100 ppm of Al ₂ O ₃ was blended. The obtained compounded raw materials were mixed and pulverized by a ball mill for 20 hours, dewatered, dried and granulated with a # 60 sieve. 750 ° C
For 2 hours, the resulting calcined product was roughly pulverized, and then mixed and pulverized again with a ball mill to obtain a slurry. The slurry was dewatered and dried to obtain a powder.

A solvent, a binder and a dispersant were added to the powder, a 50 μm-thick sheet was formed by a doctor blade method, and the sheet was punched into a predetermined size to obtain a green sheet. Part of this green sheet is Pt
The paste was printed by a screen printing method to form an internal electrode pattern. A predetermined number of the green sheets on which the internal electrode patterns were formed were stacked such that the internal electrode lead portions were alternately arranged, and were pressed under a pressure of ² ton / cm ² to form a laminate. This laminate was cut into chips of a predetermined size. After the obtained chip is heat-treated at 500 ° C. to remove the binder, it is baked at 1000 ° C. for 3 hours,
The laminated varistor element 12 was obtained.

As shown in FIG. 1, the obtained multilayer varistor element 12 was attached to a flat holding plate 40 to which an adhesive rubber was attached. At this time, the exposed surface of the internal electrode 16 of the multilayer varistor element 12 was attached to the holding plate 40. Then, the holding plate 40 is placed on the glass paste 4.
2 and the laminated varistor element 12 is
2 was immersed. At this time, the holding plate 40 and the surface of the glass paste 42 were arranged so as to be parallel, and the holding plate 40 was brought close to the glass paste 42 in this state.
As the glass paste 42, a lead borosilicate glass paste was used.

The laminated varistor element 12 is glass paste 4
2, the immersion depth D is set such that Le−D <L <L, as shown in FIG. Here, as shown in FIG. 10, L is the distance between the exposed surfaces of the two internal electrodes 16 of the multilayer varistor element 12, and e is formed on the side surface of the multilayer varistor element 12 where the internal electrodes 16 are not exposed. Are the dimensions of the external electrode 18.

The laminated varistor element 12 is glass paste 4
After immersion in 2, the holding plate 40 is given an impact,
The glass paste 42 excessively attached to the laminated varistor element 12 was shaken off. Then, as shown in FIG. 3, the glass paste 4 attached to the exposed surface of the internal electrode 16 of the multilayer varistor element 12 is placed on the filter paper 44 together with the holding plate 40.
2 was wiped off.

After that, the holding plate 40 was put in an oven, and the glass paste 42 attached to the side surface of the laminated varistor element 12 was dried at 100 ° C. Then, an Ag paste 46 serving as the electrode layer 22 of the external electrode 18 is applied to the exposed surfaces of the internal electrodes 16 at both ends of the multilayer varistor element 12,
The laminated varistor element 12 was held on a baking plate 48 made of alumina. As shown in FIG. 4, a plurality of cylindrical cavities 50 are formed in the baking plate 48, and the stacked varistor elements 12 are housed in the cavities 50 so as to stand. That is, as shown in FIG. 5, the laminated varistor element 12 was housed in the cavity 50 such that the surface to which the Ag paste 46 was applied was upside down.

Then, at 800 ° C., a glass paste 42
And the Ag paste 46 are baked on the laminated varistor element 12 to form the glass insulating film 20 and the electrode layer 2 of the external electrode 18.
2 was formed. Further, the electrode layer 22 is formed by electroplating.
The resultant was subjected to Ni plating and Sn plating to form a plating layer 24 to obtain a multilayer chip varistor 10.

In the method of manufacturing the multilayer chip varistor 10, the immersion depth D of the multilayer varistor element 12 is set to be Le−D <D
By doing so, the glass paste 42 can be attached to at least all the side surfaces except the portion where the external electrode 18 is formed by only one dipping. Therefore, the manufacturing process can be simplified and the manufacturing cost can be reduced as compared with the case where the glass paste is attached by conventional screen printing or transfer.

By setting D <L, the glass paste 42 does not adhere to the holding plate 40, and the glass paste 42 does not adhere to the exposed surface of the internal electrode 16 held by the holding plate 40. Further, the holding plate 4
The glass paste 42 adheres to the end of the multilayer varistor element 12 on the opposite side to the glass paste 42. The glass paste 42 on this surface is wiped off with a filter paper 44.
2 is absorbed by the filter paper 44, and the exposed surface of the internal electrode 18 can be easily exposed. Therefore, by forming the external electrodes 18 at both ends of the multilayer varistor element 12, the internal electrodes 16 and the external electrodes 18 are connected. If the glass paste 42 remains adhered, the external electrode 18 and the internal electrode 16 cannot be connected to each other, and the surge immunity, which is an important characteristic of the varistor, is reduced.
If 0 is formed, it is possible to prevent a decrease in surge resistance.

Further, the laminated varistor element 12 to which the glass paste 42 and the Ag paste 46 are adhered is housed upright in the cavity 50 of the baking plate 48 so that the lamination can be performed using one baking plate 48. The number of chip varistors 10 can be increased. That is, since the distance L between the exposed surfaces of the internal electrodes 16 opposed to each other is usually longer than the other dimension W in the width direction and the dimension T in the height direction, the stacked varistor element 12 is housed so as to stand up. The area occupied on the printing plate 48 is smaller than when the elements 12 are arranged in another direction. Therefore, a large number of laminated varistor elements 12 can be held on one baking plate 48, and the number of laminated chip varistors 10 obtained from one baking plate 48 can be increased.

Further, since the laminated varistor element 12 is housed in the cavity 50 so that the Ag paste 46 for the external electrode is in contact with the bottom surface of the cavity 50, the side surface on which the glass paste 42 adheres. Does not contact the baking plate 48. Therefore, it is possible to prevent the molten glass from adhering to the baking plate 48 in the baking step. It should be noted that the multilayer varistor element 12 is housed in the cavity 50 by:
This is to prevent the multilayer varistor element 12 from falling down.
Therefore, the shape of the cavity 50 is not limited to the cylindrical shape, and may be another shape such as an elliptical shape or a polygonal shape.

(Embodiment 2) As shown in FIG. 6, a through hole is formed in a rubber-like holding plate 52, and the holding plate 52
Utilizing the elasticity of the multilayer varistor element 12
Was held. The laminated varistor element 12 held by the holding plate 52 was immersed in the glass paste 42 from one side of the exposed surface of the internal electrode 16. At this time, as shown in FIG. 7, the immersion depth D of the multilayer varistor element 12 is D
= L / 2 to 2L / 3.

The varistor element 1 laminated on the glass paste 42
After immersion, the holding plate 52 was shocked to shake off the excessively adhered glass paste. Then, the glass paste 42 attached to the exposed surface of the internal electrode 16 of the multilayer varistor element 12 was wiped off with a filter paper 44. After that, put the holding plate 52 in the oven,
The glass paste was dried at ℃. Multilayer varistor element 1
2 was extruded upward or transferred to another holding plate 52, and the operations of the immersion, wiping, and drying were performed by reversing the direction of the laminated varistor element 12.

At this time, by setting the immersion depth D of the multilayer varistor element 12 to be in the range of L / 2 to 2L / 3, the first immersion allows the side face of the multilayer varistor element 12 as shown in FIG. The glass paste 42 can be attached to the middle part. Also, by the second immersion, FIG.
As shown in (1), the glass paste 42 can be applied to the entire side surface of the multilayer varistor element 12 so as to overlap at the center of the multilayer varistor element 12.

Ag for the external electrode is formed on the exposed surface of the internal electrode 16 of the laminated varistor element 12 to which the glass paste 42 is adhered.
The paste was applied and baked in the same manner as in Example 1 to produce a multilayer chip varistor 10.

In the method of manufacturing the laminated chip varistor 10, the glass paste 42 can be adhered to the entire side surface of the laminated varistor element 12 by immersion twice, and compared with the case where the glass paste is adhered by screen printing. The process can be simplified. Further, even in the case of applying the glass paste by transfer, when the chip size of the multilayer varistor element 12 is increased, the transfer and drying of the glass paste are required on the four side surfaces.
In the method of this embodiment, regardless of the chip size, 2
The glass paste 42 can be applied to the side surface of the laminated varistor element 12 by the repeated immersion.

[0031]

According to the present invention, the step of applying the glass paste can be simplified as compared with the conventional method of manufacturing a multilayer chip varistor. Moreover, a glass insulating film having a substantially uniform thickness can be formed on the entire side surface of the multilayer varistor element regardless of the size of the chip. Further, by storing the laminated varistor elements in the cavity of the baking plate so as to stand up, the number of laminated chip varistors that can be manufactured by one baking can be increased, and the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is an illustrative view showing a step of immersing a multilayer varistor element in a glass paste in a method of manufacturing a multilayer chip varistor of the present invention.

FIG. 2 is an illustrative view showing an immersion depth when a laminated varistor element is immersed in a glass paste;

FIG. 3 is an illustrative view showing a step of wiping a glass paste adhered to an end portion of the multilayer varistor element;

FIG. 4 is a plan view showing a baking plate for baking a glass paste and an Ag paste on a laminated varistor element.

FIG. 5 is an illustrative view showing a state in which a laminated varistor element is housed in a cavity of the printing plate shown in FIG. 4;

FIG. 6 is an illustrative view showing a step of immersing a multilayer varistor element in a glass paste in another method for manufacturing a multilayer chip varistor of the present invention.

FIG. 7 is an illustrative view showing a immersion depth when a laminated varistor element is immersed in a glass paste;

8 is a perspective view showing a state of the glass paste attached to the laminated varistor element at the immersion depth shown in FIG.

FIG. 9 is a perspective view showing a state of the glass paste attached to the multilayer varistor element when the multilayer varistor element is immersed in glass paste from both sides.

FIG. 10 is a perspective view showing an example of a multilayer chip varistor.

FIG. 11 is an illustrative sectional view of the multilayer chip varistor shown in FIG. 10;

FIG. 12 is an illustrative view showing a step of attaching a glass paste to a laminated varistor element by conventional screen printing.

FIG. 13 is an illustrative view showing a step of attaching a glass paste to a laminated varistor element by conventional transfer.

14 is a perspective view showing a state in which a glass paste layer is transferred from one side surface of the multilayer varistor element by the transfer shown in FIG.

FIG. 15 is a perspective view showing a state in which a glass paste layer is transferred from both side surfaces of the multilayer varistor element by the transfer shown in FIG.

16 is a perspective view showing a state in which a paste for external electrodes is applied to the multilayer varistor element shown in FIG.

[Explanation of symbols]

 Reference Signs List 10 multilayer chip varistor 12 multilayer varistor element 14 ceramic layer 16 internal electrode 18 external electrode 20 glass insulating film 22 electrode layer 24 plating layer 40 holding plate 42 glass paste 44 filter paper 46 Ag paste 48 baking plate 50 cavity 52 holding plate

Claims (4)

[Claims] A step of preparing a multilayer varistor element having internal electrodes exposed at both ends; a step of dipping the multilayer varistor element in a glass paste from one side of the internal electrode exposed surface of the multilayer varistor element; Wiping the glass paste adhered to the internal electrode exposed surface of the device; drying the glass paste adhered to the laminated varistor device; applying an external electrode paste to the two internal electrode exposed surfaces of the laminated varistor device A coating step, and baking the glass paste and the external electrode paste on the laminated varistor element, whereby an external electrode connected to the internal electrode is formed on the varistor element, and a surface other than the external electrode forming portion is formed. A method for manufacturing a laminated chip varistor, wherein a glass insulating film is formed on the substrate. 2. In the step of immersing the multilayer varistor element in the glass paste, a distance between two of the internal electrode exposed surfaces of the multilayer varistor element is set to L, and a distance other than the internal electrode exposed surface of the multilayer varistor element is set. When the dimension of the external electrode formed on the side surface is e, the immersion depth D of the laminated varistor element in the glass paste is:
The method for manufacturing a multilayer chip varistor according to claim 1, wherein a range of Le−D <L is satisfied. 3. A step of dipping the laminated varistor element into the glass paste from the other side of the internal electrode exposed surface of the laminated varistor element after the step of drying the glass paste, A step of wiping the glass paste adhered to the electrode exposed surface, and drying the glass paste adhered to the laminated varistor element, wherein a distance between the two internal electrode exposed surfaces of the laminated varistor element is L. 2. The method for manufacturing a multilayer chip varistor according to claim 1, wherein the immersion depth D of the multilayer varistor element in the glass paste is in a range of D ≧ L / 2. 4. The laminated varistor element in which the glass paste and the external electrode paste are applied to a cavity formed in a baking plate in order to bake the glass paste and the external electrode paste onto the laminated varistor element. Is stored as if standing up,
A method for manufacturing a multilayer chip varistor according to claim 1.