JPH1124991A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the system ability of a data processor having large capacity memory. SOLUTION: A data comparison circuit 110 is provided for comparing data on a head word in a write line with other data at the time of writing data in a cache memory 1300 and for outputting a compared result in accordance with the continuously matched number of words from the head word. When data transferred to a bus controller 1200 continuously have the same values at the time of write back and block transfer by a special instruction, respective pieces of data which are continuously matched are compressed into data of a 1/2 word or one work and into the number of transfer times from the head word, and they are outputted to the bus controller 1200 thus a bus is released to the other processing until the reading of next data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processor, and more particularly to a data processor having a high-speed cache memory.

[0002]

2. Description of the Related Art Conventionally, this type of data processing apparatus has a high-speed cache memory and a main memory having a low operation speed.
It is used to match the memory and improve the apparent access time seen from the microprocessor. For example, FIG. 8 is a partial block diagram showing an example of a data transfer unit between a microprocessor and a bus controller in this conventional data processing device. A data transfer unit in this conventional data processing device includes a microprocessor 100, a bus controller 200, and a cache memory 300, and transfers data to and from a main memory and a peripheral I / O unit 400 via the bus controller 200. Do.

[0003] The microprocessor 100 includes a cache control circuit 120 and a bus control circuit 130, and controls the cache memory 300 and the bus controller 200.
Address / data shared bus AD and control bus CT
L input / output control. Cache control circuit 120
Performs control to temporarily store data that is frequently read or written by the microprocessor 100 from the main memory 400 in units of lines having a configuration of several words, and to write back data to the main memory in units of lines when it becomes unnecessary. . The bus control circuit 130 outputs an address and data to the bus controller 200 via the address / data shared bus AD and the control bus CTL. These addresses and data are transferred in a time-division manner by the shared address / data bus AD, and whether the shared address / data bus AD is used for address or data is determined by the control bus CTL. Specified by signal.

A bus controller 200 is connected to an address / data sharing bus AD of the microprocessor 100, and has a main memory and a peripheral I / O unit 400.
Are connected via another address bus ADDR and data bus DATA, input / output control between these buses is performed, and data transfer is performed. At this time, the address and data passed in a time division manner from the microprocessor 100 via the address / data shared bus AD are respectively stored in the address buffer 2.
10. Temporarily store in the data buffer 220, and output these addresses and data to the main memory and the peripheral I / O unit 400 via the address bus ADDR and the data bus DATA, respectively. In addition, the address value output from the address buffer 210 to the address bus ADDR may be incremented every bus cycle in accordance with the input / output function of the main memory.

[0005] The cache memory 300 is roughly divided into two areas. FIG. 9 is an explanatory diagram showing an example of the area configuration of the cache memory 300. One is a tag area 310, which stores address information for comparing whether or not a cache hit has occurred. Two are a data area 320, which stores hit data. A pair of tag information and data is defined as one line 330,
The data area 320 in the line 330 has a plurality of words of data. When transferring data between the cache memory 300 and the main memory and the peripheral I / O unit 400,
A plurality of word data in the data area 320 in one line 330 is a transfer unit and is block-transferred.

FIG. 10 is a flowchart showing an operation flow on the microprocessor side in the data transfer section of the conventional data processing apparatus. Briefly, cache
Main memory and peripheral I / O such as at the time of write-back from memory 300 or block transfer by a special instruction
Step 613 when a data output request is issued to the unit 400
, A command is designated by the control bus CTL and an address is output to the address / data shared bus AD. next,
In steps 614 and 615, a data identifier is designated by the control bus CTL, and data output of a plurality of words to the address / data shared bus AD is repeated until the final data designation signal EOD is reached.

FIG. 11 is a flowchart showing an operation flow on the bus controller side in the data transfer section of the conventional data processing device. When a data output request is issued to the main memory and the peripheral I / O unit 400, such as at the time of writing back from the cache memory 300 or at the time of block transfer by a special instruction, the microprocessor via the address / data shared bus AD and the control bus CTL. When an address and a command are input from 100, the address is temporarily stored in the address buffer 210, and in step 621, the address is output to the main memory and the peripheral I / O unit 400 via the address bus ADDR. Next, in steps 623 to 625, the address / data shared bus AD is synchronized in synchronization with the operation on the microprocessor side in FIG. 10 in response to the data identifier designation by the control bus CTL.
From the data buffer 220 to the data bus DATA.
And outputs data to the main memory and the peripheral I / O unit 400 via These data inputs and outputs are
The data identifier designation by the control bus CTL is repeated until the final data designation signal EOD is reached.

FIG. 12 is a timing chart showing a block transfer example of the data transfer unit of the conventional data processing apparatus based on the operation flows of FIGS.

FIG. 13 is an explanatory diagram for explaining an operation function of a data transfer section of the conventional data processing apparatus. Address / data shared bus AD, control bus CTL
The operation function of the data transfer unit is shown corresponding to each bit configuration of FIG. Here, the address / data shared bus AD has 32
The bits are treated as one. Also, control bus CT
In L4-0, bit 4 indicates a bus attribute, and corresponding lower bits 3-0 have different meanings corresponding to this data. When bit 4 is “0”, bit 3
〜0 designates a command, and when bit 4 is “1”, designates a data identifier. For example, FIGS.
Main memory and peripheral I / O unit 400 described in 2
The block transfer function to each of the four bits of the control bus CTL
2 are designated as "0, 1, 1".

[0010]

A problem with the conventional data processing apparatus is that the performance of the system, which handles a large amount of image data such as a map, is greatly reduced.

The reason is that a large-capacity memory is constituted by a low-speed memory on a board different from the board on which the microprocessor is mounted, and the microprocessor normally executes the program and data in the cache at a high speed. This is because continuous access to a large-capacity memory results in a large waiting time and a gap with the processing of the microprocessor.

Accordingly, it is an object of the present invention to improve the system performance of a data processing device in which a large-capacity memory is mounted.

[0013]

SUMMARY OF THE INVENTION Therefore, the present invention provides a microprocessor and a method for temporarily storing data that is frequently read or written by the microprocessor from a main memory in units of a line having a configuration of several words. A cache that writes back to the main memory
A memory and a bus controller connected to the microprocessor via a bus, connecting the main memory and the peripheral I / O unit via another bus, controlling input / output between these buses, and performing data transfer. In the data processing device for performing data processing, when writing data in the cache memory, the data of the first word in the write line is compared with each of the other data, and the word of the same data continuously matches from the first word. Data comparing means for outputting a comparison result corresponding to the number of words, and writing the comparison result together with the data as a match flag at the time of writing the data in the cache memory in line units, and the data of the head word and the match at the time of the write back The flag is read out and a continuous match starts from the first word in accordance with the match flag. Cache control means for skipping each data and controlling reading of the next data, and compressing each data successively coincident from the first word into the data of the first word and the number of transfers thereof in correspondence with the coincidence flag at the time of the write back Bus control means for outputting to the bus controller and releasing the bus for other processing until the next data is read.

Further, the bus controller counts the number of bus cycles for the main memory at the time of the write back, and stores the data of the first word every bus cycle until the counted value reaches the number of transfers. Bus output to main memory.

[0015] The data comparing means may store the data of one half word of the first word in the write line and the other one word.
ワ ー ド word data is compared with each other, and a comparison result is output in units of ワ ー ド word corresponding to the number of words in which the word of the same data continuously matches from the first word. The half-word data and the number of transfers are simultaneously output to the bus controller by a bit division.

Further, the bus control means executes a special instruction for transferring data in blocks to the main memory and the peripheral I / O unit, thereby causing each data successively coincident from the first word of the block transfer to be 1 word or 1/2 word. And the data is transferred to the bus controller after being compressed to the number of transfers.

[0017]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a partial block diagram showing a data transfer unit in Embodiment 1 of the data processing device of the present invention. Referring to FIG. 1, the data transfer unit in the data processing device of the present embodiment includes a microprocessor 1100, a bus, and a bus, similarly to the data transfer unit of the conventional data processing device.
A controller 1200 and a cache memory 1300 are provided.
It performs data transfer with the memory and the peripheral I / O unit 400.
At this time, in addition to the conventional data transfer function, a compressed block transfer function is added and selectively executed. In the compressed block transfer, when data to be transferred to the bus controller 1200 continuously has the same value at the time of write-back and block transfer by a special instruction, each successively matching data from the first word is replaced by one word or 1 /. The bus controller 12 compresses the data into two-word data and the number of transfers.
00, and releases the bus to other processes until the next data is read. The functions other than the compressed block transfer are the same as those of the data transfer unit of the conventional data processing apparatus of FIG.

The microprocessor 1100 includes a data comparison circuit 110, a cache control circuit 120, and a bus control circuit 130. The microprocessor 1100 compares and controls data in the cache memory 1300, and shares an address / data shared bus AD with the bus controller 1200. , And input / output control of the control bus CTL.

When data is written to cache memory 1300, data comparison circuit 110 compares the data of the first word in the write line with each of the other data, and the words of the same data continuously match from the first word. The comparison result is output according to the number of words. FIG. 2 is a circuit diagram showing a configuration example of the data comparison circuit. In the present embodiment, 4 caches in the line from the cache memory 1300
The 32-bit data of a word is input in parallel in units of 1/2 word, and the data of 1/2 word of the first word and each other 1 /
Each of the two words is compared with each other and a half-word match signal is output. With these logical outputs, the words of the same data in half-word units correspond to the number of words that continuously match from the first word. A two-word continuous match signal and a four-word continuous match signal are output as comparison results.

The cache control circuit 120 performs control of writing the data and the comparison result of the data comparison circuit 110 as a match flag in line units when writing data to the cache memory 1300. In addition to performing normal read control, at the time of write back, the data and the match flag of the first word are read, and in accordance with the match flag, each successive data from the first word is skipped, and the next data is read. Perform control. This light
Since the control by the match flag at the time of backing is temporally separated from the time of data writing to the cache memory 1300, it is not affected by the delay of the comparison result of the data comparing circuit 110 and is performed at high speed.

Further, in addition to performing normal data transfer in the same manner as in the prior art, the bus control circuit 130 also converts each successively matching data from the first word into a half word corresponding to the match flag at the time of write-back. The bus controller 1 compresses the data and the number of transfers and compresses them at the same time by bit division.
A 1/2 word unit compressed block transfer to the bus 200 is performed, and the bus is released to another process until the next data is read. In addition, a special instruction for block-transferring data to the main memory and the peripheral I / O unit 400 compresses each successively matching data from the first word of the block transfer into 1 / 2-word or 1-word data and the number of transfers. Then, a 1/2 word or 1 word unit compressed block transfer to be output to the bus controller 1200 via the bus is performed, and the bus is released to another process until the next data is read. At this time, in the 1-word unit compressed block transfer, the data of the first word and the number of transfers are divided by the bus controller 12 by time division.
00 is output to the bus. The commands for the normal data transfer and the 1 / 2-word or 1-word unit compression block transfer are designated by the control bus CTL.

The bus controller 1200 is the same as the conventional data processing apparatus shown in FIG. 8 with respect to the address buffer 210 and the address bus ADDR, and performs normal data transfer together with the data buffer 220 as in the conventional case. In addition, a bus cycle counter 230 is added to perform 1/2 word or 1 word unit compression block transfer at the time of write back and block transfer by a special instruction. The bus cycle counter 230
The number of transfers is input from the microprocessor 1100 via the address / data shared bus AD, and at the time of write back, the number of bus cycles for the main memory is counted.
A signal indicating that the count value has reached the transfer count is output. Also, the first word or its first word is sent from the microprocessor 1100 via the address / data shared bus AD.
/ 2 word data is input, the first word data is temporarily stored in the data buffer 220, and is temporarily stored in the data buffer 220 every bus cycle until the count value of the bus cycle counter 230 reaches the transfer count. The output data is output to a data bus DATA.

The cache memory 1300 is roughly 3
Divided into two areas. FIG. 3 is an explanatory diagram showing an example of the area configuration of the cache memory 1300. One is
The tag area 310 stores address information for comparing whether or not a cache hit has occurred. The two are
The data area 320 stores hit data. These two areas are the same as the respective areas of the conventional cache memory 300 in FIG. In the present embodiment, 3
As a second area, a match flag area 340 for storing a 2-word continuous match signal and a 4-word continuous match signal, which are the comparison results of the data comparison circuit 110, as a match flag is added. As in the case of the conventional data processing apparatus, a pair of tag information, data, and a match flag is stored in one line 33.
The data area 320 in one line 330 has data of a plurality of words. When data is transferred between the cache memory 1300 and the main memory and the peripheral I / O unit 400, the data area 320 in this one line 330 is
Is a unit of transfer and is block-transferred.

Next, the operation of the data transfer unit in the data processing device of the present embodiment will be described. FIG. 4 is a flowchart showing an operation flow on the microprocessor side in the data transfer unit of the data processing device of the present embodiment.

First, when a data output request is issued to the main memory and the peripheral I / O unit 400, for example, at the time of write-back from the cache memory 1300 or at the time of block transfer by a special instruction, at step 613, the control bus Specify the command by CTL,
The address is output to the data sharing bus AD. Next, in step 714, it is determined whether or not block transfer is performed by a special instruction, and the process proceeds to step 715 or step 716. At step 715, at the time of write-back, the matching flag read from the cache memory 1300 is checked, and the process proceeds to step 614 or 717. The processing in steps 614 to 615 is the same as that in the conventional case. Normal data transfer is performed, and the address / data shared bus AD is used in each bus cycle until the data identifier is designated by the control bus CTL to the final data designation signal EOD.
Output data to

In step 716, block transfer by the special instruction compresses each data successively coincident from the first word into 1/2 word or 1 word data and the number of times of transfer by 1/2 word unit compressed block transfer or 1 byte.
Step 717 corresponding to the word unit compressed block transfer
Alternatively, the process proceeds to step 718. In step 717, a 1/2 word unit compressed block transfer is performed, and the data of the first word and the number of transfers are simultaneously output to the address / data shared bus AD by bit division, and a read request for the next data is made. The bus is released to other processing until it. In steps 718 and 719, the first word 1
The word data and the number of transfers are
The data is output to the data sharing bus AD, and the bus is released to another process until the next data read request.

FIG. 5 is a flowchart showing an operation flow on the bus controller side in the data transfer unit of the data processing device of the present embodiment.

First, when a data output request is issued to the main memory and the peripheral I / O unit 400 such as at the time of write-back from the cache memory 1300 or at the time of block transfer by a special instruction, the address / data shared bus AD and the control bus CTL are switched. When an address and a command are input from the microprocessor 1100 via the memory, the address is temporarily stored in the address buffer 210, and in step 621, the address is output to the main memory and the peripheral I / O unit 400 via the address bus ADDR. . next,
In step 722, one of normal data transfer, 1/2 word unit compressed block transfer, and 1 word unit compressed block transfer is determined according to the command designation by the control bus CTL.
Alternatively, the process proceeds to step 724. Step 623-625
Is performed in the same manner as in the prior art. Normal data transfer is performed and the data buffer 220 is transferred from the address / data shared bus AD every bus cycle until the data identifier designation by the control bus CTL becomes the final data designation signal EOD.
And temporarily stores the data, and outputs the data to the data bus DATA.

In step 723, the data of the half word of the first word and the number of transfers thereof are simultaneously inputted by bit division via the address / data shared bus AD, and the first word and the number of transfers are input to the data buffer. 2
20, and temporarily stored in the bus cycle counter 230 and proceed to step 726. In steps 724 and 725, the data of the first word and the number of transfers are input in a time-division manner via the address / data shared bus AD, and the data buffer 220 and the bus cycle counter 23 are input.
The value is temporarily stored as 0, and the flow advances to step 726. Step 72
In steps 6 to 728, the head word data temporarily stored in the data buffer 220 is bus-outputted to the data bus DATA for each bus cycle, and the bus cycle is counted. D
Main memory and peripheral I / O unit 4 via ATA
The data output to 00 is repeated.

FIG. 6 is a timing chart showing a block transfer example of the data transfer unit of the data processing apparatus according to the present embodiment based on the operation flows shown in FIGS. FIG. 6A is a timing chart of a half-word unit compressed block transfer, in which the data of the first half word and the number of transfers are simultaneously output to the address / data shared bus AD by bit division. Have been. FIG. 6B is a timing chart of the one-word unit compressed block transfer, in which the data of one head word and the number of transfers are output to the address / data shared bus AD in a time sharing manner.

FIG. 7 is an explanatory diagram for explaining the operation function of the data transfer unit of the data processing device of the present embodiment. Address / data shared bus AD, control bus CTL
The operation function of the data transfer unit is shown corresponding to each bit configuration of FIG. Compared to the explanatory diagram of the conventional data processing device of FIG. 13, the control bus CTL is expanded by one bit, and the main bus via the bus controller in the conventional data processing device is expanded.
In addition to the normal data transfer function to the memory and the peripheral I / O unit, a function of ワ ー ド word unit compressed block transfer and 1 word unit compressed block transfer based on the operation flow of FIGS. 4 and 5 is added. . For example, each bit 5 to 2 of the control bus CTL is set to “0, 1, 1, 0” or “0, 1, 1,
By setting the value to “1”, a command is specified for a half-word unit compressed block transfer or a one-word unit compressed block transfer.

In this embodiment, a case where one word length is 32 bits of data at the time of block transfer is described. However, as another embodiment, the present invention is applied to data whose one word length is other than 32 bits. Is possible, and 1 /
The present invention is also applicable to equally divided word data other than two words. For example, for data having a word length of 16 bits, corresponding to the number of words where the same data word continuously matches from the first word in units of 1/2 word and 8 bits,
Each data that continuously matches from the first word of the block transfer can be compressed into 1/2 word 8-bit data and the number of transfers.

[0033]

The first effect is that the system performance of a data processing device in which a large-capacity memory is mounted is improved.

The reason is that, when a data output request is issued to the main memory and the peripheral I / O unit, such as at the time of write-back from the cache memory or at the time of block transfer by a special instruction, each of the consecutive words starting from the first word of the block transfer. This is because data can be compressed into half-word or one-word data and the number of transfers thereof, output to the bus controller via the bus, and the bus can be released to other processing until the next data read request.

For example, if 4-word data can be compressed and transferred in 1 / 2-word units by data comparison, the data transfer time from the microprocessor to the bus controller can be reduced to 2/5, and the data transfer time of 3/5 can be shortened. Available for processing.

The second effect is that, in particular, the setting of the same color data for creating image data and the setting of continuous data such as the initial data setting of a large database can be performed efficiently and with less hardware resources.

The reason is that the compressed block transfer function by the special instruction can be realized also as the compressed block transfer function at the time of write back from the cache memory.

[Brief description of the drawings]

FIG. 1 is a partial block diagram illustrating a data transfer unit in an embodiment of a data processing device of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a data comparison circuit in FIG. 1;

FIG. 3 is an explanatory diagram showing an example of an area configuration of a cache memory in FIG. 1;

FIG. 4 is a flowchart showing an operation flow of the data transfer unit of FIG. 1 on the microprocessor side;

FIG. 5 is a flowchart showing an operation flow of the data transfer unit of FIG. 1 on the bus controller side;

FIG. 6 is a timing chart showing an operation example of the data transfer unit in FIG. 1 at the time of compressed block transfer.

FIG. 7 is an explanatory diagram for explaining an operation function of the data transfer unit in FIG. 1;

FIG. 8 is a partial block diagram illustrating a data transfer unit in a conventional data processing device.

FIG. 9 is an explanatory diagram showing an example of an area configuration of the cache memory in FIG. 8;

10 is a flowchart showing an operation flow of the data transfer unit shown in FIG. 8 on the microprocessor side;

11 is a flowchart showing an operation flow of the data transfer unit of FIG. 8 on the bus controller side.

12 is a timing chart showing an example of an operation at the time of block transfer of the data transfer unit of FIG. 8;

FIG. 13 is an explanatory diagram for explaining an operation function of the data transfer unit in FIG. 8;

[Explanation of symbols]

 100, 1100 Microprocessor 200, 1200 Bus controller 300, 1300 Cache memory 400 Main memory and peripheral I / O unit 110 Data comparator 120 Cache control circuit 130 Bus control circuit 210 Address buffer 220 Data buffer 230 Address Counter 310 Tag area 320 Data area 330 1 line 340 Match flag area 610 to 728 Operation steps

Claims (4)

[Claims] 1. A microprocessor and a cache for temporarily storing data frequently read or written by the microprocessor from a main memory in units of several words in a line unit and writing back the data to the main memory when it becomes unnecessary. A memory, a bus connected to the microprocessor and the main memory and peripheral I / O
A bus controller for connecting the units via different buses, performing input / output control between these buses and performing data transfer, and performing data processing. Data comparing means for comparing the data of the first word in the read line with each of the other data, and outputting a comparison result corresponding to the number of words in which the words of the same data continuously match from the first word, and the cache memory At the time of data writing, the comparison result is written together with the data as a match flag in line units.At the time of the write-back, the data of the head word and the match flag are read out, and each data successively matching from the head word corresponding to the match flag is read. A cache control means for skipping and controlling reading of the next data; Wherein compressing each data corresponding to said match flag click upon consecutive matches from the first word to the data and its transfer number of the first word bus
A data processing device comprising: a bus control unit that outputs a signal to a controller and releases the bus to another process until the next data is read. 2. The bus controller counts bus cycles for the main memory at the time of the write back, and keeps counting the number of bus cycles until the count reaches the transfer count.
2. The data processing device according to claim 1, wherein the data of the first word is bus-outputted to the main memory every bus cycle. 3. The data comparison means according to claim 1, wherein the data of the half word of the first word in the write line and each other half of the word are written.
The data of each word is compared with each other, and a comparison result is output in correspondence with the number of words in which the same data word continuously matches from the first word in units of 1/2 word. 3. The data processing device according to claim 1, wherein two words of data and the number of transfers are simultaneously output to the bus controller by bit division. 4. The bus control means according to a special instruction for block-transferring data to the main memory and the peripheral I / O unit, wherein each successively matching data from the head word of the block transfer is one word or one-half word. 4. The data processing device according to claim 1, wherein the data is compressed to the data and the number of transfers and output to the bus controller via a bus.