JPH11238827A - Manufacture of metal core - Google Patents

Manufacture of metal core

Info

Publication number
JPH11238827A
JPH11238827A JP10038917A JP3891798A JPH11238827A JP H11238827 A JPH11238827 A JP H11238827A JP 10038917 A JP10038917 A JP 10038917A JP 3891798 A JP3891798 A JP 3891798A JP H11238827 A JPH11238827 A JP H11238827A
Authority
JP
Japan
Prior art keywords
metal
hole
plate
etching
metal plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10038917A
Other languages
Japanese (ja)
Inventor
Morio Take
杜夫 岳
Nobuyuki Ikeguchi
信之 池口
Kozo Yamane
康三 山根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Gas Chemical Co Inc
Original Assignee
Mitsubishi Gas Chemical Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Gas Chemical Co Inc filed Critical Mitsubishi Gas Chemical Co Inc
Priority to JP10038917A priority Critical patent/JPH11238827A/en
Priority to US09/207,115 priority patent/US6376908B1/en
Priority to EP98310022A priority patent/EP0926729A3/en
Priority to KR1019980054122A priority patent/KR19990062959A/en
Publication of JPH11238827A publication Critical patent/JPH11238827A/en
Priority to US10/036,385 priority patent/US6720651B2/en
Priority to US10/790,039 priority patent/US20040171189A1/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To form simultaneously a protruding part and clearance holes or slits in one time of an etching process by a method wherein in the etching process, an etching liquid is sprayed upon the protruding part formation surface of an internal metal plate at a low pressure and an etching liquid is sprayed upon the opposite side to the protruding part formation surface at a high pressure. SOLUTION: A 200-μm thick copper plate, which is used as an internal metal plate (b), is prepared and after a liquid etching resist (a) is applied on the whole surface of the plate (b) in a thickness of 20 μm and is dried, the surface of the plate (b) is formed in such a way that the etching resist is left on the part of a protruding part and the rear of the plate (b) is irradiated with ultraviolet rays so that an etching resist (a) on learance hole parts (c) is removed to develop the rear with 1% of a sodium carbonate solution. After that, the surface and the rear of the plate (b) are simultaneously etched from both sides of the plate (b) at 1.0 kgf/cm<2> in the surface and 2.5 kgf/cm<2> in the rear, one piece of a 13 mm-square and 100-μm high protrusion is formed in the center of a package with the protruding part of a 50-mm square size on the surface of the plate (b) and at the same time, 0.6 mmϕ of the clearance holes (c) are bored. As a result, the hole diameters of the holes (c) are formed almost equal.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、半導体チップを少なく
とも１個小型プリント配線板に搭載した形の、新規な半
導体プラスチックパッケージに使用する、片面凸形状の
金属芯入り両面金属箔張積層板用金属芯の製造方法に関
する。これを使用した半導体プラスチックパッケージ
は、マイクロプロセッサー、マイクロコントローラー、
ASIC、グラフィック等の比較的高ワットで、多端子高密
度のパッケージとして用いられる。本半導体プラスチッ
クパッケージは、ソルダーボールを用いてマザーボード
プリント配線板に実装して電子機器として使用される。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a double-sided metal foil-clad laminate having a metal core having a convex shape on one side, which is used for a novel semiconductor plastic package in which at least one semiconductor chip is mounted on a small printed wiring board. The present invention relates to a method for manufacturing a metal core. Semiconductor plastic packages using this are microprocessors, microcontrollers,
It is used as a relatively high-wattage, multi-terminal, high-density package for ASICs and graphics. This semiconductor plastic package is mounted on a motherboard printed wiring board using solder balls and used as an electronic device.

【０００２】[0002]

【従来の技術】従来、半導体プラスチックパッケージと
して、プラスチックボールグリッドアレイ（P-BGA ）や
プラスチックランドグリッドアレイ（P-LGA ）等、プラ
スチックプリント配線板の上面に半導体チップを固定
し、このチップを、プリント配線板上面に形成された導
体回路にワイヤボンディングで結合し、プリント配線板
の下面にはソルダーボールを用いて、マザーボードプリ
ント配線板と接続するための導体パッドを形成し、表裏
回路導体がメッキされたスルーホールで接続されて、半
導体チップが樹脂封止されている構造の半導体プラスチ
ックパッケージが公知である。本公知構造において、半
導体から発生する熱をマザーボードプリント配線板に拡
散させるため、半導体チップを固定するための上面の金
属箔から下面に接続するメッキされた熱拡散スルーホー
ルが形成されている。2. Description of the Related Art Conventionally, as a semiconductor plastic package, a semiconductor chip such as a plastic ball grid array (P-BGA) or a plastic land grid array (P-LGA) is fixed on a top surface of a plastic printed wiring board. It is connected to the conductor circuit formed on the upper surface of the printed wiring board by wire bonding, and the lower surface of the printed wiring board is formed with conductor pads for connection with the motherboard printed wiring board using solder balls, and the front and back circuit conductors are plated 2. Description of the Related Art A semiconductor plastic package having a structure in which a semiconductor chip is sealed with a resin by connecting through a formed through hole is known. In the known structure, a plated heat diffusion through hole is formed from the upper metal foil for fixing the semiconductor chip to the lower surface in order to diffuse the heat generated from the semiconductor to the motherboard printed wiring board.

【０００３】該スルーホールを孔を通して、水分が半導
体固定に使われている熱伝導性接着剤に吸湿され、マザ
ーボードへの実装時の加熱により、また、半導体部品を
マザーボードから取り外す際の加熱により、層間フクレ
を生じる危険性があり、これはポップコーン現象と呼ば
れている。このポップコーン現象が発生した場合、パッ
ケージは使用不能となることが多く、この現象を大幅に
改善する必要がある。また、半導体の高機能化、高密度
化は、ますます発熱量の増大を意味し、熱放散用のため
の半導体チップ直下のスルーホールのみでは熱の放散は
不十分となってきている。Through the through holes, moisture is absorbed by the heat conductive adhesive used for fixing the semiconductor, and is heated by mounting at the time of mounting on the motherboard and by heating at the time of removing the semiconductor parts from the motherboard. There is a risk of interlayer blistering, which is called the popcorn phenomenon. When this popcorn phenomenon occurs, the package often becomes unusable, and it is necessary to greatly improve this phenomenon. In addition, higher functionality and higher density of semiconductors mean more and more heat generation, and heat dissipation is insufficient with only through holes directly below the semiconductor chip for heat dissipation.

【０００４】[0004]

【発明が解決しようとする課題】本発明は、以上の問題
点を改善した半導体プラスチックパッケージを提供する
ものである。SUMMARY OF THE INVENTION The present invention is to provide a semiconductor plastic package which solves the above problems.

【０００５】[0005]

【発明が解決するための手段】少なくとも１個の半導体
チップを熱伝導性接着剤で直接固定するための金属凸部
分と、表裏導通孔形成のためのクリアランスホール、又
はスリット孔が形成されている金属板の表裏に、必要に
より該金属板の凸部分を避けて、半硬化状態の熱硬化性
樹脂組成物プリプレグ或いは熱硬化性樹脂フィルムを配
置し、さらに、その外側に金属箔を配置し、加熱、加圧
下に作成する半導体プラスチックパッケージ用の金属芯
入り両面金属箔張積層板の金属芯の製造方法であって、
金属平板の片面の一部分に凸部形成用エッチングレジス
トを残存配置させ、反対面にはクリアランスホール或い
はスリット孔をエッチングで形成するためのエッチング
レジストを残存配置させ、エッチング工程で凸部形成面
には、より低圧力のエッチング液を吹きかけ、反対面に
は、より高圧力でエッチング液を吹きかけることによ
り、凸部分とクリアランスホール或いはスリット孔を一
度のエッチング工程で同時に形成することが出来た。凸
部の形状は 5〜20mm角或いは円錐、円錐台形であり、突
起が少なくとも１個以上とする。A metal convex portion for directly fixing at least one semiconductor chip with a heat conductive adhesive, and a clearance hole or a slit hole for forming a front / back conduction hole are formed. On the front and back of the metal plate, if necessary, avoiding the convex portion of the metal plate, arrange a thermosetting resin composition prepreg or thermosetting resin film in a semi-cured state, and further arrange a metal foil on the outside thereof, Heating, a method for producing a metal core of a double-sided metal foil clad laminate containing a metal core for a semiconductor plastic package to be created under pressure,
An etching resist for forming a convex portion is left on a part of one surface of the metal flat plate, and an etching resist for forming a clearance hole or a slit hole is left on the opposite surface. By spraying the etching solution at a lower pressure and spraying the etching solution at a higher pressure on the opposite surface, the convex portion and the clearance hole or the slit hole can be formed simultaneously in a single etching step. The shape of the projection is 5 to 20 mm square, conical, or truncated cone, and has at least one projection.

【０００６】この金属芯を用いて、その表面には必要に
より凸部をくりぬいたノーフローまたはローフローのプ
リプレグ、樹脂シート、樹脂付き金属箔、或いは塗料塗
布による樹脂層、裏面には未加工のローフロープリプレ
グまたはハイフローのプリプレグ、樹脂シート、樹脂付
き金属箔、或いは塗料塗布による樹脂層等を配置し、必
要により、その外側に金属箔を置いて、加熱、加圧下に
積層成形して両面金属箔張積層板を製造する。[0006] Using this metal core, a no-flow or low-flow prepreg, a resin sheet, a metal foil with resin, or a resin layer formed by coating with a paint, and an unprocessed low-flow A prepreg or high-flow prepreg, a resin sheet, a metal foil with resin, or a resin layer by coating with a paint, etc., are placed on the outside, if necessary. Manufacture laminates.

【０００７】これを用いて、作成されたプリント配線板
は、金属芯凸部に熱伝導性接着剤で固定された半導体チ
ップと、その周囲の回路導体とがワイヤボンディングで
接続されており、少なくとも、該表面のプリント配線板
上の信号伝播回路導体が、プリント配線板の反対面に形
成された回路導体もしくは該ハンダボールでの接続用導
体パッドとスルーホール導体で結線されており、少なく
とも、半導体チップ、ボンディングワイヤ、ボンディン
グパッドが樹脂封止されている構造の半導体プラスチッ
クパッケージであって、且つ、プリント配線板とほぼ同
じ大きさの金属板がプリント配線板の厚さ方向のほぼ中
央に配置され、表裏回路導体と熱硬化性樹脂組成物で絶
縁されており、金属板に少なくとも１個以上のスルーホ
ール径より大きい径のクリアランスホール或いはスリッ
ト孔があけられ、孔壁と金属板とは樹脂組成物で絶縁さ
れており、半導体チップとほぼ同じ大きさの内層の金属
の一部が１個以上突起で表面に露出されており、該露出
金属板の表面に半導体チップが固定され、且つ、少なく
とも１個以上のスルーホールが直接内層の金属と接続し
ており、発生した熱はこの放熱用スルーホールを通して
マザーボードに逃げるようにした半導体プラスチックパ
ッケージとすることにより、半導体チップの下面からの
吸湿がなく、吸湿後の耐熱性、すなわちポップコーン現
象が大幅に改善できるとともに、熱放散性を大幅に改善
できた。加えて大量生産性にも適しており、経済性の改
善された、新規な構造の半導体プラスチックパッケージ
を得ることができ、本発明を完成するに至った。[0007] The printed wiring board prepared by using the above-mentioned method has a semiconductor chip fixed to a metal core convex portion with a heat conductive adhesive and a circuit conductor around the semiconductor chip connected by wire bonding. A signal propagation circuit conductor on the printed wiring board on the front surface is connected to a circuit conductor formed on the opposite surface of the printed wiring board or a conductor pad for connection with the solder ball by a through-hole conductor, and at least a semiconductor A semiconductor plastic package having a structure in which a chip, a bonding wire, and a bonding pad are sealed with a resin, and a metal plate having substantially the same size as the printed wiring board is disposed substantially at the center in the thickness direction of the printed wiring board. , Which is insulated from the front and back circuit conductors by the thermosetting resin composition, and is larger than at least one through hole diameter in the metal plate. The hole wall and the metal plate are insulated with a resin composition, and a part of the metal of the inner layer having substantially the same size as the semiconductor chip is exposed on the surface by one or more protrusions. The semiconductor chip is fixed to the surface of the exposed metal plate, and at least one or more through holes are directly connected to the metal of the inner layer, so that generated heat escapes to the motherboard through the heat radiating through holes. By adopting the semiconductor plastic package described above, there is no moisture absorption from the lower surface of the semiconductor chip, and the heat resistance after moisture absorption, that is, the popcorn phenomenon can be significantly improved, and the heat dissipation can be greatly improved. In addition, a semiconductor plastic package having a novel structure that is suitable for mass productivity and has improved economic efficiency can be obtained, and the present invention has been completed.

【０００８】[0008]

【発明の実施の形態】本発明の金属芯を用いた半導体プ
ラスチックパッケージは、プリント配線板の厚み方向の
ほぼ中央に熱放散性の良好な金属板を配置し、表裏の回
路導体導通用のメッキされたスルーホールは、金属板に
あけられた該クリアランスホール或いはスリット孔径よ
り小さめの径の孔とし、埋め込まれた樹脂のほぼ中央に
形成することにより、金属板との絶縁性を保持する。DESCRIPTION OF THE PREFERRED EMBODIMENTS In a semiconductor plastic package using a metal core according to the present invention, a metal plate having good heat dissipation is arranged at substantially the center in the thickness direction of a printed wiring board, and plating for conducting circuit conductors on the front and back surfaces is performed. The formed through hole is a hole having a diameter smaller than the diameter of the clearance hole or the slit hole formed in the metal plate, and is formed substantially at the center of the embedded resin, thereby maintaining the insulation with the metal plate.

【０００９】公知のスルーホールを有する金属芯プリン
ト配線板の上面に半導体チップを固定する方法において
は、従来のP-BGA パッケージと同様に半導体チップから
の熱は直下の熱放散用スルーホールに落として熱放散せ
ざるを得ず、ポップコーン現象は改善できない。本発明
は、まず金属芯とする両面平滑な金属板を用意し、表面
の凸部を形成する部分のエッチングレジストを残し、裏
面はクリアランスホール或いはスリット孔以外の部分の
エッチングレジストを残るように加工し、表面はより低
圧力で、裏面はより高圧力で、エッチングにより表面の
凸部を形成すると同時に、裏面からクリアランスホール
或いはスリット孔をあける。表面の凸部は、少なくとも
１個以上の半導体チップ固定用に、半導体チップとほぼ
同等の大きさの凸部、又は円錐、円錐台形の複数個の凸
部を形成しておく。金属板の表裏のエッチング圧力は、
目的とする凸部の高さ、金属板の厚さによっても変わる
が、一般には表面は、 0.5〜1.5kgf/cm 、裏面は 1.0〜
2.5kgf/cm の圧力の範囲で適宜選択する。In a known method of fixing a semiconductor chip on the upper surface of a metal-core printed wiring board having a through hole, heat from the semiconductor chip is dropped to a heat-dissipating through hole immediately below, similarly to a conventional P-BGA package. Heat must be dissipated and the popcorn phenomenon cannot be improved. According to the present invention, first, a metal plate having both surfaces smooth as a metal core is prepared, and an etching resist in a portion forming a convex portion on the front surface is left, and an etching resist in a portion other than the clearance hole or the slit hole is left on the rear surface. At a lower pressure on the front surface and at a higher pressure on the rear surface, a convex portion of the front surface is formed by etching, and at the same time, a clearance hole or a slit hole is formed from the rear surface. As the convex portion on the surface, a convex portion having substantially the same size as the semiconductor chip, or a plurality of convex portions having a conical or truncated cone shape is formed for fixing at least one or more semiconductor chips. The etching pressure on the front and back of the metal plate is
It depends on the height of the target projection and the thickness of the metal plate, but generally the surface is 0.5-1.5kgf / cm and the back is 1.0-1.5kgf / cm.
Select appropriately within the pressure range of 2.5 kgf / cm2.

【００１０】該金属凸部とクリアランスホール或いはス
リット孔が形成された金属板の表面を公知の方法で酸化
処理、微細凹凸形成、皮膜形成等の接着性や電気絶縁性
向上のための表面処理を必要に応じて施す。該表面処理
され、凸部とクリアランスホール或いはスリット孔が形
成された金属板の、半導体チップを直接固定する面以外
は、すべて熱硬化性樹脂組成物で絶縁部を形成する。熱
硬化性樹脂組成物による絶縁部の形成は、半硬化状態の
熱硬化性樹脂組成物を含浸、乾燥したプリプレグ等を用
い、半導体チップを直接固定する凸起のある金属部分に
相当するプリプレグの部分を、必要によりあらかじめ凸
部分の面積よりやや大きめの孔を打ち抜き等によってあ
けておき、これを表面に配置し、裏面には孔のあいてい
ないプリプレグを配置し、必要により表裏に金属箔を置
き、加熱、加圧下に積層成形する。プリプレグの厚みは
金属突起の高さよりやや高めになるように作成する。加
熱、加圧工程中に、熱により１度熔融した半硬化状態の
熱硬化性樹脂を金属板のクリアランスホール或いはスリ
ット孔に流し込んでクリアランスホール或いはスリット
孔の中を埋め込むと同時に、全体を一体化する。The surface of the metal plate on which the metal protrusions and the clearance holes or slit holes are formed is subjected to a surface treatment for improving adhesiveness and electric insulation such as oxidation treatment, formation of fine irregularities, and film formation by a known method. Apply as needed. The insulating portion is formed of a thermosetting resin composition except for the surface of the metal plate on which the surface treatment is performed and the convex portion and the clearance hole or the slit hole are formed, except for the surface on which the semiconductor chip is directly fixed. The formation of the insulating part by the thermosetting resin composition is performed by impregnating the thermosetting resin composition in a semi-cured state, using a dried prepreg, or the like, and forming a prepreg corresponding to a metal part having a protrusion directly fixing the semiconductor chip. If necessary, punch a hole slightly larger than the area of the convex part if necessary by punching out, place it on the front side, place a prepreg without holes on the back side, and place metal foil on the front and back as necessary. Place, laminate under heat and pressure. The thickness of the prepreg is made slightly higher than the height of the metal projection. During the heating and pressurizing steps, the semi-cured thermosetting resin melted once by heat is poured into the clearance holes or slit holes of the metal plate to fill the clearance holes or slit holes and at the same time integrate the whole. I do.

【００１１】また、無溶剤或いは溶剤タイプの熱硬化性
樹脂組成物を用い、スクリーン印刷等で該金属板凸場所
以外に塗布し、更には裏面も同様に塗布してから加熱し
て半硬化状態とした後、金属箔を上下に配置し、加熱、
加圧下に積層成形して一体化する。積層成形する場合、
上記と同様にクリアランスホール或いはスリット孔内に
樹脂を流し込むと同時に熱硬化させる。塗布、半硬化す
る場合、低圧にてクリアランスホール或いはスリット孔
の中に樹脂を流し込み、溶剤或いは空気を加熱しながら
抜き、半硬化する。溶剤が入っている場合、クリアラン
スホール内の未充填が起こり易いため、あらかじめ無溶
剤液状の熱硬化性樹脂組成物をクリアランスホール或い
はスリット孔に流し込み、硬化しておく方法が一般的で
あるが、いずれの方法においても、金属板のクリアラン
スホール或いはスリット孔内を熱硬化性樹脂組成物で充
填されるように加工する。A non-solvent or solvent-type thermosetting resin composition is applied by screen printing or the like to a portion other than the convex portion of the metal plate. After that, place the metal foil up and down, heating,
Laminate and integrate under pressure. When laminating,
In the same manner as described above, the resin is poured into the clearance holes or the slit holes and, at the same time, thermally cured. In the case of coating and semi-curing, a resin is poured into a clearance hole or a slit hole at a low pressure, a solvent or air is removed while heating, and semi-cured. When the solvent is contained, since the unfilling in the clearance hole is apt to occur, a method of pouring the solvent-free liquid thermosetting resin composition into the clearance hole or the slit hole in advance and curing is generally used. In either method, the metal plate is processed so that the clearance hole or the slit hole is filled with the thermosetting resin composition.

【００１２】金属板の側面については、熱硬化性樹脂組
成物で埋め込まれている形、露出している形、いずれの
形でも良い。[0012] The side surface of the metal plate may be any of a shape embedded with a thermosetting resin composition and an exposed shape.

【００１３】また、サブトラクティブ法によるスルーホ
ールプリント配線板の形成のためには、積層成形時に、
表裏の最外層に、プリント配線板よりやや大きめの金属
箔、片面銅張積層板、或いは片面に回路を形成し、必要
により表面処理を施したプリント配線板の回路形成面を
内側になるように配置し、加熱、加圧下に積層成形する
ことにより、外層回路形成用の金属箔で表裏が覆われた
金属箔張多層板が形成される。Further, in order to form a through-hole printed wiring board by a subtractive method, it is necessary to
On the outermost layer on the front and back, form a metal foil slightly larger than the printed wiring board, a single-sided copper-clad laminate, or form a circuit on one side so that the surface of the printed wiring board that has been subjected to surface treatment is placed inside as necessary. By arranging and laminating under heat and pressure, a metal foil-clad multilayer board whose front and back are covered with metal foil for forming an outer layer circuit is formed.

【００１４】表裏層に金属箔を使用しないで積層成形す
る場合、公知のアディティブ法にて回路を形成し、プリ
ント配線板を作る。In the case of laminating and molding without using a metal foil for the front and back layers, a circuit is formed by a known additive method to produce a printed wiring board.

【００１５】上記サブトラクティブ法、セミアディティ
ブ法で作成した板の、半導体を固定する部分以外の箇所
に表裏の回路を導通するスルーホール用孔をドリル、レ
ーザー或いはプラズマ等、公知の方法にて小径の孔をあ
ける。[0015] In a plate prepared by the above subtractive method or semi-additive method, a hole for a through hole for conducting the circuit on the front and back is formed in a portion other than the portion where the semiconductor is fixed by a known method such as drilling, laser or plasma. Drill holes.

【００１６】表裏信号回路用のスルーホール用孔は、樹
脂の埋め込まれた金属板クリアランスホール或いはスリ
ット孔のほぼ中央に、金属板と接触しないように形成す
る。次いで無電解メッキや電解メッキによりスルーホー
ル内部の金属層を形成して、メッキされたスルーホール
を形成するとともに、フルアディティブ法では、同時に
表裏にワイヤボンディング用端子、信号回路、ソルダー
ボール用パッド、導体回路等を形成する。The through-holes for the front and back signal circuits are formed substantially in the center of the metal plate clearance hole or slit hole in which the resin is embedded so as not to contact the metal plate. Next, a metal layer inside the through hole is formed by electroless plating or electrolytic plating, and a plated through hole is formed.At the same time, in the full additive method, wire bonding terminals, signal circuits, solder ball pads, Form conductor circuits and the like.

【００１７】セミアディティブ法では、スルーホールを
メッキすると同時に、表裏も全面メッキされ、その後、
公知の方法にて上下に回路を形成する。また、半導体チ
ップと同じ大きさの凸部を有する金属芯を用いた場合、
表裏金属箔を使用して積層成形されたものは、表裏の回
路形成工程で、半導体チップ固定部分の金属凸部分の表
面にある金属箔も除去される。更に、その表面の凸部と
なった金属露出部分以外に樹脂層を形成し、ビアをレー
ザー、プラズマ等で作成してから、必要によりデスミア
処理を施し、金属メッキを行い、回路形成後、貴金属メ
ッキを、少なくともワイヤボンディングパッド表面に形
成してプリント配線板を完成させることも可能である。
この場合、貴金属メッキの必要のない箇所は、事前にメ
ッキレジストで被覆しておく。または、メッキ後に、必
要により公知の熱硬化性樹脂組成物、或いは光選択熱硬
化性樹脂組成物で、少なくともボンディングパッド、反
対面のハンダボール接着用パッド以外の表面に皮膜を形
成する。片面銅張積層板を使用した場合、回路形成後、
或いは貴金属メッキ後にルータ等で半導体チップ搭載箇
所金属板の基材を切除する。In the semi-additive method, the through hole is plated, and simultaneously the front and back surfaces are plated.
Circuits are formed above and below by a known method. Also, when using a metal core having a protrusion of the same size as the semiconductor chip,
In the case of lamination molding using the front and back metal foils, the metal foil on the surface of the metal convex portion of the semiconductor chip fixing portion is also removed in the front and back circuit forming steps. In addition, a resin layer is formed on the surface except for the exposed metal part which has become a convex part, and a via is formed by laser, plasma, etc., then desmearing is performed if necessary, metal plating is performed, and after forming the circuit, the noble metal is formed. Plating can be formed on at least the surface of the wire bonding pad to complete the printed wiring board.
In this case, a portion that does not require noble metal plating is covered with a plating resist in advance. Alternatively, after plating, a film is formed on at least the surface other than the bonding pad and the opposite surface of the solder ball bonding pad using a known thermosetting resin composition or a photo-selective thermosetting resin composition as necessary. When using a single-sided copper-clad laminate, after forming the circuit,
Alternatively, the base material of the metal plate where the semiconductor chip is mounted is cut off by a router or the like after the noble metal plating.

【００１８】ブラインドビア部を形成する層に使用する
材料としては、上記の基材補強プリプレグ、銅箔に熱硬
化性樹脂組成物を塗布、乾燥して半硬化した樹脂付き銅
箔、或いは塗料等、一般に公知のものが使用される。ブ
ラインドビアを形成する方法は、一般に公知の方法が使
用できる。具体的には、炭酸ガスレーザー、プラズマで
ビアをあける方法、フォトビア法であける方法等が挙げ
られる。Examples of the material used for the layer forming the blind via portion include the above-mentioned base material reinforcing prepreg, a copper foil with a resin which is obtained by applying a thermosetting resin composition to a copper foil, drying and semi-curing, or a paint. A generally known one is used. A generally known method can be used for forming a blind via. Specifically, a method of opening a via with a carbon dioxide laser, plasma, a method of opening with a photo via method, and the like can be given.

【００１９】該プリント配線板の半導体を接着する金属
突起部分の表面に接着剤や金属粉混合接着剤を用いて、
半導体チップを固定し、さらに半導体チップとプリント
配線板回路のボンディングパッドとをワイヤボンディン
グ法で接続し、少なくとも、半導体チップ、ボンディン
グワイヤ、及びボンディングパッドを公知の封止樹脂で
封止する。Using an adhesive or a metal powder-mixed adhesive on the surface of the metal projection portion of the printed wiring board for bonding the semiconductor,
The semiconductor chip is fixed, and the semiconductor chip and the bonding pads of the printed wiring board circuit are connected by a wire bonding method, and at least the semiconductor chip, the bonding wires, and the bonding pads are sealed with a known sealing resin.

【００２０】半導体チップと反対面のソルダーボール接
続用導体パッドに、ソルダーボールを接続してP-BGA を
作り、マザーボードプリント配線板上の回路にソルダー
ボールを重ね、熱によってボールを熔融接続するか、ま
たはパッケージにソルダーボールをつけずにP-LGA を作
り、マザーボードプリント配線板に実装する時に、マザ
ーボードプリント配線板面に形成されたソルダーボール
接続用導体パッドとP-LGA 用のソルダーボール用導体パ
ッドとを、ソルダーボールを加熱熔融することにより接
続する。A solder ball is connected to the solder ball connecting conductor pad on the opposite side of the semiconductor chip to form a P-BGA, and the solder ball is overlaid on a circuit on a motherboard printed wiring board, and the ball is melt-connected by heat. When the P-LGA is made without attaching solder balls to the package, and mounted on the motherboard printed wiring board, the solder ball connection conductor pads formed on the motherboard printed wiring board surface and the solder ball conductors for the P-LGA The pads are connected by heating and melting the solder balls.

【００２１】本発明に用いる金属板は、特に限定しない
が、高弾性率、高熱伝導性で、厚さ30〜500 μm のもの
が好適である。具体的には、純銅、無酸素銅、その他、
銅が95重量％以上のFe、Sn、P 、Cr、Zr、Zn等との合
金、或いは合金の表面を銅メッキした金属板等が好適に
使用される。Although the metal plate used in the present invention is not particularly limited, a metal plate having a high elastic modulus, a high thermal conductivity and a thickness of 30 to 500 μm is suitable. Specifically, pure copper, oxygen-free copper, and others,
An alloy of 95% or more by weight of copper with Fe, Sn, P, Cr, Zr, Zn, or the like, or a metal plate having a copper-plated alloy surface is preferably used.

【００２２】本発明の金属凸部の高さは、30〜200 μm
が好適である。また、凸部をくり抜いたプリプレグ、或
いはスクリーン印刷で形成する熱硬化性樹脂の高さは、
この凸起と同じ高さか、やや高いことが好ましい。凸部
の面積は、半導体チップの面積と同等以上であり、僅か
に大きめが好ましい。一般的には５〜20mm角である。The height of the metal projection of the present invention is 30 to 200 μm.
Is preferred. Also, the height of the thermosetting resin formed by prepreg or screen printing,
It is preferable that the height is equal to or slightly higher than the height of the protrusion. The area of the protrusion is equal to or greater than the area of the semiconductor chip, and is preferably slightly larger. Generally, it is 5 to 20 mm square.

【００２３】本発明で使用される熱硬化性樹脂組成物の
樹脂としては、一般に公知の熱硬化性樹脂が使用され
る。具体的には、エポキシ樹脂、多官能性シアン酸エス
テル樹脂、多官能性マレイミド−シアン酸エステル樹
脂、多官能性マレイミド樹脂、不飽和基含有ポリフェニ
レンエーテル樹脂等が挙げられ、１種或いは２種類以上
が組み合わせて使用される。耐熱性、耐湿性、耐マイグ
レーション性、吸湿後の電気的特性等の点から多官能性
シアン酸エステル樹脂組成物が好適である。As the resin of the thermosetting resin composition used in the present invention, generally known thermosetting resins are used. Specific examples include an epoxy resin, a polyfunctional cyanate ester resin, a polyfunctional maleimide-cyanate ester resin, a polyfunctional maleimide resin, and an unsaturated group-containing polyphenylene ether resin. Are used in combination. Polyfunctional cyanate ester resin compositions are preferred from the viewpoints of heat resistance, moisture resistance, migration resistance, electrical properties after moisture absorption, and the like.

【００２４】本発明の好適な熱硬化性樹脂分である多官
能性シアン酸エステル化合物とは、分子内に２個以上の
シアナト基を有する化合物である。具体的に例示する
と、1,3-又は1,4-ジシアナトベンゼン、1,3,5-トリシア
ナトベンゼン、1,3-、1,4-、1,6-、1,8-、2,6-又は2,7-
ジシアナトナフタレン、1,3,6-トリシアナトナフタレ
ン、4,4-ジシアナトビフェニル、ビス（4-ジシアナトフ
ェニル）メタン、2,2-ビス（4-シアナトフェニル）プロ
パン、2,2-ビス（3,5-ジブロモ-4- シアナトフェニル）
プロパン、ビス（4-シアナトフェニル）エーテル、ビス
（4-シアナトフェニル）チオエーテル、ビス（4-シアナ
トフェニル）スルホン、トリス（4-シアナトフェニル）
ホスファイト、トリス（4-シアナトフェニル）ホスフェ
ート、およびノボラックとハロゲン化シアンとの反応に
より得られるシアネート類などである。The polyfunctional cyanate compound which is a preferred thermosetting resin component of the present invention is a compound having two or more cyanato groups in a molecule. Specific examples include 1,3- or 1,4-dicyanatobenzene, 1,3,5-tricyanatobenzene, 1,3-, 1,4-, 1,6-, 1,8-, 2 , 6- or 2,7-
Dicyanatonaphthalene, 1,3,6-tricyanatonaphthalene, 4,4-dicyanatobiphenyl, bis (4-dicyanatophenyl) methane, 2,2-bis (4-cyanatophenyl) propane, 2,2- Bis (3,5-dibromo-4-cyanatophenyl)
Propane, bis (4-cyanatophenyl) ether, bis (4-cyanatophenyl) thioether, bis (4-cyanatophenyl) sulfone, tris (4-cyanatophenyl)
Phosphite, tris (4-cyanatophenyl) phosphate, and cyanates obtained by reacting novolak with cyanogen halide.

【００２５】これらのほかに特公昭41-1928 、同43-184
68、同44-4791 、同45-11712、同46-41112、同47-26853
及び特開昭51-63149等に記載の多官能性シアン酸エステ
ル化合物類も用いら得る。また、これら多官能性シアン
酸エステル化合物のシアナト基の三量化によって形成さ
れるトリアジン環を有する分子量 400〜6,000 のプレポ
リマーが使用される。このプレポリマーは、上記の多官
能性シアン酸エステルモノマーを、例えば鉱酸、ルイス
酸等の酸類；ナトリウムアルコラート等、第三級アミン
類等の塩基；炭酸ナトリウム等の塩類等を触媒として重
合させることにより得られる。このプレポリマー中には
一部未反応のモノマーも含まれており、モノマーとプレ
ポリマーとの混合物の形態をしており、このような原料
は本発明の用途に好適に使用される。一般には可溶な有
機溶剤に溶解させて使用する。In addition to these, Japanese Patent Publication Nos. 41-1928 and 43-184
68, 44-4791, 45-11712, 46-41112, 47-26853
And polyfunctional cyanate compounds described in JP-A-51-63149 and the like can also be used. A prepolymer having a molecular weight of 400 to 6,000 and having a triazine ring formed by trimerizing a cyanato group of these polyfunctional cyanate compounds is used. This prepolymer is obtained by polymerizing the above-mentioned polyfunctional cyanate ester monomer using, for example, an acid such as a mineral acid or a Lewis acid; a base such as a sodium alcoholate or a tertiary amine; a salt such as sodium carbonate as a catalyst. It can be obtained by: The prepolymer also contains some unreacted monomers and is in the form of a mixture of the monomer and the prepolymer, and such a raw material is suitably used for the purpose of the present invention. Generally, it is used after being dissolved in a soluble organic solvent.

【００２６】エポキシ樹脂としては、一般に公知のもの
が使用できる。具体的には、液状或いは固形のビスフェ
ノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ
樹脂、フェノールノボラック型エポキシ樹脂、クレゾー
ルノボラック型エポキシ樹脂、脂環式エポキシ樹脂；ブ
タジエン、ペンタジエン、ビニルシクロヘキセン、ジシ
クロペンチルエーテル等の結合をエポキシ化したポリエ
ポキシ化合物類；ポリオール、水酸基含有シリコン樹脂
類とエポハロヒドリンとの反応によって得られるポリグ
リシジル化合物類等が挙げられる。これらは１種或いは
２種類以上が組み合わせて使用され得る。As the epoxy resin, a generally known epoxy resin can be used. Specifically, liquid or solid bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolak type epoxy resin, cresol novolak type epoxy resin, alicyclic epoxy resin; butadiene, pentadiene, vinylcyclohexene, dicyclopentyl ether, etc. And polyglycidyl compounds obtained by reacting a polyol, a hydroxyl group-containing silicone resin with an epohalohydrin, and the like. These may be used alone or in combination of two or more.

【００２７】ポリイミド樹脂としては、一般に公知のも
のが使用され得る。具体的には、多官能性マレイミド類
とポリアミン類との反応物、特公昭57-005406 に記載の
末端三重結合のポリイミド類が挙げられる。As the polyimide resin, generally known ones can be used. Specific examples include a reaction product of a polyfunctional maleimide and a polyamine, and a polyimide having a terminal triple bond described in JP-B-57-005406.

【００２８】これらの熱硬化性樹脂は、単独でも使用さ
れるが、特性のバランスを考え、適宜組み合わせて使用
するのが良い。These thermosetting resins may be used alone, but it is preferable to use them in an appropriate combination in consideration of the balance of properties.

【００２９】本発明の熱硬化性樹脂組成物には、組成物
本来の特性が損なわれない範囲で、所望に応じて種々の
添加物を配合することができる。これらの添加物として
は、不飽和ポリエステル等の重合性二重結合含有モノマ
ー類及びそのプレポリマー類；ポリブタジエン、エポキ
シ化ブタジエン、マレイン化ブタジエン、ブタジエン−
アクリロニトリル共重合体、ポリクロロプレン、ブタジ
エン−スチレン共重合体、ポリイソプレン、ブチルゴ
ム、フッ素ゴム、天然ゴム等の低分子量液状〜高分子量
のelastic なゴム類；ポリエチレン、ポリプロピレン、
ポリブテン、ポリ-4- メチルペンテン、ポリスチレン、
AS樹脂、ABS 樹脂、MBS 樹脂、スチレン−イソプレンゴ
ム、ポリエチレン−プロピレン共重合体、4-フッ化エチ
レン-6- フッ化エチレン共重合体類；ポリカーボネー
ト、ポリフェニレンエーテル、ポリスルホン、ポリエス
テル、ポリフェニレンサルファイド等の高分子量プレポ
リマー若しくはオリゴマー；ポリウレタン等が例示さ
れ、適宜使用される。また、その他、公知の無機或いは
有機の充填剤、染料、顔料、増粘剤、滑剤、消泡剤、分
散剤、レベリング剤、光増感剤、難燃剤、光沢剤、重合
禁止剤、チキソ性付与剤等の各種添加剤が、所望に応じ
て適宜組み合わせて用いられる。必要により、反応基を
有する化合物は硬化剤、触媒が適宜配合される。Various additives can be added to the thermosetting resin composition of the present invention, if desired, as long as the inherent properties of the composition are not impaired. These additives include polymerizable double bond-containing monomers such as unsaturated polyesters and prepolymers thereof; polybutadiene, epoxidized butadiene, maleated butadiene, butadiene-
Low molecular weight liquid to high molecular weight elastic rubbers such as acrylonitrile copolymer, polychloroprene, butadiene-styrene copolymer, polyisoprene, butyl rubber, fluoro rubber, natural rubber; polyethylene, polypropylene,
Polybutene, poly-4-methylpentene, polystyrene,
AS resin, ABS resin, MBS resin, styrene-isoprene rubber, polyethylene-propylene copolymer, 4-fluoroethylene-6-fluoroethylene copolymers; polycarbonate, polyphenylene ether, polysulfone, polyester, polyphenylene sulfide, etc. High molecular weight prepolymers or oligomers; polyurethanes and the like are exemplified, and are appropriately used. Other known inorganic or organic fillers, dyes, pigments, thickeners, lubricants, defoamers, dispersants, leveling agents, photosensitizers, flame retardants, brighteners, polymerization inhibitors, thixotropic Various additives such as imparting agents are used in combination as needed. If necessary, the compound having a reactive group is appropriately blended with a curing agent and a catalyst.

【００３０】本発明の熱硬化性樹脂組成物は、それ自体
は加熱により硬化するが硬化速度が遅く、作業性、経済
性等に劣るため使用した熱硬化性樹脂に対して公知の熱
硬化触媒を用い得る。使用量は、熱硬化性樹脂 100重量
部に対して 0.005〜10重量部、好ましくは0.01〜５重量
部である。The thermosetting resin composition of the present invention can be cured by heating itself, but has a low curing rate and is inferior in workability and economy, so that a known thermosetting catalyst is used for the thermosetting resin used. Can be used. The amount used is 0.005 to 10 parts by weight, preferably 0.01 to 5 parts by weight, per 100 parts by weight of the thermosetting resin.

【００３１】プリプレグの補強基材として使用するもの
は、一般に公知の無機或いは有機の織布、不織布が使用
される。具体的には、Ｅガラス、Ｓガラス、Ｄガラス等
の公知のガラス繊維布、全芳香族ポリアミド繊維布、液
晶ポリエステル繊維布等が挙げられる。これらは、混抄
でも良い。また、ポリイミドフィルム等のフィルムの表
裏に熱硬化性樹脂組成物を塗布、加熱して半硬化状態に
したものも使用できる。As the reinforcing base material of the prepreg, generally known inorganic or organic woven or nonwoven fabrics are used. Specific examples include known glass fiber cloths such as E glass, S glass, and D glass, wholly aromatic polyamide fiber cloths, and liquid crystal polyester fiber cloths. These may be mixed. Alternatively, a thermosetting resin composition applied to the front and back of a film such as a polyimide film and heated to a semi-cured state can be used.

【００３２】最外層の金属箔は、一般に公知のものが使
用できる。好適には厚さ３〜100 μｍの銅箔、ニッケル
箔等が使用される。A generally known metal foil can be used as the outermost layer. Preferably, a copper foil, a nickel foil or the like having a thickness of 3 to 100 μm is used.

【００３３】金属板に形成するクリアランスホール或い
はスリット孔の径は、表裏導通用スルーホール径よりや
や大きめに形成する。具体的には、該スルーホール壁と
金属板クリアランスホール或いはスリット孔壁とは50μ
ｍ以上の距離が、熱硬化性樹脂組成物で絶縁されている
ことが好ましい。表裏導通用スルーホール径について
は、特に限定はないが、50〜300 μｍが好適である。The diameter of the clearance hole or the slit hole formed in the metal plate is formed slightly larger than the diameter of the through hole for front and back conduction. Specifically, the wall of the through hole and the wall of the metal plate clearance hole or slit hole are 50 μm.
It is preferable that the distance of at least m is insulated by the thermosetting resin composition. The diameter of the through hole for front / back conduction is not particularly limited, but is preferably 50 to 300 μm.

【００３４】本発明の多層プリント配線板用プリプレグ
を作成する場合、基材に熱硬化性樹脂組成物を含浸、乾
燥し、半硬化状態の積層材料とする。また基材を使用し
ない半硬化状態とした樹脂シート、樹脂付き金属箔も使
用できる。或いは塗料も使用できる。この場合、半硬化
状態の程度により、ハイフロー化、ローフロー化、或い
はノーフロー化する。ノーフローとした場合、加熱、加
圧して積層成形した時、樹脂の流れ出しが 100μｍ以
下、好ましくは50μm 以下とする。また、この際、金属
板、金属箔とは接着し、ボイドの発生しないことが肝要
である。一般には、これよりフローの大きいローフロー
プリプレグ、ハイフロープリプレグを使用する。プリプ
レグを作成する温度は一般的には 100〜180 ℃である。
時間は５〜60分であり、目的とするフローの程度によ
り、適宜選択する。When preparing a prepreg for a multilayer printed wiring board of the present invention, a substrate is impregnated with a thermosetting resin composition and dried to obtain a semi-cured laminated material. Further, a resin sheet in a semi-cured state without using a base material and a metal foil with a resin can also be used. Alternatively, paints can be used. In this case, depending on the degree of the semi-cured state, high flow, low flow, or no flow is achieved. In the case of no flow, the flow of resin is 100 μm or less, preferably 50 μm or less when laminating by heating and pressing. At this time, it is important that the metal plate and the metal foil adhere to each other and no void is generated. Generally, a low-flow prepreg and a high-flow prepreg having larger flows are used. The temperature at which the prepreg is made is generally between 100 and 180 ° C.
The time is 5 to 60 minutes, and is appropriately selected depending on the desired flow rate.

【００３５】本発明で得られた異形金属芯の入った半導
体プラスチックパッケージを作成する方法は特に限定し
ないが、例えば以下（図１）の方法による。 (1) 内層となる金属板全面を液状エッチングレジストで
被覆し、加熱して溶剤を除去した後、半導体チップを固
定する表面の凸部のレジスト、及び裏面のクリアランス
ホール部が残るように作成したネガフィルムを被せ、紫
外線照射した後、１％炭酸ナトリウム水溶液で未露光部
分を溶解除去する。 (2) エッチングにて、表面は低圧力、裏面は高圧力で加
工して、表面には半導体チップを搭載する凸部を形成す
ると同時に、裏面からクリアランスホールの上下ほぼ同
じ径の孔があける。The method of producing the semiconductor plastic package containing the deformed metal core obtained in the present invention is not particularly limited, but for example, the following method (FIG. 1). (1) The entire surface of the metal plate serving as the inner layer was coated with a liquid etching resist, and after removing the solvent by heating, the resist was formed so that the resist of the convex portion on the front surface fixing the semiconductor chip and the clearance hole portion on the rear surface remained. After covering with a negative film and irradiating with ultraviolet rays, unexposed portions are dissolved and removed with a 1% aqueous solution of sodium carbonate. (2) By etching, the front surface is processed at a low pressure and the back surface is processed at a high pressure to form a projection for mounting a semiconductor chip on the front surface, and at the same time, holes having substantially the same diameter as a clearance hole are formed from the back surface.

【００３６】(3) エッチングレジストを除去後、金属板
全面を化学表面処理し、金属凸の部分よりやや大きめに
孔をあけたプリプレグを表側に、裏面には孔のあいてい
ないプリプレグを配置し、上下に金属箔を置く。 (4) 加熱、加圧、真空下に積層成形した後、所定の位置
にドリル、或いはレーザー等でスルーホールを内層金属
箔に接触しないようにあけ、デスミア処理を施した後、
金属メッキを行う。 (5) 公知の方法にて上下に回路を作成すると同時に、金
属板凸部の金属箔を除去する。(3) After removing the etching resist, the entire surface of the metal plate is subjected to a chemical surface treatment, and a prepreg having a hole slightly larger than a convex portion of the metal is arranged on the front side, and a prepreg without holes is arranged on the back side. Put metal foil on top and bottom. (4) Heating, pressing, after laminating under vacuum, drilling at a predetermined position, or opening the through-hole with a laser etc. so as not to contact the inner metal foil, and after performing desmear treatment,
Perform metal plating. (5) At the same time as forming circuits up and down by a known method, the metal foil on the metal plate protrusion is removed.

【００３７】(6) ノーフロー、或いはローフロープリプ
レグを、半導体チップ搭載金属露出部分だけザグリマシ
ーンで孔をあけて表面に配置し、裏面にはローフロープ
リプレグ、或いはハイフロープリプレグを配置し、その
上側に18μm の電解銅箔を置く。 (7) これを積層成形し、一体化する。 (8) ドリルにてクリアランスホール部に、内層金属芯に
接触しないように孔あけし、デスミア処理を施し、金属
メッキを施す。 (9) メッキレジストで被覆後、貴金属メッキを施し、内
層金属板の半導体チップ搭載部である凸部の表面に半導
体チップを接着し、ワイヤボンディングを行い、その
後、樹脂封止して、必要によりハンダボールを接着す
る。(6) A no-flow or low-flow prepreg is placed on the surface of the semiconductor chip mounting metal exposed portion by drilling a hole with a counterbore machine, a low-flow prepreg or a high-flow prepreg is placed on the back surface, and Place 18μm electrolytic copper foil. (7) This is laminated and integrated. (8) Drill a hole in the clearance hole so as not to contact the inner layer metal core, apply desmear treatment, and apply metal plating. (9) After coating with a plating resist, apply noble metal plating, bond the semiconductor chip to the surface of the convex portion that is the semiconductor chip mounting portion of the inner metal plate, perform wire bonding, and then seal with resin, if necessary. Glue the solder balls.

【００３８】[0038]

【実施例】以下に実施例、比較例で本発明を具体的に説
明する。尚、特に断らない限り、『部』は重量部を表
す。 実施例１ 2,2-ビス（4-シアナトフェニル）プロパン 900部、ビス
（4-マレイミドフェニル）メタン 100部を 150℃に熔融
させ、撹拌しながら４時間反応させ、プレポリマーを得
た。これをメチルエチルケトンとジメチルホルムアミド
の混合溶剤に溶解した。これにビスフェノールＡ型エポ
キシ樹脂（商品名：エピコート1001、油化シェルエポキ
シ＜株＞製） 400部、クレゾールノボラック型エポキシ
樹脂（商品名：ESCN-220F 、住友化学工業＜株＞製） 6
00部を加え、均一に溶解混合した。更に触媒としてオク
チル酸亜鉛 0.4部を加え、溶解混合し、これに無機充填
剤（商品名：タルクBST200、日本タルク＜株＞製） 500
部を加え、均一撹拌混合してワニスＡを得た。The present invention will be specifically described below with reference to examples and comparative examples. Unless otherwise specified, “parts” indicates parts by weight. Example 1 900 parts of 2,2-bis (4-cyanatophenyl) propane and 100 parts of bis (4-maleimidophenyl) methane were melted at 150 ° C. and reacted with stirring for 4 hours to obtain a prepolymer. This was dissolved in a mixed solvent of methyl ethyl ketone and dimethylformamide. 400 parts of bisphenol A type epoxy resin (trade name: Epicoat 1001, Yuka Shell Epoxy Co., Ltd.) and cresol novolak type epoxy resin (trade name: ESCN-220F, Sumitomo Chemical Co., Ltd.) 6
Then, 00 parts were added and uniformly mixed. Further, 0.4 part of zinc octylate is added as a catalyst, dissolved and mixed, and an inorganic filler (trade name: Talc BST200, manufactured by Nippon Talc Co., Ltd.) 500
Then, varnish A was obtained by uniformly stirring and mixing.

【００３９】このワニスを厚さ 100μｍのガラス織布に
含浸し 150℃で乾燥して、ゲル化時間（at 170℃）７
秒、 170℃、20kgf/cm2 、５分間での樹脂流れ 110μｍ
となるように作成した、厚さ 107μm の半硬化状態のロ
ーフロープリプレグ（プリプレグＢ）を得た。また、ゲ
ル化時間 114秒、樹脂流れ13mm、厚さ 109μｍのハイフ
ロープリプレグＣを作成した。The varnish was impregnated with a glass woven cloth having a thickness of 100 μm, dried at 150 ° C., and gelled for 7 minutes at 170 ° C.
Second, 170 ° C, 20kgf / cm 2 , Resin flow in 5 minutes 110μm
Thus, a semi-cured low flow prepreg (prepreg B) having a thickness of 107 μm was prepared. A high flow prepreg C having a gelation time of 114 seconds, a resin flow of 13 mm, and a thickness of 109 μm was prepared.

【００４０】一方、内層金属板となる厚さ 200μｍの銅
板を用意し、その全面に液状エッチングレジストを厚さ
20μｍ塗布、乾燥した後、表面は凸部の部分のエッチン
グレジストが残るようにし、裏面はクリアランスホール
部のエッチングレジストが除去されるように紫外線を照
射して、１％炭酸ナトリウム溶液で現像後、表面は1.0k
gf/cm2、裏面は2.5kgf/cm2にて同時に両側からエッチン
グし、表面の凸部の大きさ50mm角のパッケージの中央に
13mm角、高さ 100μｍの突起を１個作成し、同時に 0.6
mmφのクリアランスホールをあけた。このクリアランス
ホールの孔径は、上下ほとんど同じであった。On the other hand, a copper plate having a thickness of 200 μm serving as an inner metal plate is prepared, and a liquid etching resist is coated on the entire surface thereof.
After applying and drying 20 μm, the surface is irradiated with ultraviolet rays so that the etching resist in the convex portion remains, and the back surface is irradiated with ultraviolet rays so as to remove the etching resist in the clearance hole portion. After developing with a 1% sodium carbonate solution, The surface is 1.0k
gf / cm 2 , the back side is 2.5kgf / cm 2 at the same time, etched from both sides.
Create one 13mm square, 100μm height projection,
A clearance hole of mmφ was opened. The diameter of the clearance hole was almost the same in the upper and lower portions.

【００４１】金属板全面に黒色酸化銅処理を施し、この
表面には、凸部に相当する位置に、凸部より50μｍ大き
めの孔をルーターにてあけた上記プリプレグＢを被せ、
裏面にはプリプレグＣを配置し、その両外側に厚さ12μ
m の電解銅箔を配置し、 200℃、20kgf/cm2 、30mmHg以
下の真空下で２時間積層成形し、一体化した。クリアラ
ンスホール箇所は、クリアランスホール部の金属に接触
しないように、中央に孔径0.25mmのスルーホールをドリ
ルにてあけ、放熱用スルーホールを４隅内層金属板と接
続してあけ、デスミア処理後、銅メッキを無電解、電解
メッキで行い、孔内に17μｍの銅メッキ層を形成した。The entire surface of the metal plate was subjected to a black copper oxide treatment, and the surface was covered with the prepreg B having a hole 50 μm larger than the protrusion by a router at a position corresponding to the protrusion,
Prepreg C is placed on the back, and 12μ thick on both sides
m of electrolytic copper foil was placed, laminated and molded at 200 ° C., 20 kgf / cm 2 , and a vacuum of 30 mmHg or less for 2 hours, and integrated. Drill a 0.25mm diameter through hole in the center of the clearance hole so that it does not come in contact with the metal in the clearance hole, connect the through holes for heat dissipation to the four corner inner layer metal plates, and after desmearing, Copper plating was performed by electroless and electrolytic plating to form a 17 μm copper plating layer in the hole.

【００４２】表裏に液状エッチングレジストを塗布、乾
燥してからポジフィルムを重ねて露光、現像し、表裏回
路を形成するとともに、凸部上の銅箔も同時にエッチン
グ除去し、次いで凸部、ボンディングパッド及びボール
パッド以外にメッキレジストを形成し、ニッケル、金メ
ッキを施してプリント配線板Ｄを完成した。表面凸部に
大きさ13mm角の半導体チップを銀ペーストで接着固定し
た後、ワイヤボンディングを行い、次いでシリカ入りエ
ポキシ封止用液状樹脂を用い、半導体チップ、ワイヤ、
ボンディングパッド部を樹脂封止して半導体パッケージ
を作成した（図１）。このパッケージの評価結果を表１
に示す。A liquid etching resist is coated on the front and back, dried, and then a positive film is overlaid and exposed and developed to form a front and back circuit. At the same time, the copper foil on the protrusion is removed by etching. Then, a plating resist was formed on portions other than the ball pads, and nickel and gold plating were performed to complete the printed wiring board D. After bonding and fixing a 13 mm square semiconductor chip on the surface convex part with silver paste, wire bonding is performed, and then using a silica-containing epoxy sealing liquid resin, the semiconductor chip, wires,
A semiconductor package was prepared by resin-sealing the bonding pad portion (FIG. 1). Table 1 shows the evaluation results of this package.
Shown in

【００４３】比較例１ 実施例１のプリプレグＣを２枚使用し、上下に12μｍの
電解銅箔を配置し、 200℃、20kgf/cm2 、真空下に２時
間積層成形し、両面銅張積層板を得た。所定の位置に孔
径0.25mmφのスルーホールをドリルであけ、デスミア処
理後に銅メッキを施した。この板の上下に公知の方法で
回路を形成し、ニッケルメッキ、金メッキを施した。こ
れは半導体チップを搭載する箇所に放熱用のスルーホー
ルが形成されており、この上に銀ペーストで半導体チッ
プを接着し、ワイヤボンディング後、エポキシ封止用コ
ンパウンドで実施例１と同様に樹脂封止した（図２）。
このパッケージの評価結果を表１に示す。Comparative Example 1 Two prepregs C of Example 1 were used, and 12 μm electrolytic copper foils were arranged on the upper and lower sides, and laminated and molded at 200 ° C., 20 kgf / cm 2 under vacuum for 2 hours. I got a board. A through hole having a hole diameter of 0.25 mmφ was drilled at a predetermined position, and copper plating was performed after desmear treatment. Circuits were formed on and under the plate by a known method, and nickel plating and gold plating were performed. This has a through hole for heat dissipation formed at the place where the semiconductor chip is mounted. The semiconductor chip is adhered on this with a silver paste, and after wire bonding, it is sealed with a resin for epoxy sealing in the same manner as in Example 1. Stopped (FIG. 2).
Table 1 shows the evaluation results of this package.

【００４４】比較例２ エポキシ樹脂（商品名：エピコート5045）1700部、及び
エポキシ樹脂（商品名：ESCN220F） 300部、ジシアンジ
アミド 35部、2-エチル-4- メチルイミダゾール２部を
メチルエチルケトンとジメチルホルムアミドの混合溶剤
に溶解し、これを厚さ 100μｍのガラス織布に含浸、乾
燥させて、ゲル化時間15秒、樹脂流れ 120μｍのローフ
ロープリプレグＤを作成した。また、ゲル化時間 150
秒、樹脂流れ18mmのハイフロープリプレグＥを作成し
た。Comparative Example 2 1700 parts of an epoxy resin (trade name: Epicoat 5045), 300 parts of an epoxy resin (trade name: ESCN220F), 35 parts of dicyandiamide, and 2 parts of 2-ethyl-4-methylimidazole were prepared by mixing methyl ethyl ketone and dimethylformamide. The resin was dissolved in a mixed solvent, impregnated into a glass woven fabric having a thickness of 100 μm, and dried to prepare a low flow prepreg D having a gelation time of 15 seconds and a resin flow of 120 μm. Gelation time 150
In seconds, a high flow prepreg E having a resin flow of 18 mm was prepared.

【００４５】プリプレグＥを２枚使用し、 190℃、20kg
f/cm2 、30mmHg以下の真空下で２時間積層成形し、両面
銅張積層板を作成した。後は比較例１は同様にしてプリ
ント配線板を作成し、半導体チップ搭載部分をザグリマ
シーンにてくり抜き、裏面に厚さ 200μm の銅板を上記
プリプレグＤを打ち抜いたものを使用して、加熱、加圧
下に同様に接着させ、放熱板付きプリント配線板を作成
した。これはややそりが発生した。この放熱板に直接銀
ペーストで半導体チップを接着させ、ワイヤボンディン
グで接続後、液状エポキシ樹脂封止剤で封止した（図
３）。このパッケージの評価結果を表１に示す。Using two pieces of prepreg E, 190 ° C., 20 kg
Laminate molding was performed for 2 hours under a vacuum of f / cm 2 and 30 mmHg or less to prepare a double-sided copper-clad laminate. Thereafter, in Comparative Example 1, a printed wiring board was prepared in the same manner, a semiconductor chip mounting portion was cut out with a counterbore machine, and a copper plate having a thickness of 200 μm was punched out from the back side using a prepreg D, and heated and heated. In the same manner, the printed circuit board with the heat radiating plate was made to adhere under pressure. This caused a slight sled. A semiconductor chip was directly bonded to the heat sink with a silver paste, connected by wire bonding, and then sealed with a liquid epoxy resin sealant (FIG. 3). Table 1 shows the evaluation results of this package.

【００４６】比較例３ 実施例１の内層金属芯を、エッチングする場合、表裏面
の両側から、圧力２kgf/cm2 でエッチングを行なった。
得られた金属板のクリアランスホールは、表面の孔径
0.3mmφ、裏面の孔径 0.6mmφであり、均一に表裏があ
かず、0.25mmφの孔をあけたときに、67％のスルーホー
ルが内層金属芯と接触していた。Comparative Example 3 When the inner metal core of Example 1 was etched, etching was performed from both sides of the front and back surfaces at a pressure of 2 kgf / cm 2 .
The clearance hole of the obtained metal plate has a hole diameter on the surface.
0.3 mmφ, the hole diameter on the back was 0.6 mmφ, and the front and back were not evenly formed. When a hole of 0.25 mmφ was drilled, 67% of the through holes were in contact with the inner metal core.

【００４７】[0047]

【表１】 実施例１ 比較例１ 比較例２ 吸湿後の耐熱性(1) 常態 異常なし 異常なし 異常なし 72hrs 異常なし 異常なし 異常なし 96hrs 異常なし 異常なし 一部剥離 120hrs 異常なし 一部剥離 一部剥離 168hrs 異常なし 一部剥離 一部剥離 吸湿後の耐熱性(2) 常態 異常なし 異常なし 異常なし 24hrs 異常なし 一部剥離 一部剥離 48hrs 異常なし 剥離大 剥離大 72hrs 異常なし ワイヤ 切れ ワイヤ 切れ 96hrs 異常なし ワイヤ 切れ ワイヤ 切れ 168hrs 異常なし − − ガラス転移温度 (℃) ２３４ ２３５ １６０ プレッシャークッ 常態 ４×1014 − ６×1014 カー処理後の絶縁 200hrs ６×1012 − ２×1011 抵抗値 （Ω） 500hrs ５×1011 − ＜ 108 700hrs ８×1010 − − 1000hrs ６×1010 − − 耐マイグレーシ 常態 ５×1013 − ２×1013 ョン性 200hrs ６×1011 − ７×109 （Ω） 500hrs ５×1011 − ＜ 108 700hrs ９×1010 − − 1000hrs ６×1010 − − 放熱性 (℃) ３７ ５５ ４８ [Table 1] Example 1 Comparative example 1 Comparative example 2 Heat resistance after moisture absorption (1) Normal condition No abnormality No abnormality No abnormality No abnormality 72hrs No abnormality No abnormality No abnormality 96hrs No abnormality No abnormality Partial peeling 120hrs No abnormality Partial peeling Partial peeling 168 hrs No abnormality Partial peeling Partial peeling Heat resistance after moisture absorption (2) Normal No abnormality No abnormality No abnormality No abnormality 24 hrs No abnormality Partial peeling Partial peeling 48 hrs No abnormality Large peeling Large peeling 72 hrs No abnormality Wire break Wire break 96 hrs No abnormalities Wire breaks Wire breaks 168hrs No abnormalities-- Glass transition temperature (℃) 234 235 160 Pressure cooker Normal 4 × 10 14 −6 × 10 14 Insulation after car treatment 200hrs 6 × 10 12 −2 × 10 11 Resistance value ( Ω) 500hrs 5 × 10 11 - <10 8 700hrs 8 × 10 10 - - 1000hrs 6 × 10 10 - - anti-migrating normal 5 × 10 13 - 2 × 10 13 tio emission properties 200hrs 6 × 10 11 - 7 × 10 9 (Ω) 500hrs 5 × 10 11 − <10 8 700 hrs 9 × 10 10 − − 1000 hrs 6 × 10 10 − − Heat dissipation (° C) 37 55 48

【００４８】＜測定方法＞ （1)吸湿後の耐熱性1) JEDEC STANDARD TEST METHOD A113-A LEVEL3：30℃・60
％RHで所定時間処理後、 220℃リフローソルダー３サイ
クル後の基板の異常の有無について、断面観察及び電気
的チェックによって確認した。 （2)吸湿後の電気絶縁性2) JEDEC STANDARD TEST METHOD A113-A LEVEL2：85℃・60
％RHで所定時間（Max.168hrs. ）処理後、 220℃リフロ
ーソルダー３サイクル後の基板の異常の有無を断面観察
及び電気的チェックによって確認した。 （3)ガラス転移温度 DMA 法にて測定した。<Measurement method> (1) Heat resistance after moisture absorption 1) JEDEC STANDARD TEST METHOD A113-A LEVEL3: 30 ° C, 60
After the treatment at% RH for a predetermined time, the substrate was checked for abnormalities after 3 cycles of reflow soldering at 220 ° C. by cross-sectional observation and electrical check. (2) Electrical insulation after moisture absorption 2) JEDEC STANDARD TEST METHOD A113-A LEVEL2: 85 ℃ ・ 60
After treatment at% RH for a predetermined time (Max. 168 hrs.), The presence or absence of abnormality in the substrate after three cycles of reflow soldering at 220 ° C. was confirmed by cross-sectional observation and electrical check. (3) Glass transition temperature Measured by the DMA method.

【００４９】（4)プレッシャークッカー処理後の絶縁抵
抗値 端子間70／70μｍの櫛形パターンを作成し、この上に、
それぞれ使用したプリプレグを配置して、同様に積層成
形したものを、 121℃・２気圧で所定時間処理した後、
25℃・60％RHで２時間処理し、500VDCを印加60秒後に、
その端子間の絶縁抵抗値を測定した。 （5)耐マイグレーション性 （4)の試験片を用い、85℃・85％RH、50VDC 印加して端
子間の絶縁抵抗値を測定した。 （6)放熱性 パッケージを同一マザーボードプリント配線板にハンダ
ボールで接着させ、1000時間連続使用してから、パッケ
ージの温度を測定した。(4) Insulation resistance value after pressure cooker treatment A comb-shaped pattern of 70/70 μm between terminals was created.
After laying out the prepregs used in each case and laminating them in the same manner, treating them at 121 ° C. and 2 atm for a predetermined time,
Treat at 25 ℃ ・ 60% RH for 2 hours, apply 500VDC for 60 seconds,
The insulation resistance between the terminals was measured. (5) Migration resistance Using the test piece of (4), insulation resistance between terminals was measured by applying 50 VDC at 85 ° C. and 85% RH. (6) Heat dissipation The package was adhered to the same motherboard printed wiring board with solder balls and used continuously for 1000 hours, and then the temperature of the package was measured.

【００５０】[0050]

【発明の効果】少なくとも１個以上の半導体チップを、
熱伝導性接着剤で直接固定するための金属凸部分と、表
裏導通孔形成のためのクリアランスホール、又はスリッ
ト孔が形成されている金属板の表裏に、該金属板の凸部
分を避けて、半硬化状態の熱硬化性樹脂組成物プリプレ
グ或いは熱硬化性樹脂フィルムを配置し、さらに、その
外側に金属箔を配置し、加熱、加圧下に作成する半導体
プラスチックパッケージ用の金属芯入り両面金属箔張積
層板の金属芯の製造方法であって、金属平板の片面の一
部分に凸部形成用エッチングレジストを配置し、反対面
にはクリアランスホール或いはスリット孔をエッチング
で形成するためのエッチングレジストを配置し、エッチ
ング工程で凸部形成面には、より低圧力でエッチング液
を吹きかけ、反対面には、より高圧力でエッチング液を
吹きかけることにより、凸部分とクリアランスホール或
いはスリット孔を同時に形成することにより、特に、金
属芯の表裏部の孔部の径がほぼ同じものを作成する事が
可能となり、スルーホール形成時のスルーホール壁と金
属芯の接触のない、信頼性に優れたプリント配線板を作
成することができた。この得られた半導体プラスチック
パッケージは、発生した熱の金属板を通して逃げる構造
であり、半導体チップの下面からの吸湿がなく、吸湿後
の耐熱性、すなわちポップコーン現象が大幅に改善でき
るとともに、熱放散性も改善でき、加えて大量生産性に
も適しており、経済性の改善されたものを得ることがで
きた。According to the present invention, at least one or more semiconductor chips are
A metal convex portion for directly fixing with a heat conductive adhesive, a clearance hole for forming a front and back conduction hole, or a metal plate on which a slit hole is formed, avoiding the convex portion of the metal plate, A semi-cured thermosetting resin composition prepreg or thermosetting resin film is arranged, and a metal foil is arranged outside the thermosetting resin composition prepreg. A method for producing a metal core of a laminated laminate, wherein an etching resist for forming a convex portion is disposed on a part of one surface of a metal flat plate, and an etching resist for forming a clearance hole or a slit hole by etching is disposed on the opposite surface. Then, in the etching process, the etching liquid is sprayed at a lower pressure on the projection forming surface, and the etching liquid is sprayed on the opposite surface at a higher pressure. In addition, by forming the convex portion and the clearance hole or the slit hole at the same time, it is possible to create a metal core having substantially the same diameter of the hole portion on the front and back portions of the metal core. A highly reliable printed wiring board without contact of the metal core could be produced. The resulting semiconductor plastic package has a structure in which the generated heat escapes through the metal plate.There is no moisture absorption from the lower surface of the semiconductor chip, and the heat resistance after moisture absorption, that is, the popcorn phenomenon can be greatly improved, and the heat dissipation property is improved. In addition, it was suitable for mass productivity, and an economically improved product was obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図１】実施例１の金属芯の製造工程である。FIG. 1 shows a manufacturing process of a metal core of Example 1.

【図２】実施例１の金属芯を使用した両面銅張積層板及
び半導体プラスチックパッケージの製造工程である。FIG. 2 shows a manufacturing process of a double-sided copper-clad laminate and a semiconductor plastic package using the metal core of Example 1.

【図３】比較例１の半導体プラスチックパッケージの製
造工程である。FIG. 3 shows a manufacturing process of the semiconductor plastic package of Comparative Example 1.

【図４】比較例２の半導体プラスチックパッケージの製
造工程である。FIG. 4 shows a manufacturing process of the semiconductor plastic package of Comparative Example 2.

【符号の説明】[Explanation of symbols]

ａ：エッチングレジスト、ｂ：金属板、ｃ：クリアラン
スホール、ｄ：片面回路形成銅張積層板、ｅ：ローフロ
ープリプレグＢ、ｆ：金属箔、ｇ：ハイフロープリプレ
グＣ、ｈ：表裏回路導通用スルーホール、ｉ：半導体チ
ップ、ｊ：ボンディングワイヤ、ｋ：銀ペースト、ｌ：
ハンダボール、ｍ：メッキレジスト、ｎ：封止樹脂、
ｏ：放熱用スルーホール、ｐ：ノーフロープリプレグＤa: etching resist, b: metal plate, c: clearance hole, d: single-sided circuit-formed copper-clad laminate, e: low-flow prepreg B, f: metal foil, g: high-flow prepreg C, h: front and back circuit conduction through Hole, i: semiconductor chip, j: bonding wire, k: silver paste, l:
Solder ball, m: plating resist, n: sealing resin,
o: Through hole for heat radiation, p: No-flow prepreg D

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】 少なくとも１個の半導体チップを熱伝導
性接着剤で直接固定するための金属凸部分と、表裏導通
孔形成のためのクリアランスホール、又はスリット孔が
形成されている金属板の表裏に、必要により該金属板の
凸部分を避けて、半硬化状態の熱硬化性樹脂組成物プリ
プレグ或いは熱硬化性樹脂フィルムを配置し、さらに、
その外側に金属箔を配置し、加熱、加圧下に作成する半
導体プラスチックパッケージ用の金属芯入り両面金属箔
張積層板の金属芯の製造方法であって、金属平板の片面
の一部分に凸部形成用エッチングレジストを配置し、反
対面にはクリアランスホール或いはスリット孔をエッチ
ングで形成するためのエッチングレジストを配置し、エ
ッチング工程で凸部形成面には、より低圧力でエッチン
グ液を吹きかけ、反対面には、より高圧力でエッチング
液を吹きかけることにより、凸部分とクリアランスホー
ル或いはスリット孔を同時に形成することを特徴とする
片面凸形状金属芯入り両面金属箔張積層板用の金属芯の
製造方法。1. A metal plate for directly fixing at least one semiconductor chip with a heat conductive adhesive, and a front and back surface of a metal plate in which a clearance hole for forming a front and back conduction hole or a slit hole is formed. In order to avoid the convex portion of the metal plate as necessary, a thermosetting resin composition prepreg or a thermosetting resin film in a semi-cured state is arranged, and further,
A method for producing a metal core of a double-sided metal foil-clad laminate with a metal core for a semiconductor plastic package, wherein a metal foil is placed under the metal foil and heated and pressurized, wherein a convex portion is formed on a part of one surface of the metal flat plate. An etching resist for forming a clearance hole or a slit hole by etching is arranged on the opposite surface, and an etching solution is sprayed at a lower pressure on the convex portion forming surface in the etching process, and the opposite surface is formed. A method for producing a metal core for a double-sided metal foil-clad laminate containing a metal core with a single-sided convex shape, wherein a convex portion and a clearance hole or a slit hole are simultaneously formed by spraying an etching solution at a higher pressure. . 【請求項２】 該金属板が銅９５重量％以上の銅合金或
いは純銅である請求項１に記載の金属芯の製造方法。2. The method for producing a metal core according to claim 1, wherein said metal plate is a copper alloy or pure copper containing 95% by weight or more of copper.
JP10038917A 1997-12-10 1998-02-20 Manufacture of metal core Pending JPH11238827A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP10038917A JPH11238827A (en) 1998-02-20 1998-02-20 Manufacture of metal core
US09/207,115 US6376908B1 (en) 1997-12-10 1998-12-08 Semiconductor plastic package and process for the production thereof
EP98310022A EP0926729A3 (en) 1997-12-10 1998-12-08 Semiconductor plastic package and process for the production thereof
KR1019980054122A KR19990062959A (en) 1997-12-10 1998-12-10 Semiconductor plastic package and manufacturing method thereof
US10/036,385 US6720651B2 (en) 1997-12-10 2002-01-07 Semiconductor plastic package and process for the production thereof
US10/790,039 US20040171189A1 (en) 1997-12-10 2004-03-02 Semiconductor plastic package and process for the production thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10038917A JPH11238827A (en) 1998-02-20 1998-02-20 Manufacture of metal core

Publications (1)

Publication Number Publication Date
JPH11238827A true JPH11238827A (en) 1999-08-31

Family

ID=12538575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10038917A Pending JPH11238827A (en) 1997-12-10 1998-02-20 Manufacture of metal core

Country Status (1)

Country Link
JP (1) JPH11238827A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2005094144A1 (en) * 2004-03-29 2008-02-14 三洋電機株式会社 Circuit device and manufacturing method thereof
JP2009033199A (en) * 2008-10-17 2009-02-12 Denka Agsp Kk Light emitting element mounting substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2005094144A1 (en) * 2004-03-29 2008-02-14 三洋電機株式会社 Circuit device and manufacturing method thereof
JP4722836B2 (en) * 2004-03-29 2011-07-13 三洋電機株式会社 Circuit device and manufacturing method thereof
JP2009033199A (en) * 2008-10-17 2009-02-12 Denka Agsp Kk Light emitting element mounting substrate

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